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Subversion Repositories usb_fpga_2_13

[/] [usb_fpga_2_13/] [trunk/] [include/] [ztex-fpga3.h] - Blame information for rev 2

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/*!
   ZTEX Firmware Kit for EZ-USB FX2 Microcontrollers
   Copyright (C) 2009-2014 ZTEX GmbH.
   http://www.ztex.de
 
   This program is free software; you can redistribute it and/or modify
   it under the terms of the GNU General Public License version 3 as
   published by the Free Software Foundation.
 
   This program is distributed in the hope that it will be useful, but
   WITHOUT ANY WARRANTY; without even the implied warranty of
   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
   General Public License for more details.
 
   You should have received a copy of the GNU General Public License
   along with this program; if not, see http://www.gnu.org/licenses/.
!*/
 
/*
    FPGA support for ZTEX USB FPGA Modules 1.11
*/
 
#ifndef[ZTEX_FPGA_H]
#define[ZTEX_FPGA_H]
 
#define[@CAPABILITY_FPGA;]
 
__xdata BYTE fpga_checksum;         // checksum
__xdata DWORD fpga_bytes;           // transfered bytes
__xdata BYTE fpga_init_b;           // init_b state (should be 222 after configuration)
__xdata BYTE fpga_flash_result;     // result of automatic fpga configuarion from Flash
 
/* *********************************************************************
   ***** reset_fpga ****************************************************
   ********************************************************************* */
static void reset_fpga_int (BYTE mode) {                // reset FPGA
    unsigned short k;
    IFCONFIG = bmBIT7;
    SYNCDELAY;
    PORTACFG = 0;
    PORTCCFG = 0;
 
    OEA = bmBIT1 | bmBIT3 | bmBIT4 | bmBIT5 | bmBIT6 | bmBIT7;
    IOA = bmBIT7 | mode;
    wait(10);
 
    OEC &= ~bmBIT3;
 
    IOA = bmBIT1 | mode;                                // ready for configuration
    k=0;
    while (!IOA0 && k<65535)
        k++;
 
    fpga_init_b = IOA0 ? 200 : 100;
    fpga_bytes = 0;
    fpga_checksum = 0;
}
 
static void reset_fpga () {
    reset_fpga_int(bmBIT5);
}
 
static void reset_fpga_flash () {
    reset_fpga_int(bmBIT5 | bmBIT6);
}
 
/* *********************************************************************
   ***** init_fpga_configuration ***************************************
   ********************************************************************* */
static void init_fpga_configuration () {
    {
        PRE_FPGA_RESET
    }
    reset_fpga();                       // reset FPGA
}
 
/* *********************************************************************
   ***** post_fpga_confog **********************************************
   ********************************************************************* */
static void post_fpga_config () {
    POST_FPGA_CONFIG
}
 
/* *********************************************************************
   ***** finish_fpga_configuration *************************************
   ********************************************************************* */
static void finish_fpga_configuration () {
    BYTE w;
    fpga_init_b += IOA0 ? 20 : 10;
 
    for ( w=0; w<64; w++ ) {
        IOA3 = 1; IOA3 = 0;
    }
    IOA7 = 1;
    IOA3 = 1; IOA3 = 0;
    IOA3 = 1; IOA3 = 0;
    IOA3 = 1; IOA3 = 0;
    IOA3 = 1; IOA3 = 0;
 
    OEA = OEA & 5;
    fpga_init_b += IOA0 ? 2 : 1;
    if ( IOA1 )  {
        IOA1 = 1;
        post_fpga_config();
    }
 
    IOA1 = 1;
    OEA |= bmBIT1;
}
 
 
/* *********************************************************************
   ***** EP0 vendor request 0x30 ***************************************
   ********************************************************************* */
ADD_EP0_VENDOR_REQUEST((0x30,,          // get FPGA state
    MEM_COPY1(fpga_checksum,EP0BUF+1,7);
    OEA &= ~bmBIT1;
    if ( IOA1 )  {
        EP0BUF[0] = 0;                    // FPGA configured 
        IOA1 = 1;
        OEA |= bmBIT1;
    }
    else {
        EP0BUF[0] = 1;                   // FPGA unconfigured 
        reset_fpga();                   // prepare FPGA for configuration
    }
    EP0BUF[8] = 1;                      // bit order for bitstream in Flash memory: swapped
 
    EP0BCH = 0;
    EP0BCL = 9;
,,));;
 
 
/* *********************************************************************
   ***** EP0 vendor command 0x31 ***************************************
   ********************************************************************* */
ADD_EP0_VENDOR_COMMAND((0x31,,init_fpga_configuration();,,));;  // reset FPGA
 
 
/* *********************************************************************
   ***** EP0 vendor command 0x32 ***************************************
   ********************************************************************* */
void fpga_send_ep0() {
    BYTE oOED;
    oOED = OED;
    OED = 255;
    fpga_bytes += ep0_payload_transfer;
    __asm
        mov     dptr,#_EP0BCL
        movx    a,@dptr
        jz      010000$
        mov     r2,a
        mov     _AUTOPTRL1,#(_EP0BUF)
        mov     _AUTOPTRH1,#(_EP0BUF >> 8)
        mov     _AUTOPTRSETUP,#0x07
        mov     dptr,#_fpga_checksum
        movx    a,@dptr
        mov     r1,a
        mov     dptr,#_XAUTODAT1
010001$:
        movx    a,@dptr                 // 2
        mov     _IOD,a                  // 2
        setb    _IOA3                   // 2
        add     a,r1                    // 1
        mov     r1,a                    // 1
        clr     _IOA3                   // 2
        djnz    r2, 010001$             // 4
 
        mov     dptr,#_fpga_checksum
        mov     a,r1
        movx    @dptr,a
 
010000$:
        __endasm;
    OED = oOED;
    if ( EP0BCL<64 ) {
        finish_fpga_configuration();
    }
}
 
ADD_EP0_VENDOR_COMMAND((0x32,,          // send FPGA configuration data
,,
    fpga_send_ep0();
));;
 
 
#ifeq[FLASH_BITSTREAM_ENABLED][1]
#ifeq[FLASH_ENABLED][1]
 
/* *********************************************************************
   ***** fpga_send_bitstream_from_flash ********************************
   ********************************************************************* */
void fpga_send_bitstream_from_flash (WORD size) {
        size;                   // this avoids stupid warnings
__asm
        push    _OED
        mov     _OED,#0
 
        mov     r5,dpl          // = size
        mov     r6,dph
 
        // fpga_bytes+=size
        mov     dptr,#_fpga_bytes
        movx    a,@dptr
        mov     r1,a
        inc     dptr
        movx    a,@dptr
        mov     r2,a
        inc     dptr
        movx    a,@dptr
        mov     r3,a
        inc     dptr
        movx    a,@dptr
        mov     r4,a
 
        mov     dptr,#_fpga_bytes
        mov     a,r5
        add     a,r1
        movx    @dptr,a
        mov     a,r6
        addc    a,r2
        inc     dptr
        movx    @dptr,a
        mov     a,#0
        addc    a,r3
        inc     dptr
        movx    @dptr,a
        mov     a,#0
        addc    a,r4
        inc     dptr
        movx    @dptr,a
 
010003$:
        cjne    r5,#0x00,010002$        // 4
        cjne    r6,#0x00,010002$
        pop     _OED
        ret
010002$:                                // approx 69*4 cycles per byte
        setb    _IOA3  // 2
        setb    _IOC6  // 2
        clr     _IOA3  // 2
        clr     _IOC6  // 2
 
        setb    _IOA3
        setb    _IOC6
        clr     _IOA3
        clr     _IOC6
 
        setb    _IOA3
        setb    _IOC6
        clr     _IOA3
        clr     _IOC6
 
        setb    _IOA3
        setb    _IOC6
        clr     _IOA3
        clr     _IOC6
 
        setb    _IOA3
        setb    _IOC6
        clr     _IOA3
        clr     _IOC6
 
        setb    _IOA3
        setb    _IOC6
        clr     _IOA3
        clr     _IOC6
 
        setb    _IOA3
        setb    _IOC6
        clr     _IOA3
        clr     _IOC6
 
        setb    _IOA3
        setb    _IOC6
        clr     _IOA3
        clr     _IOC6
 
        dec     r5                      // 1
        cjne    r5,#0xff,010003$        // 4
        dec     r6
        sjmp    010003$
__endasm;
}
 
#include[ztex-fpga-flash1.h]
 
#else
#warning[Flash interface is not enabled but required for FPGA configuration using a bitstream from Flash meomory]
#define[FLASH_BITSTREAM_ENABLED][0]
#endif
#endif
 
#endif  /*ZTEX_FPGA_H*/

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Subversion Repositories usb_fpga_2_13

[/] [usb_fpga_2_13/] [trunk/] [include/] [ztex-fpga3.h] - Blame information for rev 2

Line No.	Rev	Author	Line
1	2	ZTEX	`/*!`
2			`ZTEX Firmware Kit for EZ-USB FX2 Microcontrollers`
3			`Copyright (C) 2009-2014 ZTEX GmbH.`
4			`http://www.ztex.de`
5
6			`This program is free software; you can redistribute it and/or modify`
7			`it under the terms of the GNU General Public License version 3 as`
8			`published by the Free Software Foundation.`
9
10			`This program is distributed in the hope that it will be useful, but`
11			`WITHOUT ANY WARRANTY; without even the implied warranty of`
12			`MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU`
13			`General Public License for more details.`
14
15			`You should have received a copy of the GNU General Public License`
16			`along with this program; if not, see http://www.gnu.org/licenses/.`
17			`!*/`
18
19			`/*`
20			`FPGA support for ZTEX USB FPGA Modules 1.11`
21			`*/`
22
23			`#ifndef[ZTEX_FPGA_H]`
24			`#define[ZTEX_FPGA_H]`
25
26			`#define[@CAPABILITY_FPGA;]`
27
28			`__xdata BYTE fpga_checksum; // checksum`
29			`__xdata DWORD fpga_bytes; // transfered bytes`
30			`__xdata BYTE fpga_init_b; // init_b state (should be 222 after configuration)`
31			`__xdata BYTE fpga_flash_result; // result of automatic fpga configuarion from Flash`
32
33			`/* *********************************************************************`
34			`*** reset_fpga **************************************************`
35			`********************************************************************* */`
36			`static void reset_fpga_int (BYTE mode) { // reset FPGA`
37			`unsigned short k;`
38			`IFCONFIG = bmBIT7;`
39			`SYNCDELAY;`
40			`PORTACFG = 0;`
41			`PORTCCFG = 0;`
42
43			`OEA = bmBIT1 \| bmBIT3 \| bmBIT4 \| bmBIT5 \| bmBIT6 \| bmBIT7;`
44			`IOA = bmBIT7 \| mode;`
45			`wait(10);`
46
47			`OEC &= ~bmBIT3;`
48
49			`IOA = bmBIT1 \| mode; // ready for configuration`
50			`k=0;`
51			`while (!IOA0 && k<65535)`
52			`k++;`
53
54			`fpga_init_b = IOA0 ? 200 : 100;`
55			`fpga_bytes = 0;`
56			`fpga_checksum = 0;`
57			`}`
58
59			`static void reset_fpga () {`
60			`reset_fpga_int(bmBIT5);`
61			`}`
62
63			`static void reset_fpga_flash () {`
64			`reset_fpga_int(bmBIT5 \| bmBIT6);`
65			`}`
66
67			`/* *********************************************************************`
68			`*** init_fpga_configuration *************************************`
69			`********************************************************************* */`
70			`static void init_fpga_configuration () {`
71			`{`
72			`PRE_FPGA_RESET`
73			`}`
74			`reset_fpga(); // reset FPGA`
75			`}`
76
77			`/* *********************************************************************`
78			`*** post_fpga_confog ********************************************`
79			`********************************************************************* */`
80			`static void post_fpga_config () {`
81			`POST_FPGA_CONFIG`
82			`}`
83
84			`/* *********************************************************************`
85			`*** finish_fpga_configuration ***********************************`
86			`********************************************************************* */`
87			`static void finish_fpga_configuration () {`
88			`BYTE w;`
89			`fpga_init_b += IOA0 ? 20 : 10;`
90
91			`for ( w=0; w<64; w++ ) {`
92			`IOA3 = 1; IOA3 = 0;`
93			`}`
94			`IOA7 = 1;`
95			`IOA3 = 1; IOA3 = 0;`
96			`IOA3 = 1; IOA3 = 0;`
97			`IOA3 = 1; IOA3 = 0;`
98			`IOA3 = 1; IOA3 = 0;`
99
100			`OEA = OEA & 5;`
101			`fpga_init_b += IOA0 ? 2 : 1;`
102			`if ( IOA1 ) {`
103			`IOA1 = 1;`
104			`post_fpga_config();`
105			`}`
106
107			`IOA1 = 1;`
108			`OEA \|= bmBIT1;`
109			`}`
110
111
112			`/* *********************************************************************`
113			`*** EP0 vendor request 0x30 *************************************`
114			`********************************************************************* */`
115			`ADD_EP0_VENDOR_REQUEST((0x30,, // get FPGA state`
116			`MEM_COPY1(fpga_checksum,EP0BUF+1,7);`
117			`OEA &= ~bmBIT1;`
118			`if ( IOA1 ) {`
119			`EP0BUF[0] = 0; // FPGA configured`
120			`IOA1 = 1;`
121			`OEA \|= bmBIT1;`
122			`}`
123			`else {`
124			`EP0BUF[0] = 1; // FPGA unconfigured`
125			`reset_fpga(); // prepare FPGA for configuration`
126			`}`
127			`EP0BUF[8] = 1; // bit order for bitstream in Flash memory: swapped`
128
129			`EP0BCH = 0;`
130			`EP0BCL = 9;`
131			`,,));;`
132
133
134			`/* *********************************************************************`
135			`*** EP0 vendor command 0x31 *************************************`
136			`********************************************************************* */`
137			`ADD_EP0_VENDOR_COMMAND((0x31,,init_fpga_configuration();,,));; // reset FPGA`
138
139
140			`/* *********************************************************************`
141			`*** EP0 vendor command 0x32 *************************************`
142			`********************************************************************* */`
143			`void fpga_send_ep0() {`
144			`BYTE oOED;`
145			`oOED = OED;`
146			`OED = 255;`
147			`fpga_bytes += ep0_payload_transfer;`
148			`__asm`
149			`mov dptr,#_EP0BCL`
150			`movx a,@dptr`
151			`jz 010000$`
152			`mov r2,a`
153			`mov _AUTOPTRL1,#(_EP0BUF)`
154			`mov _AUTOPTRH1,#(_EP0BUF >> 8)`
155			`mov _AUTOPTRSETUP,#0x07`
156			`mov dptr,#_fpga_checksum`
157			`movx a,@dptr`
158			`mov r1,a`
159			`mov dptr,#_XAUTODAT1`
160			`010001$:`
161			`movx a,@dptr // 2`
162			`mov _IOD,a // 2`
163			`setb _IOA3 // 2`
164			`add a,r1 // 1`
165			`mov r1,a // 1`
166			`clr _IOA3 // 2`
167			`djnz r2, 010001$ // 4`
168
169			`mov dptr,#_fpga_checksum`
170			`mov a,r1`
171			`movx @dptr,a`
172
173			`010000$:`
174			`__endasm;`
175			`OED = oOED;`
176			`if ( EP0BCL<64 ) {`
177			`finish_fpga_configuration();`
178			`}`
179			`}`
180
181			`ADD_EP0_VENDOR_COMMAND((0x32,, // send FPGA configuration data`
182			`,,`
183			`fpga_send_ep0();`
184			`));;`
185
186
187			`#ifeq[FLASH_BITSTREAM_ENABLED][1]`
188			`#ifeq[FLASH_ENABLED][1]`
189
190			`/* *********************************************************************`
191			`*** fpga_send_bitstream_from_flash ******************************`
192			`********************************************************************* */`
193			`void fpga_send_bitstream_from_flash (WORD size) {`
194			`size; // this avoids stupid warnings`
195			`__asm`
196			`push _OED`
197			`mov _OED,#0`
198
199			`mov r5,dpl // = size`
200			`mov r6,dph`
201
202			`// fpga_bytes+=size`
203			`mov dptr,#_fpga_bytes`
204			`movx a,@dptr`
205			`mov r1,a`
206			`inc dptr`
207			`movx a,@dptr`
208			`mov r2,a`
209			`inc dptr`
210			`movx a,@dptr`
211			`mov r3,a`
212			`inc dptr`
213			`movx a,@dptr`
214			`mov r4,a`
215
216			`mov dptr,#_fpga_bytes`
217			`mov a,r5`
218			`add a,r1`
219			`movx @dptr,a`
220			`mov a,r6`
221			`addc a,r2`
222			`inc dptr`
223			`movx @dptr,a`
224			`mov a,#0`
225			`addc a,r3`
226			`inc dptr`
227			`movx @dptr,a`
228			`mov a,#0`
229			`addc a,r4`
230			`inc dptr`
231			`movx @dptr,a`
232
233			`010003$:`
234			`cjne r5,#0x00,010002$ // 4`
235			`cjne r6,#0x00,010002$`
236			`pop _OED`
237			`ret`
238			`010002$: // approx 69*4 cycles per byte`
239			`setb _IOA3 // 2`
240			`setb _IOC6 // 2`
241			`clr _IOA3 // 2`
242			`clr _IOC6 // 2`
243
244			`setb _IOA3`
245			`setb _IOC6`
246			`clr _IOA3`
247			`clr _IOC6`
248
249			`setb _IOA3`
250			`setb _IOC6`
251			`clr _IOA3`
252			`clr _IOC6`
253
254			`setb _IOA3`
255			`setb _IOC6`
256			`clr _IOA3`
257			`clr _IOC6`
258
259			`setb _IOA3`
260			`setb _IOC6`
261			`clr _IOA3`
262			`clr _IOC6`
263
264			`setb _IOA3`
265			`setb _IOC6`
266			`clr _IOA3`
267			`clr _IOC6`
268
269			`setb _IOA3`
270			`setb _IOC6`
271			`clr _IOA3`
272			`clr _IOC6`
273
274			`setb _IOA3`
275			`setb _IOC6`
276			`clr _IOA3`
277			`clr _IOC6`
278
279			`dec r5 // 1`
280			`cjne r5,#0xff,010003$ // 4`
281			`dec r6`
282			`sjmp 010003$`
283			`__endasm;`
284			`}`
285
286			`#include[ztex-fpga-flash1.h]`
287
288			`#else`
289			`#warning[Flash interface is not enabled but required for FPGA configuration using a bitstream from Flash meomory]`
290			`#define[FLASH_BITSTREAM_ENABLED][0]`
291			`#endif`
292			`#endif`
293
294			`#endif /ZTEX_FPGA_H/`