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ZTEX |
project new test.xise
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project set "Device Family" "spartan6"
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project set "Device" "xc6slx16"
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project set "Package" "ftg256"
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project set "Speed Grade" "-2"
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project set "Synthesis Tool" "XST (VHDL/Verilog)"
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project set "Simulator" "ISim (VHDL/Verilog)"
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xfile add "../rtl/example_top.v"
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xfile add "../rtl/infrastructure.v"
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xfile add "../rtl/memc_tb_top.v"
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xfile add "../rtl/memc_wrapper.v"
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xfile add "../rtl/mcb_controller/iodrp_controller.v"
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xfile add "../rtl/mcb_controller/iodrp_mcb_controller.v"
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xfile add "../rtl/mcb_controller/mcb_raw_wrapper.v"
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xfile add "../rtl/mcb_controller/mcb_soft_calibration.v"
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xfile add "../rtl/mcb_controller/mcb_soft_calibration_top.v"
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xfile add "../rtl/mcb_controller/mcb_ui_top.v"
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xfile add "../rtl/traffic_gen/afifo.v"
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xfile add "../rtl/traffic_gen/cmd_gen.v"
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xfile add "../rtl/traffic_gen/cmd_prbs_gen.v"
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xfile add "../rtl/traffic_gen/data_prbs_gen.v"
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xfile add "../rtl/traffic_gen/init_mem_pattern_ctr.v"
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xfile add "../rtl/traffic_gen/mcb_flow_control.v"
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xfile add "../rtl/traffic_gen/mcb_traffic_gen.v"
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xfile add "../rtl/traffic_gen/rd_data_gen.v"
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xfile add "../rtl/traffic_gen/read_data_path.v"
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xfile add "../rtl/traffic_gen/read_posted_fifo.v"
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xfile add "../rtl/traffic_gen/sp6_data_gen.v"
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xfile add "../rtl/traffic_gen/tg_status.v"
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xfile add "../rtl/traffic_gen/v6_data_gen.v"
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xfile add "../rtl/traffic_gen/wr_data_gen.v"
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xfile add "../rtl/traffic_gen/write_data_path.v"
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xfile add "example_top.ucf"
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project set "FSM Encoding Algorithm" "Auto" -process "Synthesize - XST"
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project set "Safe Implementation" "No" -process "Synthesize - XST"
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project set "FSM Style" "LUT" -process "Synthesize - XST"
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project set "RAM Extraction" "True" -process "Synthesize - XST"
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project set "RAM Style" "Auto" -process "Synthesize - XST"
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project set "ROM Extraction" "True" -process "Synthesize - XST"
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project set "ROM Style" "Auto" -process "Synthesize - XST"
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project set "Resource Sharing" "True" -process "Synthesize - XST"
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project set "Asynchronous To Synchronous" "False" -process "Synthesize - XST"
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project set "Register Balancing" "No" -process "Synthesize - XST"
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project set "Add I/O Buffers" "True" -process "Synthesize - XST"
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project set "Max Fanout" "500" -process "Synthesize - XST"
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project set "Number of Clock Buffers" "8" -process "Synthesize - XST"
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project set "Register Duplication" "True" -process "Synthesize - XST"
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project set "Optimize Instantiated Primitives" "False" -process "Synthesize - XST"
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project set "Use Clock Enable" "Yes" -process "Synthesize - XST"
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project set "Use Synchronous Set" "Yes" -process "Synthesize - XST"
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project set "Use Synchronous Reset" "Yes" -process "Synthesize - XST"
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project set "Pack I/O Registers into IOBs" "Auto" -process "Synthesize - XST"
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project set "Equivalent Register Removal" "True" -process "Synthesize - XST"
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project set "Optimization Goal" "Speed" -process "Synthesize - XST"
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project set "Optimization Effort" "Normal" -process "Synthesize - XST"
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project set "Library Search Order" "../synth/example_top.lso" -process "Synthesize - XST"
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project set "Keep Hierarchy" "Soft" -process "Synthesize - XST"
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project set "Netlist Hierarchy" "As Optimized" -process "Synthesize - XST"
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project set "Generate RTL Schematic" "Yes" -process "Synthesize - XST"
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project set "Global Optimization Goal" "AllClockNets" -process "Synthesize - XST"
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project set "Read Cores" "True" -process "Synthesize - XST"
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project set "Write Timing Constraints" "False" -process "Synthesize - XST"
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project set "Cross Clock Analysis" "False" -process "Synthesize - XST"
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project set "Hierarchy Separator" "/" -process "Synthesize - XST"
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project set "Bus Delimiter" "<>" -process "Synthesize - XST"
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project set "Case" "Maintain" -process "Synthesize - XST"
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project set "BRAM Utilization Ratio" "100" -process "Synthesize - XST"
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project set "Automatic BRAM Packing" "False" -process "Synthesize - XST"
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project set "Pack I/O Registers/Latches into IOBs" "Off" -process Map
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project set "Place & Route Effort Level (Overall)" "Standard" -process "Place & Route"
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project set "Number of Paths in Error/Verbose Report" "100" -process "Generate Post-Map Static Timing"
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project set "Enable Debugging of Serial Mode BitStream" "False" -process "Generate Programming File"
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project set "Create Binary Configuration File" "False" -process "Generate Programming File"
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project set "Enable Cyclic Redundancy Checking (CRC)" "True" -process "Generate Programming File"
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project set "Configuration Rate" "6" -process "Generate Programming File"
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project set "Configuration Pin Program" "Pull Up" -process "Generate Programming File"
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project set "Configuration Pin Done" "Pull Up" -process "Generate Programming File"
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project set "JTAG Pin TCK" "Pull Up" -process "Generate Programming File"
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project set "JTAG Pin TDI" "Pull Up" -process "Generate Programming File"
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project set "JTAG Pin TDO" "Pull Up" -process "Generate Programming File"
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project set "JTAG Pin TMS" "Pull Up" -process "Generate Programming File"
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project set "Unused IOB Pins" "Float" -process "Generate Programming File"
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project set "UserID Code (8 Digit Hexadecimal)" "0xFFFFFFFF" -process "Generate Programming File"
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project set "FPGA Start-Up Clock" "CCLK" -process "Generate Programming File"
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project set "Done (Output Events)" "Default (4)" -process "Generate Programming File"
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project set "Enable Outputs (Output Events)" "Default (5)" -process "Generate Programming File"
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project set "Release Write Enable (Output Events)" "Default (6)" -process "Generate Programming File"
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project set "Enable Internal Done Pipe" "False" -process "Generate Programming File"
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project set "Drive Done Pin High" "False" -process "Generate Programming File"
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project set "Security" "Enable Readback and Reconfiguration" -process "Generate Programming File"
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project close
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