Subversion Repositories usb_fpga_2_14

//*****************************************************************************

// (c) Copyright 2009 Xilinx, Inc. All rights reserved.

//

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//*****************************************************************************

//   ____  ____

//  /   /\/   /

// /___/  \  /   Vendor             : Xilinx

// \   \   \/    Version            : 3.92

//  \   \        Application        : MIG

//  /   /        Filename           : sim_tb_top.v

// /___/   /\    Date Last Modified : $Date: 2011/06/02 07:17:00 $

// \   \  /  \   Date Created       : Mon Mar 2 2009

//  \___\/\___\

//

// Device      : Spartan-6

// Design Name : DDR/DDR2/DDR3/LPDDR

// Purpose     : This is the simulation testbench which is used to verify the

//               design. The basic clocks and resets to the interface are

//               generated here. This also connects the memory interface to the

//               memory model.

//*****************************************************************************

`timescale 1ps/1ps

module sim_tb_top;

// ========================================================================== //

// Parameters                                                                 //

// ========================================================================== //

   parameter DEBUG_EN                = 0;

   localparam DBG_WR_STS_WIDTH       = 32;

   localparam DBG_RD_STS_WIDTH       = 32;

   localparam C3_P0_PORT_MODE             =  "BI_MODE";

   localparam C3_P1_PORT_MODE             =  "BI_MODE";

   localparam C3_P2_PORT_MODE             =  "WR_MODE";

   localparam C3_P3_PORT_MODE             =  "RD_MODE";

   localparam C3_P4_PORT_MODE             =  "WR_MODE";

   localparam C3_P5_PORT_MODE             =  "RD_MODE";

   localparam C3_PORT_ENABLE              = 6'b111111;

   localparam C3_PORT_CONFIG             =  "B32_B32_W32_R32_W32_R32";

        parameter C3_MEMCLK_PERIOD     = 5000;

   parameter C3_RST_ACT_LOW        = 0;

   parameter C3_INPUT_CLK_TYPE     = "SINGLE_ENDED";

   parameter C3_NUM_DQ_PINS        = 16;

   parameter C3_MEM_ADDR_WIDTH     = 13;

   parameter C3_MEM_BANKADDR_WIDTH = 2;

   parameter C3_MEM_ADDR_ORDER     = "ROW_BANK_COLUMN";

      parameter C3_P0_MASK_SIZE       = 4;

   parameter C3_P0_DATA_PORT_SIZE  = 32;

   parameter C3_P1_MASK_SIZE       = 4;

   parameter C3_P1_DATA_PORT_SIZE  = 32;

   parameter C3_MEM_BURST_LEN     = 4;

   parameter C3_MEM_NUM_COL_BITS   = 10;

   parameter C3_CALIB_SOFT_IP      = "TRUE";

   parameter C3_SIMULATION      = "TRUE";

   parameter C3_HW_TESTING      = "FALSE";

   parameter C3_SMALL_DEVICE    = "FALSE";

   localparam C3_p0_BEGIN_ADDRESS                   = (C3_HW_TESTING == "TRUE") ? 32'h01000000:32'h00000100;

   localparam C3_p0_DATA_MODE                       = 4'b0010;

   localparam C3_p0_END_ADDRESS                     = (C3_HW_TESTING == "TRUE") ? 32'h02ffffff:32'h000002ff;

   localparam C3_p0_PRBS_EADDR_MASK_POS             = (C3_HW_TESTING == "TRUE") ? 32'hfc000000:32'hfffffc00;

   localparam C3_p0_PRBS_SADDR_MASK_POS             = (C3_HW_TESTING == "TRUE") ? 32'h01000000:32'h00000100;

   localparam C3_p1_BEGIN_ADDRESS                   = (C3_HW_TESTING == "TRUE") ? 32'h03000000:32'h00000300;

   localparam C3_p1_DATA_MODE                       = 4'b0010;

   localparam C3_p1_END_ADDRESS                     = (C3_HW_TESTING == "TRUE") ? 32'h04ffffff:32'h000004ff;

   localparam C3_p1_PRBS_EADDR_MASK_POS             = (C3_HW_TESTING == "TRUE") ? 32'hf8000000:32'hfffff800;

   localparam C3_p1_PRBS_SADDR_MASK_POS             = (C3_HW_TESTING == "TRUE") ? 32'h03000000:32'h00000300;

   localparam C3_p2_BEGIN_ADDRESS                   = (C3_HW_TESTING == "TRUE") ? 32'h05000000:32'h00000500;

   localparam C3_p2_DATA_MODE                       = 4'b0010;

   localparam C3_p2_END_ADDRESS                     = (C3_HW_TESTING == "TRUE") ? 32'h06ffffff:32'h000006ff;

   localparam C3_p2_PRBS_EADDR_MASK_POS             = (C3_HW_TESTING == "TRUE") ? 32'hf8000000:32'hfffff800;

   localparam C3_p2_PRBS_SADDR_MASK_POS             = (C3_HW_TESTING == "TRUE") ? 32'h05000000:32'h00000500;

   localparam C3_p3_BEGIN_ADDRESS                   = (C3_HW_TESTING == "TRUE") ? 32'h01000000:32'h00000100;

   localparam C3_p3_DATA_MODE                       = 4'b0010;

   localparam C3_p3_END_ADDRESS                     = (C3_HW_TESTING == "TRUE") ? 32'h02ffffff:32'h000002ff;

   localparam C3_p3_PRBS_EADDR_MASK_POS             = (C3_HW_TESTING == "TRUE") ? 32'hfc000000:32'hfffffc00;

   localparam C3_p3_PRBS_SADDR_MASK_POS             = (C3_HW_TESTING == "TRUE") ? 32'h01000000:32'h00000100;

   localparam C3_p4_BEGIN_ADDRESS                   = (C3_HW_TESTING == "TRUE") ? 32'h07000000:32'h00000700;

   localparam C3_p4_DATA_MODE                       = 4'b0010;

   localparam C3_p4_END_ADDRESS                     = (C3_HW_TESTING == "TRUE") ? 32'h08ffffff:32'h000008ff;

   localparam C3_p4_PRBS_EADDR_MASK_POS             = (C3_HW_TESTING == "TRUE") ? 32'hf0000000:32'hfffff000;

   localparam C3_p4_PRBS_SADDR_MASK_POS             = (C3_HW_TESTING == "TRUE") ? 32'h07000000:32'h00000800;

   localparam C3_p5_BEGIN_ADDRESS                   = (C3_HW_TESTING == "TRUE") ? 32'h01000000:32'h00000100;

   localparam C3_p5_DATA_MODE                       = 4'b0010;

   localparam C3_p5_END_ADDRESS                     = (C3_HW_TESTING == "TRUE") ? 32'h02ffffff:32'h000002ff;

   localparam C3_p5_PRBS_EADDR_MASK_POS             = (C3_HW_TESTING == "TRUE") ? 32'hfc000000:32'hfffffc00;

   localparam C3_p5_PRBS_SADDR_MASK_POS             = (C3_HW_TESTING == "TRUE") ? 32'h01000000:32'h00000100;

// ========================================================================== //

// Signal Declarations                                                        //

// ========================================================================== //

// Clocks

                // Clocks

   reg                              c3_sys_clk;

   wire                             c3_sys_clk_p;

   wire                             c3_sys_clk_n;

// System Reset

   reg                              c3_sys_rst;

   wire                             c3_sys_rst_i;

// Design-Top Port Map

   wire [31:0]                      c3_cmp_data;

   wire                             c3_cmp_error;

   wire [C3_MEM_ADDR_WIDTH-1:0]     mcb3_dram_a;

   wire [C3_MEM_BANKADDR_WIDTH-1:0] mcb3_dram_ba;

   wire                             mcb3_dram_ck;

   wire                             mcb3_dram_ck_n;

   wire [C3_NUM_DQ_PINS-1:0]        mcb3_dram_dq;

   wire                             mcb3_dram_dqs;

   wire                             mcb3_dram_dm;

   wire                             mcb3_dram_ras_n;

   wire                             mcb3_dram_cas_n;

   wire                             mcb3_dram_we_n;

   wire                             mcb3_dram_cke;

   wire                             c3_error;

   wire                             c3_calib_done;

   wire [64 + (2*C3_P0_DATA_PORT_SIZE - 1):0]     c3_p0_error_status;

   wire [64 + (2*C3_P1_DATA_PORT_SIZE - 1):0]     c3_p1_error_status;

   wire [127 : 0]     c3_p2_error_status;

   wire [127 : 0]     c3_p3_error_status;

   wire [127 : 0]     c3_p4_error_status;

   wire [127 : 0]     c3_p5_error_status;

   wire                              mcb3_dram_udqs;    // for X16 parts

   wire                             mcb3_dram_udm;     // for X16 parts

   wire                              c3_vio_modify_enable   = 1'b1;

   wire  [2:0]                       c3_vio_data_mode_value = 3'b010;

   wire  [2:0]                       c3_vio_addr_mode_value = 3'b011;

// User design  Sim

        wire                             c3_clk0;

   wire                                                  c3_rst0;

   reg                              c3_aresetn;

   wire                              c3_wrap_en;

   wire                              c3_cmd_err;

   wire                              c3_data_msmatch_err;

   wire                              c3_write_err;

   wire                              c3_read_err;

   wire                              c3_test_cmptd;

   wire                              c3_dbg_wr_sts_vld;

   wire                              c3_dbg_rd_sts_vld;

   wire  [DBG_WR_STS_WIDTH-1:0]                      c3_dbg_wr_sts;

   wire  [DBG_WR_STS_WIDTH-1:0]                      c3_dbg_rd_sts;

     wire               c3_p0_cmd_en;

  wire [2:0]     c3_p0_cmd_instr;

  wire [5:0]     c3_p0_cmd_bl;

  wire [29:0]    c3_p0_cmd_byte_addr;

  wire          c3_p0_cmd_empty;

  wire          c3_p0_cmd_full;

  wire          c3_p0_wr_en;

  wire [C3_P0_MASK_SIZE - 1:0]   c3_p0_wr_mask;

  wire [C3_P0_DATA_PORT_SIZE - 1:0]      c3_p0_wr_data;

  wire          c3_p0_wr_full;

  wire          c3_p0_wr_empty;

  wire [6:0]     c3_p0_wr_count;

  wire          c3_p0_wr_underrun;

  wire          c3_p0_wr_error;

  wire          c3_p0_rd_en;

  wire [C3_P0_DATA_PORT_SIZE - 1:0]      c3_p0_rd_data;

  wire          c3_p0_rd_full;

  wire          c3_p0_rd_empty;

  wire [6:0]     c3_p0_rd_count;

  wire          c3_p0_rd_overflow;

  wire          c3_p0_rd_error;

  wire          c3_p1_cmd_en;

  wire [2:0]     c3_p1_cmd_instr;

  wire [5:0]     c3_p1_cmd_bl;

  wire [29:0]    c3_p1_cmd_byte_addr;

  wire          c3_p1_cmd_empty;

  wire          c3_p1_cmd_full;

  wire          c3_p1_wr_en;

  wire [C3_P1_MASK_SIZE - 1:0]   c3_p1_wr_mask;

  wire [C3_P1_DATA_PORT_SIZE - 1:0]      c3_p1_wr_data;

  wire          c3_p1_wr_full;

  wire          c3_p1_wr_empty;

  wire [6:0]     c3_p1_wr_count;

  wire          c3_p1_wr_underrun;

  wire          c3_p1_wr_error;

  wire          c3_p1_rd_en;

  wire [C3_P1_DATA_PORT_SIZE - 1:0]      c3_p1_rd_data;

  wire          c3_p1_rd_full;

  wire          c3_p1_rd_empty;

  wire [6:0]     c3_p1_rd_count;

  wire          c3_p1_rd_overflow;

  wire          c3_p1_rd_error;

  wire          c3_p2_cmd_en;

  wire [2:0]     c3_p2_cmd_instr;

  wire [5:0]     c3_p2_cmd_bl;

  wire [29:0]    c3_p2_cmd_byte_addr;

  wire          c3_p2_cmd_empty;

  wire          c3_p2_cmd_full;

  wire          c3_p2_wr_en;

  wire [3:0]     c3_p2_wr_mask;

  wire [31:0]    c3_p2_wr_data;

  wire          c3_p2_wr_full;

  wire          c3_p2_wr_empty;

  wire [6:0]     c3_p2_wr_count;

  wire          c3_p2_wr_underrun;

  wire          c3_p2_wr_error;

  wire          c3_p3_cmd_en;

  wire [2:0]     c3_p3_cmd_instr;

  wire [5:0]     c3_p3_cmd_bl;

  wire [29:0]    c3_p3_cmd_byte_addr;

  wire          c3_p3_cmd_empty;

  wire          c3_p3_cmd_full;

  wire          c3_p3_rd_en;

  wire [31:0]    c3_p3_rd_data;

  wire          c3_p3_rd_full;

  wire          c3_p3_rd_empty;

  wire [6:0]     c3_p3_rd_count;

  wire          c3_p3_rd_overflow;

  wire          c3_p3_rd_error;

  wire          c3_p4_cmd_en;

  wire [2:0]     c3_p4_cmd_instr;

  wire [5:0]     c3_p4_cmd_bl;

  wire [29:0]    c3_p4_cmd_byte_addr;

  wire          c3_p4_cmd_empty;

  wire          c3_p4_cmd_full;

  wire          c3_p4_wr_en;

  wire [3:0]     c3_p4_wr_mask;

  wire [31:0]    c3_p4_wr_data;

  wire          c3_p4_wr_full;

  wire          c3_p4_wr_empty;

  wire [6:0]     c3_p4_wr_count;

  wire          c3_p4_wr_underrun;

  wire          c3_p4_wr_error;

  wire          c3_p5_cmd_en;

  wire [2:0]     c3_p5_cmd_instr;

  wire [5:0]     c3_p5_cmd_bl;

  wire [29:0]    c3_p5_cmd_byte_addr;

  wire          c3_p5_cmd_empty;

  wire          c3_p5_cmd_full;

  wire          c3_p5_rd_en;

  wire [31:0]    c3_p5_rd_data;

  wire          c3_p5_rd_full;

  wire          c3_p5_rd_empty;

  wire [6:0]     c3_p5_rd_count;

  wire          c3_p5_rd_overflow;

  wire          c3_p5_rd_error;

wire                            c3_p2_rd_clk;

wire                            c3_p2_rd_en;

wire[31:0]                       c3_p2_rd_data;

wire                            c3_p2_rd_full;

wire                            c3_p2_rd_empty;

wire[6:0]                        c3_p2_rd_count;

wire                            c3_p2_rd_overflow;

wire                            c3_p2_rd_error;

wire                            c3_p3_wr_clk;

wire                            c3_p3_wr_en;

wire[3:0]                        c3_p3_wr_mask;

wire[31:0]                       c3_p3_wr_data;

wire                            c3_p3_wr_full;

wire                            c3_p3_wr_empty;

wire[6:0]                        c3_p3_wr_count;

wire                            c3_p3_wr_underrun;

wire                            c3_p3_wr_error;

wire                            c3_p4_rd_clk;

wire                            c3_p4_rd_en;

wire[31:0]                       c3_p4_rd_data;

wire                            c3_p4_rd_full;

wire                            c3_p4_rd_empty;

wire[6:0]                        c3_p4_rd_count;

wire                            c3_p4_rd_overflow;

wire                            c3_p4_rd_error;

wire                            c3_p5_wr_clk;

wire                            c3_p5_wr_en;

wire[3:0]                        c3_p5_wr_mask;

wire[31:0]                       c3_p5_wr_data;

wire                            c3_p5_wr_full;

wire                            c3_p5_wr_empty;

wire[6:0]                        c3_p5_wr_count;

wire                            c3_p5_wr_underrun;

wire                            c3_p5_wr_error;

// Error & Calib Signals

   wire                             error;

   wire                             calib_done;

   wire                             rzq3;

// ========================================================================== //

// Clocks Generation                                                          //

// ========================================================================== //

   initial

      c3_sys_clk = 1'b0;

   always

      #(C3_MEMCLK_PERIOD/2) c3_sys_clk = ~c3_sys_clk;

   assign                c3_sys_clk_p = c3_sys_clk;

   assign                c3_sys_clk_n = ~c3_sys_clk;

// ========================================================================== //

// Reset Generation                                                           //

// ========================================================================== //

   initial begin

      c3_sys_rst = 1'b0;

      #20000;

      c3_sys_rst = 1'b1;

   end

   assign c3_sys_rst_i = C3_RST_ACT_LOW ? c3_sys_rst : ~c3_sys_rst;

// ========================================================================== //

// Error Grouping                                                           //

// ========================================================================== //

assign error = c3_error;

assign calib_done = c3_calib_done;

   PULLDOWN rzq_pulldown3 (.O(rzq3));

// ========================================================================== //

// DESIGN TOP INSTANTIATION                                                    //

// ========================================================================== //

mem0 #(

.C3_P0_MASK_SIZE       (C3_P0_MASK_SIZE      ),

.C3_P0_DATA_PORT_SIZE  (C3_P0_DATA_PORT_SIZE ),

.C3_P1_MASK_SIZE       (C3_P1_MASK_SIZE      ),

.C3_P1_DATA_PORT_SIZE  (C3_P1_DATA_PORT_SIZE ),

.C3_MEMCLK_PERIOD      (C3_MEMCLK_PERIOD),

.C3_RST_ACT_LOW        (C3_RST_ACT_LOW),

.C3_INPUT_CLK_TYPE     (C3_INPUT_CLK_TYPE),

.DEBUG_EN              (DEBUG_EN),

.C3_MEM_ADDR_ORDER     (C3_MEM_ADDR_ORDER    ),

.C3_NUM_DQ_PINS        (C3_NUM_DQ_PINS       ),

.C3_MEM_ADDR_WIDTH     (C3_MEM_ADDR_WIDTH    ),

.C3_MEM_BANKADDR_WIDTH (C3_MEM_BANKADDR_WIDTH),

.C3_SIMULATION         (C3_SIMULATION),

.C3_CALIB_SOFT_IP      (C3_CALIB_SOFT_IP )

)

design_top (

    .c3_sys_clk           (c3_sys_clk),

  .c3_sys_rst_i           (c3_sys_rst_i),

  .mcb3_dram_dq           (mcb3_dram_dq),

  .mcb3_dram_a            (mcb3_dram_a),

  .mcb3_dram_ba           (mcb3_dram_ba),

  .mcb3_dram_ras_n        (mcb3_dram_ras_n),

  .mcb3_dram_cas_n        (mcb3_dram_cas_n),

  .mcb3_dram_we_n         (mcb3_dram_we_n),

  .mcb3_dram_cke          (mcb3_dram_cke),

  .mcb3_dram_ck           (mcb3_dram_ck),

  .mcb3_dram_ck_n         (mcb3_dram_ck_n),

  .mcb3_dram_dqs          (mcb3_dram_dqs),

  .mcb3_dram_udqs         (mcb3_dram_udqs),    // for X16 parts

  .mcb3_dram_udm          (mcb3_dram_udm),     // for X16 parts

  .mcb3_dram_dm           (mcb3_dram_dm),

  .c3_clk0                      (c3_clk0),

  .c3_rst0                      (c3_rst0),

  .c3_calib_done    (c3_calib_done),

     .mcb3_rzq               (rzq3),

     .c3_p0_cmd_clk                          (c3_clk0),

   .c3_p0_cmd_en                           (c3_p0_cmd_en),

   .c3_p0_cmd_instr                        (c3_p0_cmd_instr),

   .c3_p0_cmd_bl                           (c3_p0_cmd_bl),

   .c3_p0_cmd_byte_addr                    (c3_p0_cmd_byte_addr),

   .c3_p0_cmd_empty                        (c3_p0_cmd_empty),

   .c3_p0_cmd_full                         (c3_p0_cmd_full),

   .c3_p0_wr_clk                           (c3_clk0),

   .c3_p0_wr_en                            (c3_p0_wr_en),

   .c3_p0_wr_mask                          (c3_p0_wr_mask),

   .c3_p0_wr_data                          (c3_p0_wr_data),

   .c3_p0_wr_full                          (c3_p0_wr_full),

   .c3_p0_wr_empty                         (c3_p0_wr_empty),

   .c3_p0_wr_count                         (c3_p0_wr_count),

   .c3_p0_wr_underrun                      (c3_p0_wr_underrun),

   .c3_p0_wr_error                         (c3_p0_wr_error),

   .c3_p0_rd_clk                           (c3_clk0),

   .c3_p0_rd_en                            (c3_p0_rd_en),

   .c3_p0_rd_data                          (c3_p0_rd_data),

   .c3_p0_rd_full                          (c3_p0_rd_full),

   .c3_p0_rd_empty                         (c3_p0_rd_empty),

   .c3_p0_rd_count                         (c3_p0_rd_count),

   .c3_p0_rd_overflow                      (c3_p0_rd_overflow),

   .c3_p0_rd_error                         (c3_p0_rd_error),

   .c3_p1_cmd_clk                          (c3_clk0),

   .c3_p1_cmd_en                           (c3_p1_cmd_en),

   .c3_p1_cmd_instr                        (c3_p1_cmd_instr),

   .c3_p1_cmd_bl                           (c3_p1_cmd_bl),

   .c3_p1_cmd_byte_addr                    (c3_p1_cmd_byte_addr),

   .c3_p1_cmd_empty                        (c3_p1_cmd_empty),

   .c3_p1_cmd_full                         (c3_p1_cmd_full),

   .c3_p1_wr_clk                           (c3_clk0),

   .c3_p1_wr_en                            (c3_p1_wr_en),

   .c3_p1_wr_mask                          (c3_p1_wr_mask),

   .c3_p1_wr_data                          (c3_p1_wr_data),

   .c3_p1_wr_full                          (c3_p1_wr_full),

   .c3_p1_wr_empty                         (c3_p1_wr_empty),

   .c3_p1_wr_count                         (c3_p1_wr_count),

   .c3_p1_wr_underrun                      (c3_p1_wr_underrun),

   .c3_p1_wr_error                         (c3_p1_wr_error),

   .c3_p1_rd_clk                           (c3_clk0),

   .c3_p1_rd_en                            (c3_p1_rd_en),

   .c3_p1_rd_data                          (c3_p1_rd_data),

   .c3_p1_rd_full                          (c3_p1_rd_full),

   .c3_p1_rd_empty                         (c3_p1_rd_empty),

   .c3_p1_rd_count                         (c3_p1_rd_count),

   .c3_p1_rd_overflow                      (c3_p1_rd_overflow),

   .c3_p1_rd_error                         (c3_p1_rd_error),

   .c3_p2_cmd_clk                          (c3_clk0),

   .c3_p2_cmd_en                           (c3_p2_cmd_en),

   .c3_p2_cmd_instr                        (c3_p2_cmd_instr),

   .c3_p2_cmd_bl                           (c3_p2_cmd_bl),

   .c3_p2_cmd_byte_addr                    (c3_p2_cmd_byte_addr),

   .c3_p2_cmd_empty                        (c3_p2_cmd_empty),

   .c3_p2_cmd_full                         (c3_p2_cmd_full),

   .c3_p2_wr_clk                           (c3_clk0),

   .c3_p2_wr_en                            (c3_p2_wr_en),

   .c3_p2_wr_mask                          (c3_p2_wr_mask),

   .c3_p2_wr_data                          (c3_p2_wr_data),

   .c3_p2_wr_full                          (c3_p2_wr_full),

   .c3_p2_wr_empty                         (c3_p2_wr_empty),

   .c3_p2_wr_count                         (c3_p2_wr_count),

   .c3_p2_wr_underrun                      (c3_p2_wr_underrun),

   .c3_p2_wr_error                         (c3_p2_wr_error),

   .c3_p3_cmd_clk                          (c3_clk0),

   .c3_p3_cmd_en                           (c3_p3_cmd_en),

   .c3_p3_cmd_instr                        (c3_p3_cmd_instr),

   .c3_p3_cmd_bl                           (c3_p3_cmd_bl),

   .c3_p3_cmd_byte_addr                    (c3_p3_cmd_byte_addr),

   .c3_p3_cmd_empty                        (c3_p3_cmd_empty),

   .c3_p3_cmd_full                         (c3_p3_cmd_full),

   .c3_p3_rd_clk                           (c3_clk0),

   .c3_p3_rd_en                            (c3_p3_rd_en),

   .c3_p3_rd_data                          (c3_p3_rd_data),

   .c3_p3_rd_full                          (c3_p3_rd_full),

   .c3_p3_rd_empty                         (c3_p3_rd_empty),

   .c3_p3_rd_count                         (c3_p3_rd_count),

   .c3_p3_rd_overflow                      (c3_p3_rd_overflow),

   .c3_p3_rd_error                         (c3_p3_rd_error),

   .c3_p4_cmd_clk                          (c3_clk0),

   .c3_p4_cmd_en                           (c3_p4_cmd_en),

   .c3_p4_cmd_instr                        (c3_p4_cmd_instr),

   .c3_p4_cmd_bl                           (c3_p4_cmd_bl),

   .c3_p4_cmd_byte_addr                    (c3_p4_cmd_byte_addr),

   .c3_p4_cmd_empty                        (c3_p4_cmd_empty),

   .c3_p4_cmd_full                         (c3_p4_cmd_full),

   .c3_p4_wr_clk                           (c3_clk0),

   .c3_p4_wr_en                            (c3_p4_wr_en),

   .c3_p4_wr_mask                          (c3_p4_wr_mask),

   .c3_p4_wr_data                          (c3_p4_wr_data),

   .c3_p4_wr_full                          (c3_p4_wr_full),

   .c3_p4_wr_empty                         (c3_p4_wr_empty),

   .c3_p4_wr_count                         (c3_p4_wr_count),

   .c3_p4_wr_underrun                      (c3_p4_wr_underrun),

   .c3_p4_wr_error                         (c3_p4_wr_error),

   .c3_p5_cmd_clk                          (c3_clk0),

   .c3_p5_cmd_en                           (c3_p5_cmd_en),

   .c3_p5_cmd_instr                        (c3_p5_cmd_instr),

   .c3_p5_cmd_bl                           (c3_p5_cmd_bl),

   .c3_p5_cmd_byte_addr                    (c3_p5_cmd_byte_addr),

   .c3_p5_cmd_empty                        (c3_p5_cmd_empty),

   .c3_p5_cmd_full                         (c3_p5_cmd_full),

   .c3_p5_rd_clk                           (c3_clk0),

   .c3_p5_rd_en                            (c3_p5_rd_en),

   .c3_p5_rd_data                          (c3_p5_rd_data),

   .c3_p5_rd_full                          (c3_p5_rd_full),

   .c3_p5_rd_empty                         (c3_p5_rd_empty),

   .c3_p5_rd_count                         (c3_p5_rd_count),

   .c3_p5_rd_overflow                      (c3_p5_rd_overflow),

   .c3_p5_rd_error                         (c3_p5_rd_error)

);

// Test bench top for the controller-3

      memc_tb_top #

      (

         .C_SIMULATION                   (C3_SIMULATION),

         .C_NUM_DQ_PINS                  (C3_NUM_DQ_PINS),

         .C_MEM_BURST_LEN                (C3_MEM_BURST_LEN),

         .C_MEM_NUM_COL_BITS             (C3_MEM_NUM_COL_BITS),

         .C_SMALL_DEVICE                 (C3_SMALL_DEVICE),

         // The following parameters from C_PORT_ENABLE to C_P5_PORT_MODE are introduced

         // to handle the static instances of all the six traffic generators inside the

         // memc_tb_top module. 

         .C_PORT_ENABLE                  (C3_PORT_ENABLE),

         .C_P0_MASK_SIZE                 (C3_P0_MASK_SIZE),

         .C_P0_DATA_PORT_SIZE            (C3_P0_DATA_PORT_SIZE),

         .C_P1_MASK_SIZE                 (C3_P1_MASK_SIZE),

         .C_P1_DATA_PORT_SIZE            (C3_P1_DATA_PORT_SIZE),

         .C_P0_PORT_MODE                 (C3_P0_PORT_MODE),

         .C_P1_PORT_MODE                 (C3_P1_PORT_MODE),

         .C_P2_PORT_MODE                 (C3_P2_PORT_MODE),

         .C_P3_PORT_MODE                 (C3_P3_PORT_MODE),

         .C_P4_PORT_MODE                 (C3_P4_PORT_MODE),

         .C_P5_PORT_MODE                 (C3_P5_PORT_MODE),

         .C_p0_BEGIN_ADDRESS             (C3_p0_BEGIN_ADDRESS),

         .C_p0_DATA_MODE                 (C3_p0_DATA_MODE),

         .C_p0_END_ADDRESS               (C3_p0_END_ADDRESS),

         .C_p0_PRBS_EADDR_MASK_POS       (C3_p0_PRBS_EADDR_MASK_POS),

         .C_p0_PRBS_SADDR_MASK_POS       (C3_p0_PRBS_SADDR_MASK_POS),

         .C_p1_BEGIN_ADDRESS             (C3_p1_BEGIN_ADDRESS),

         .C_p1_DATA_MODE                 (C3_p1_DATA_MODE),

         .C_p1_END_ADDRESS               (C3_p1_END_ADDRESS),

         .C_p1_PRBS_EADDR_MASK_POS       (C3_p1_PRBS_EADDR_MASK_POS),

         .C_p1_PRBS_SADDR_MASK_POS       (C3_p1_PRBS_SADDR_MASK_POS),

         .C_p2_BEGIN_ADDRESS             (C3_p2_BEGIN_ADDRESS),

         .C_p2_DATA_MODE                 (C3_p2_DATA_MODE),

         .C_p2_END_ADDRESS               (C3_p2_END_ADDRESS),

         .C_p2_PRBS_EADDR_MASK_POS       (C3_p2_PRBS_EADDR_MASK_POS),

         .C_p2_PRBS_SADDR_MASK_POS       (C3_p2_PRBS_SADDR_MASK_POS),

         .C_p3_BEGIN_ADDRESS             (C3_p3_BEGIN_ADDRESS),

         .C_p3_DATA_MODE                 (C3_p3_DATA_MODE),

         .C_p3_END_ADDRESS               (C3_p3_END_ADDRESS),

         .C_p3_PRBS_EADDR_MASK_POS       (C3_p3_PRBS_EADDR_MASK_POS),

         .C_p3_PRBS_SADDR_MASK_POS       (C3_p3_PRBS_SADDR_MASK_POS),

         .C_p4_BEGIN_ADDRESS             (C3_p4_BEGIN_ADDRESS),

         .C_p4_DATA_MODE                 (C3_p4_DATA_MODE),

         .C_p4_END_ADDRESS               (C3_p4_END_ADDRESS),

         .C_p4_PRBS_EADDR_MASK_POS       (C3_p4_PRBS_EADDR_MASK_POS),

         .C_p4_PRBS_SADDR_MASK_POS       (C3_p4_PRBS_SADDR_MASK_POS),

         .C_p5_BEGIN_ADDRESS             (C3_p5_BEGIN_ADDRESS),

         .C_p5_DATA_MODE                 (C3_p5_DATA_MODE),

         .C_p5_END_ADDRESS               (C3_p5_END_ADDRESS),

         .C_p5_PRBS_EADDR_MASK_POS       (C3_p5_PRBS_EADDR_MASK_POS),

         .C_p5_PRBS_SADDR_MASK_POS       (C3_p5_PRBS_SADDR_MASK_POS)

         )

      memc3_tb_top_inst

      (

         .error                                  (c3_error),

         .calib_done                             (c3_calib_done),

         .clk0                                   (c3_clk0),

         .rst0                                   (c3_rst0),

         .cmp_error                                  (c3_cmp_error),

         .cmp_data_valid                     (c3_cmp_data_valid),

         .cmp_data                                   (c3_cmp_data),

         .vio_modify_enable              (c3_vio_modify_enable),

         .vio_data_mode_value            (c3_vio_data_mode_value),

         .vio_addr_mode_value            (c3_vio_addr_mode_value),

         .p0_error_status                    (c3_p0_error_status),

         .p1_error_status                    (c3_p1_error_status),

         .p2_error_status                    (c3_p2_error_status),

         .p3_error_status                    (c3_p3_error_status),

         .p4_error_status                    (c3_p4_error_status),

         .p5_error_status                    (c3_p5_error_status),

         // The following port map shows that all the memory controller ports are connected

         // to the test bench top. However, a traffic generator can be connected to the 

         // corresponding port only if the port is enabled, whose information can be obtained

         // from the parameters C_PORT_ENABLE. 

         // User Port-0 command interface will be active only when the port is enabled in 

         // the port configurations Config-1, Config-2, Config-3, Config-4 and Config-5

         .p0_mcb_cmd_en                  (c3_p0_cmd_en),

         .p0_mcb_cmd_instr               (c3_p0_cmd_instr),

         .p0_mcb_cmd_bl                  (c3_p0_cmd_bl),

         .p0_mcb_cmd_addr                (c3_p0_cmd_byte_addr),

         .p0_mcb_cmd_full                (c3_p0_cmd_full),

         // User Port-0 data write interface will be active only when the port is enabled in

         // the port configurations Config-1, Config-2, Config-3, Config-4 and Config-5

         .p0_mcb_wr_en                   (c3_p0_wr_en),

         .p0_mcb_wr_mask                 (c3_p0_wr_mask),

         .p0_mcb_wr_data                 (c3_p0_wr_data),

         .p0_mcb_wr_full                 (c3_p0_wr_full),

         .p0_mcb_wr_fifo_counts          (c3_p0_wr_count),

         // User Port-0 data read interface will be active only when the port is enabled in

         // the port configurations Config-1, Config-2, Config-3, Config-4 and Config-5

         .p0_mcb_rd_en                   (c3_p0_rd_en),

         .p0_mcb_rd_data                 (c3_p0_rd_data),

         .p0_mcb_rd_empty                (c3_p0_rd_empty),

         .p0_mcb_rd_fifo_counts          (c3_p0_rd_count),

         // User Port-1 command interface will be active only when the port is enabled in 

         // the port configurations Config-1, Config-2, Config-3 and Config-4

         .p1_mcb_cmd_en                  (c3_p1_cmd_en),

         .p1_mcb_cmd_instr               (c3_p1_cmd_instr),

         .p1_mcb_cmd_bl                  (c3_p1_cmd_bl),

         .p1_mcb_cmd_addr                (c3_p1_cmd_byte_addr),

         .p1_mcb_cmd_full                (c3_p1_cmd_full),

         // User Port-1 data write interface will be active only when the port is enabled in 

         // the port configurations Config-1, Config-2, Config-3 and Config-4

         .p1_mcb_wr_en                   (c3_p1_wr_en),

         .p1_mcb_wr_mask                 (c3_p1_wr_mask),

         .p1_mcb_wr_data                 (c3_p1_wr_data),

         .p1_mcb_wr_full                 (c3_p1_wr_full),

         .p1_mcb_wr_fifo_counts          (c3_p1_wr_count),

         // User Port-1 data read interface will be active only when the port is enabled in