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//*****************************************************************************
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// (c) Copyright 2008-2009 Xilinx, Inc. All rights reserved.
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//
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// This file contains confidential and proprietary information
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// of Xilinx, Inc. and is protected under U.S. and
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// international copyright and other intellectual property
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// laws.
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//
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// DISCLAIMER
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// This disclaimer is not a license and does not grant any
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// rights to the materials distributed herewith. Except as
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// otherwise provided in a valid license issued to you by
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// Xilinx, and to the maximum extent permitted by applicable
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// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
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// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
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// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
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// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
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// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
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// (2) Xilinx shall not be liable (whether in contract or tort,
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// including negligence, or under any other theory of
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// liability) for any loss or damage of any kind or nature
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// related to, arising under or in connection with these
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// materials, including for any direct, or any indirect,
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// special, incidental, or consequential loss or damage
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// (including loss of data, profits, goodwill, or any type of
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// loss or damage suffered as a result of any action brought
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// by a third party) even if such damage or loss was
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// reasonably foreseeable or Xilinx had been advised of the
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// possibility of the same.
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//
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// CRITICAL APPLICATIONS
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// Xilinx products are not designed or intended to be fail-
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// safe, or for use in any application requiring fail-safe
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// performance, such as life-support or safety devices or
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// systems, Class III medical devices, nuclear facilities,
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// applications related to the deployment of airbags, or any
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// other applications that could lead to death, personal
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// injury, or severe property or environmental damage
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// (individually and collectively, "Critical
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// Applications"). Customer assumes the sole risk and
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// liability of any use of Xilinx products in Critical
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// Applications, subject only to applicable laws and
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// regulations governing limitations on product liability.
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//
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// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
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// PART OF THIS FILE AT ALL TIMES.
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//
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//*****************************************************************************
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// ____ ____
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// / /\/ /
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// /___/ \ / Vendor: Xilinx
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// \ \ \/ Version: %version
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// \ \ Application: MIG
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// / / Filename: data_gen.v
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// /___/ /\ Date Last Modified:
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// \ \ / \ Date Created:
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// \___\/\___\
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//
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//Device: Spartan6
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//Design Name: DDR/DDR2/DDR3/LPDDR
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//Purpose: This module generates different data pattern as described in
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// parameter DATA_PATTERN and is set up for Spartan 6 family.
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//Reference:
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//Revision History:
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//*****************************************************************************
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`timescale 1ps/1ps
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module sp6_data_gen #
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(
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parameter TCQ = 100,
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parameter ADDR_WIDTH = 32,
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parameter BL_WIDTH = 6,
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parameter DWIDTH = 32,
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parameter DATA_PATTERN = "DGEN_ALL", //"DGEN__HAMMER", "DGEN_WALING1","DGEN_WALING0","DGEN_ADDR","DGEN_NEIGHBOR","DGEN_PRBS","DGEN_ALL"
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parameter NUM_DQ_PINS = 8,
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parameter COLUMN_WIDTH = 10
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)
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(
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input clk_i, //
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input rst_i,
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input [31:0] prbs_fseed_i,
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input [3:0] data_mode_i, // "00" = bram;
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input data_rdy_i,
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input cmd_startA,
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input cmd_startB,
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input cmd_startC,
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input cmd_startD,
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input cmd_startE,
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input [DWIDTH-1:0] fixed_data_i,
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input [ADDR_WIDTH-1:0] addr_i, // generated address used to determine data pattern.
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input [6:0] user_burst_cnt, // generated burst length for control the burst data
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input fifo_rdy_i, // connect from mcb_wr_full when used as wr_data_gen
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// connect from mcb_rd_empty when used as rd_data_gen
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// When both data_rdy and data_valid is asserted, the ouput data is valid.
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output [DWIDTH-1:0] data_o // generated data pattern
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);
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//
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wire [31:0] prbs_data;
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reg [31:0] adata;
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reg [DWIDTH-1:0] hdata;
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reg [DWIDTH-1:0] ndata;
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reg [DWIDTH - 1:0] w1data;
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reg [DWIDTH-1:0] data;
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reg burst_count_reached2;
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reg data_valid;
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reg [2:0] walk_cnt;
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reg [ADDR_WIDTH-1:0] user_address;
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integer i,j;
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reg [BL_WIDTH-1:0] user_bl;
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reg [7:0] BLANK;
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reg [7:0] SHIFT_0;
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reg [7:0] SHIFT_1;
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reg [7:0] SHIFT_2;
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reg [7:0] SHIFT_3;
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reg [7:0] SHIFT_4;
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reg [7:0] SHIFT_5;
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reg [7:0] SHIFT_6;
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reg [7:0] SHIFT_7;
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reg [31:0] SHIFTB_0 ;
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reg [31:0] SHIFTB_1;
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reg [31:0] SHIFTB_2;
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reg [31:0] SHIFTB_3;
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reg [31:0] SHIFTB_4;
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reg [31:0] SHIFTB_5;
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reg [31:0] SHIFTB_6;
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reg [31:0] SHIFTB_7;
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reg [3:0] TSTB;
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//*********************************************************************************************
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assign data_o = data;
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generate
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if (DWIDTH==32) begin: data_out32
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always @ (adata,hdata,ndata,w1data,prbs_data,data_mode_i,fixed_data_i)
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begin
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case(data_mode_i)
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// 4'b0000: data = 32'b0; //reserved
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4'b0001: data = fixed_data_i; // fixed
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4'b0010: data = adata; // address as data
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4'b0011: data = hdata; // DGEN_HAMMER
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4'b0100: data = ndata; // DGEN_NEIGHBOUR
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4'b0101: data = w1data; // DGEN_WALKING1
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4'b0110: data = w1data; // DGEN_WALKING0
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4'b0111: data = prbs_data;
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default : data = 'b0;
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endcase
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end
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end
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endgenerate
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generate
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if (DWIDTH==64) begin: data_out64
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always @ (adata,hdata,ndata,w1data,prbs_data,data_mode_i,fixed_data_i)
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begin
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case(data_mode_i)
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4'b0000: data = 'b0; //reserved
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4'b0001: data = fixed_data_i; // fixed
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4'b0010: data = {adata,adata}; // address as data
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4'b0011: data = hdata; // DGEN_HAMMER
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4'b0100: data = ndata; // DGEN_NEIGHBOUR
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4'b0101: data = w1data; // DGEN_WALKING1
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4'b0110: data = w1data; // DGEN_WALKING0
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4'b0111: data = {prbs_data,prbs_data};
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default : data = 'b0;
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endcase
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end
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end
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endgenerate
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generate
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if (DWIDTH==128) begin: data_out128
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always @ (adata,hdata,ndata,w1data,prbs_data,data_mode_i,fixed_data_i)
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begin
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case(data_mode_i)
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4'b0000: data = 'b0; //reserved
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4'b0001: data = fixed_data_i; // fixed
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4'b0010: data = {adata,adata,adata,adata}; // address as data
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4'b0011: data = hdata; // DGEN_HAMMER
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4'b0100: data = ndata; // DGEN_NEIGHBOUR
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4'b0101: data = w1data; // DGEN_WALKING1
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4'b0110: data = w1data; // DGEN_WALKING0
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4'b0111: data = {prbs_data,prbs_data,prbs_data,prbs_data};
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default : data = 'b0;
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endcase
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end
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end
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endgenerate
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// WALKING ONES:
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generate
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if ((DWIDTH == 64) ||(DWIDTH == 128)) begin: SHIFT_VALUE
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always @ (data_mode_i) begin
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if (data_mode_i == 3'b101 || data_mode_i == 3'b100) begin // WALKING ONE
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BLANK = 8'h00;
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SHIFT_0 = 8'h01;
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SHIFT_1 = 8'h02;
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SHIFT_2 = 8'h04;
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SHIFT_3 = 8'h08;
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SHIFT_4 = 8'h10;
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SHIFT_5 = 8'h20;
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SHIFT_6 = 8'h40;
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SHIFT_7 = 8'h80;
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end
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else if (data_mode_i == 3'b100)begin // NEIGHBOR ONE
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BLANK = 8'h00;
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SHIFT_0 = 8'h01;
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SHIFT_1 = 8'h02;
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SHIFT_2 = 8'h04;
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SHIFT_3 = 8'h08;
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SHIFT_4 = 8'h10;
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SHIFT_5 = 8'h20;
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SHIFT_6 = 8'h40;
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SHIFT_7 = 8'h80;
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end
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else if (data_mode_i == 3'b110) begin // WALKING ZERO
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BLANK = 8'hff;
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SHIFT_0 = 8'hfe;
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SHIFT_1 = 8'hfd;
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SHIFT_2 = 8'hfb;
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SHIFT_3 = 8'hf7;
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SHIFT_4 = 8'hef;
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SHIFT_5 = 8'hdf;
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SHIFT_6 = 8'hbf;
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SHIFT_7 = 8'h7f;
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end
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else begin
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BLANK = 8'hff;
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SHIFT_0 = 8'hfe;
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SHIFT_1 = 8'hfd;
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SHIFT_2 = 8'hfb;
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SHIFT_3 = 8'hf7;
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SHIFT_4 = 8'hef;
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SHIFT_5 = 8'hdf;
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SHIFT_6 = 8'hbf;
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SHIFT_7 = 8'h7f;
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end
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end
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end
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endgenerate
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always @ (data_mode_i) begin
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if (data_mode_i == 3'b101 ) begin // WALKING ONE
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SHIFTB_0 = 32'h0002_0001;
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SHIFTB_1 = 32'h0008_0004;
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SHIFTB_2 = 32'h0020_0010;
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SHIFTB_3 = 32'h0080_0040;
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SHIFTB_4 = 32'h0200_0100;
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SHIFTB_5 = 32'h0800_0400;
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SHIFTB_6 = 32'h2000_1000;
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SHIFTB_7 = 32'h8000_4000;
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end
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else if (data_mode_i == 3'b100)begin // NEIGHBOR ONE
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SHIFTB_0 = 32'h0000_0001;
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SHIFTB_1 = 32'h0000_0002;
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SHIFTB_2 = 32'h0000_0004;
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SHIFTB_3 = 32'h0000_0008;
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SHIFTB_4 = 32'h0000_0010;
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SHIFTB_5 = 32'h0000_0020;
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SHIFTB_6 = 32'h0000_0040;
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SHIFTB_7 = 32'h0000_0080;
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end
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else begin // WALKING ZERO
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SHIFTB_0 = 32'hfffd_fffe;
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SHIFTB_1 = 32'hfff7_fffb;
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SHIFTB_2 = 32'hffdf_ffef;
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SHIFTB_3 = 32'hff7f_ffbf;
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SHIFTB_4 = 32'hfdff_feff;
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SHIFTB_5 = 32'hf7ff_fbff;
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SHIFTB_6 = 32'hdfff_efff;
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SHIFTB_7 = 32'h7fff_bfff;
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end
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end
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reg [DWIDTH-1:0] tmpdata ;
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reg ndata_rising;
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reg shift_en;
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generate
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if (DWIDTH == 32 && (DATA_PATTERN == "DGEN_WALKING0" || DATA_PATTERN == "DGEN_WALKING1" ||
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DATA_PATTERN == "DGEN_ALL")) begin : WALKING_ONE_32_PATTERN
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always @ (posedge clk_i)
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begin
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if (rst_i) begin
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w1data <= #TCQ 'b0;
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ndata_rising <= #TCQ 1'b1;
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shift_en <= #TCQ 1'b0;
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end
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else if((fifo_rdy_i && user_burst_cnt != 6'd0) || cmd_startC )
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if (NUM_DQ_PINS == 16)
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begin
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if(cmd_startC)
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begin
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case (addr_i[4:2])
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0: w1data <= #TCQ SHIFTB_0;
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1: w1data <= #TCQ SHIFTB_1;
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2: w1data <= #TCQ SHIFTB_2;
|
| 331 |
|
|
3: w1data <= #TCQ SHIFTB_3;
|
| 332 |
|
|
4: w1data <= #TCQ SHIFTB_4;
|
| 333 |
|
|
5: w1data <= #TCQ SHIFTB_5;
|
| 334 |
|
|
6: w1data <= #TCQ SHIFTB_6;
|
| 335 |
|
|
7: w1data <= #TCQ SHIFTB_7;
|
| 336 |
|
|
|
| 337 |
|
|
default :w1data <= #TCQ SHIFTB_0;
|
| 338 |
|
|
endcase
|
| 339 |
|
|
|
| 340 |
|
|
ndata_rising <= #TCQ 1'b0;
|
| 341 |
|
|
end //(NUM_DQ_PINS == 16) (cmd_startC)
|
| 342 |
|
|
else //shifting
|
| 343 |
|
|
if (data_mode_i == 3'b100)
|
| 344 |
|
|
w1data <= #TCQ {16'h0000,w1data[14:0],w1data[15]};
|
| 345 |
|
|
else
|
| 346 |
|
|
w1data <= #TCQ {w1data[29:16],w1data[31:30],w1data[13:0],w1data[15:14]};
|
| 347 |
|
|
|
| 348 |
|
|
|
| 349 |
|
|
end //(DQ_PINS == 16
|
| 350 |
|
|
else if (NUM_DQ_PINS == 8) begin
|
| 351 |
|
|
if(cmd_startC) // loading data pattern according the incoming address
|
| 352 |
|
|
begin
|
| 353 |
|
|
case (addr_i[2])
|
| 354 |
|
|
0: w1data <= #TCQ SHIFTB_0;
|
| 355 |
|
|
1: w1data <= #TCQ SHIFTB_1;
|
| 356 |
|
|
default :w1data <= #TCQ SHIFTB_0;
|
| 357 |
|
|
endcase
|
| 358 |
|
|
end // (cmd_startC)
|
| 359 |
|
|
else // Shifting
|
| 360 |
|
|
// need neigbour pattern ********************
|
| 361 |
|
|
w1data <= #TCQ {w1data[27:24],w1data[31:28],w1data[19:16],w1data[23:20],
|
| 362 |
|
|
w1data[11:8] ,w1data[15:12],w1data[3:0] ,w1data[7:4]};
|
| 363 |
|
|
|
| 364 |
|
|
end //(NUM_DQ_PINS == 8)
|
| 365 |
|
|
else if (NUM_DQ_PINS == 4) begin // NUM_DQ_PINS == 4
|
| 366 |
|
|
// need neigbour pattern ********************
|
| 367 |
|
|
if (data_mode_i == 3'b100)
|
| 368 |
|
|
w1data <= #TCQ 32'h0804_0201;
|
| 369 |
|
|
else
|
| 370 |
|
|
w1data <= #TCQ 32'h8421_8421;
|
| 371 |
|
|
end // (NUM_DQ_PINS_4
|
| 372 |
|
|
|
| 373 |
|
|
end
|
| 374 |
|
|
end
|
| 375 |
|
|
endgenerate // DWIDTH == 32
|
| 376 |
|
|
|
| 377 |
|
|
generate
|
| 378 |
|
|
if (DWIDTH == 64 && (DATA_PATTERN == "DGEN_WALKING0" || DATA_PATTERN == "DGEN_WALKING1"
|
| 379 |
|
|
|| DATA_PATTERN == "DGEN_ALL")) begin : WALKING_ONE_64_PATTERN
|
| 380 |
|
|
|
| 381 |
|
|
always @ (posedge clk_i)
|
| 382 |
|
|
begin
|
| 383 |
|
|
if (rst_i)
|
| 384 |
|
|
w1data <= #TCQ 'b0;
|
| 385 |
|
|
|
| 386 |
|
|
else if((fifo_rdy_i && user_burst_cnt != 6'd0) || cmd_startC )
|
| 387 |
|
|
|
| 388 |
|
|
|
| 389 |
|
|
|
| 390 |
|
|
if (NUM_DQ_PINS == 16)
|
| 391 |
|
|
begin
|
| 392 |
|
|
if(cmd_startC)
|
| 393 |
|
|
begin
|
| 394 |
|
|
|
| 395 |
|
|
case (addr_i[4:3])
|
| 396 |
|
|
|
| 397 |
|
|
|
| 398 |
|
|
0: begin
|
| 399 |
|
|
// 7:0
|
| 400 |
|
|
w1data[2*DWIDTH/4-1:0*DWIDTH/4] <= #TCQ SHIFTB_0;
|
| 401 |
|
|
w1data[4*DWIDTH/4-1:2*DWIDTH/4] <= #TCQ SHIFTB_1;
|
| 402 |
|
|
|
| 403 |
|
|
end
|
| 404 |
|
|
1: begin
|
| 405 |
|
|
w1data[2*DWIDTH/4-1:0*DWIDTH/4] <= #TCQ SHIFTB_2;
|
| 406 |
|
|
w1data[4*DWIDTH/4-1:2*DWIDTH/4] <= #TCQ SHIFTB_3;
|
| 407 |
|
|
end
|
| 408 |
|
|
|
| 409 |
|
|
2: begin
|
| 410 |
|
|
w1data[2*DWIDTH/4-1:0*DWIDTH/4] <= #TCQ SHIFTB_4;
|
| 411 |
|
|
w1data[4*DWIDTH/4-1:2*DWIDTH/4] <= #TCQ SHIFTB_5;
|
| 412 |
|
|
end
|
| 413 |
|
|
3: begin
|
| 414 |
|
|
w1data[2*DWIDTH/4-1:0*DWIDTH/4] <= #TCQ SHIFTB_6;
|
| 415 |
|
|
w1data[4*DWIDTH/4-1:2*DWIDTH/4] <= #TCQ SHIFTB_7;
|
| 416 |
|
|
|
| 417 |
|
|
end
|
| 418 |
|
|
|
| 419 |
|
|
|
| 420 |
|
|
default :begin
|
| 421 |
|
|
w1data <= #TCQ BLANK; //15:8
|
| 422 |
|
|
end
|
| 423 |
|
|
|
| 424 |
|
|
endcase
|
| 425 |
|
|
|
| 426 |
|
|
|
| 427 |
|
|
end //(NUM_DQ_PINS == 16) (cmd_startC)
|
| 428 |
|
|
else begin //shifting
|
| 429 |
|
|
if (data_mode_i == 3'b100)
|
| 430 |
|
|
begin
|
| 431 |
|
|
w1data[63:48] <= #TCQ {16'h0000};
|
| 432 |
|
|
w1data[47:32] <= #TCQ {w1data[45:32],w1data[47:46]};
|
| 433 |
|
|
w1data[31:16] <= #TCQ {16'h0000};
|
| 434 |
|
|
w1data[15:0] <= #TCQ {w1data[13:0],w1data[15:14]};
|
| 435 |
|
|
|
| 436 |
|
|
end
|
| 437 |
|
|
else
|
| 438 |
|
|
|
| 439 |
|
|
w1data[DWIDTH - 1:0] <= #TCQ {
|
| 440 |
|
|
w1data[4*DWIDTH/4 - 5:4*DWIDTH/4 - 16],
|
| 441 |
|
|
w1data[4*DWIDTH/4 - 1 :4*DWIDTH/4 - 4],
|
| 442 |
|
|
|
| 443 |
|
|
w1data[3*DWIDTH/4 - 5:3*DWIDTH/4 - 16],
|
| 444 |
|
|
w1data[3*DWIDTH/4 - 1 :3*DWIDTH/4 - 4],
|
| 445 |
|
|
|
| 446 |
|
|
w1data[2*DWIDTH/4 - 5:2*DWIDTH/4 - 16],
|
| 447 |
|
|
w1data[2*DWIDTH/4 - 1 :2*DWIDTH/4 - 4],
|
| 448 |
|
|
|
| 449 |
|
|
w1data[1*DWIDTH/4 - 5:1*DWIDTH/4 - 16],
|
| 450 |
|
|
w1data[1*DWIDTH/4 - 1 :1*DWIDTH/4 - 4]
|
| 451 |
|
|
|
| 452 |
|
|
};
|
| 453 |
|
|
|
| 454 |
|
|
|
| 455 |
|
|
end
|
| 456 |
|
|
|
| 457 |
|
|
end //(DQ_PINS == 16
|
| 458 |
|
|
else if (NUM_DQ_PINS == 8) begin
|
| 459 |
|
|
if(cmd_startC) // loading data pattern according the incoming address
|
| 460 |
|
|
|
| 461 |
|
|
if (data_mode_i == 3'b100)
|
| 462 |
|
|
|
| 463 |
|
|
case (addr_i[3])
|
| 464 |
|
|
|
| 465 |
|
|
|
| 466 |
|
|
0: w1data <= #TCQ {
|
| 467 |
|
|
BLANK,SHIFT_3,BLANK,SHIFT_2,
|
| 468 |
|
|
BLANK,SHIFT_1,BLANK,SHIFT_0
|
| 469 |
|
|
};
|
| 470 |
|
|
|
| 471 |
|
|
1: w1data <= #TCQ {
|
| 472 |
|
|
BLANK,SHIFT_7,BLANK,SHIFT_6,
|
| 473 |
|
|
BLANK,SHIFT_5,BLANK,SHIFT_4
|
| 474 |
|
|
};
|
| 475 |
|
|
|
| 476 |
|
|
default :begin
|
| 477 |
|
|
w1data <= #TCQ 'b0; //15:8
|
| 478 |
|
|
end
|
| 479 |
|
|
|
| 480 |
|
|
endcase
|
| 481 |
|
|
|
| 482 |
|
|
else
|
| 483 |
|
|
w1data <= #TCQ {32'h8040_2010,32'h0804_0201}; //**** checked
|
| 484 |
|
|
else // Shifting
|
| 485 |
|
|
if (data_mode_i == 3'b100)
|
| 486 |
|
|
|
| 487 |
|
|
begin
|
| 488 |
|
|
w1data[63:56] <= #TCQ {8'h00};
|
| 489 |
|
|
w1data[55:48] <= #TCQ {w1data[51:48],w1data[55:52]};
|
| 490 |
|
|
|
| 491 |
|
|
w1data[47:40] <= #TCQ {8'h00};
|
| 492 |
|
|
w1data[39:32] <= #TCQ {w1data[35:32],w1data[39:36]};
|
| 493 |
|
|
|
| 494 |
|
|
w1data[31:24] <= #TCQ {8'h00};
|
| 495 |
|
|
w1data[23:16] <= #TCQ {w1data[19:16],w1data[23:20]};
|
| 496 |
|
|
|
| 497 |
|
|
w1data[15:8] <= #TCQ {8'h00};
|
| 498 |
|
|
w1data[7:0] <= #TCQ {w1data[3:0],w1data[7:4]};
|
| 499 |
|
|
|
| 500 |
|
|
end
|
| 501 |
|
|
else
|
| 502 |
|
|
w1data <= #TCQ w1data;
|
| 503 |
|
|
end //(NUM_DQ_PINS == 8)
|
| 504 |
|
|
else if (NUM_DQ_PINS == 4) // NUM_DQ_PINS == 4
|
| 505 |
|
|
if (data_mode_i == 3'b100)
|
| 506 |
|
|
w1data <= #TCQ 64'h0804_0201_0804_0201;
|
| 507 |
|
|
else
|
| 508 |
|
|
w1data <= #TCQ 64'h8421_8421_8421_8421;
|
| 509 |
|
|
|
| 510 |
|
|
end
|
| 511 |
|
|
end
|
| 512 |
|
|
endgenerate
|
| 513 |
|
|
|
| 514 |
|
|
generate
|
| 515 |
|
|
|
| 516 |
|
|
if (DWIDTH == 128 && (DATA_PATTERN == "DGEN_WALKING0" || DATA_PATTERN == "DGEN_WALKING1" || DATA_PATTERN == "DGEN_ALL")) begin : WALKING_ONE_128_PATTERN
|
| 517 |
|
|
|
| 518 |
|
|
always @ (posedge clk_i)
|
| 519 |
|
|
begin
|
| 520 |
|
|
if (rst_i)
|
| 521 |
|
|
w1data <= #TCQ 'b0;
|
| 522 |
|
|
|
| 523 |
|
|
else if((fifo_rdy_i && user_burst_cnt != 6'd0) || cmd_startC )
|
| 524 |
|
|
|
| 525 |
|
|
|
| 526 |
|
|
|
| 527 |
|
|
if (NUM_DQ_PINS == 16)
|
| 528 |
|
|
begin
|
| 529 |
|
|
if(cmd_startC)
|
| 530 |
|
|
begin
|
| 531 |
|
|
case (addr_i[4])
|
| 532 |
|
|
|
| 533 |
|
|
|
| 534 |
|
|
0: begin
|
| 535 |
|
|
|
| 536 |
|
|
w1data[1*DWIDTH/4-1:0*DWIDTH/4] <= #TCQ SHIFTB_0;
|
| 537 |
|
|
w1data[2*DWIDTH/4-1:1*DWIDTH/4] <= #TCQ SHIFTB_1; // 32
|
| 538 |
|
|
w1data[3*DWIDTH/4-1:2*DWIDTH/4] <= #TCQ SHIFTB_2;
|
| 539 |
|
|
w1data[4*DWIDTH/4-1:3*DWIDTH/4] <= #TCQ SHIFTB_3;
|
| 540 |
|
|
|
| 541 |
|
|
|
| 542 |
|
|
end
|
| 543 |
|
|
1: begin
|
| 544 |
|
|
|
| 545 |
|
|
w1data[1*DWIDTH/4-1:0*DWIDTH/4] <= #TCQ SHIFTB_4;
|
| 546 |
|
|
w1data[2*DWIDTH/4-1:1*DWIDTH/4] <= #TCQ SHIFTB_5; // 32
|
| 547 |
|
|
w1data[3*DWIDTH/4-1:2*DWIDTH/4] <= #TCQ SHIFTB_6;
|
| 548 |
|
|
w1data[4*DWIDTH/4-1:3*DWIDTH/4] <= #TCQ SHIFTB_7;
|
| 549 |
|
|
|
| 550 |
|
|
end
|
| 551 |
|
|
|
| 552 |
|
|
default :begin
|
| 553 |
|
|
w1data <= #TCQ BLANK; //15:8
|
| 554 |
|
|
|
| 555 |
|
|
end
|
| 556 |
|
|
|
| 557 |
|
|
endcase
|
| 558 |
|
|
|
| 559 |
|
|
end //(NUM_DQ_PINS == 16) (cmd_startC)
|
| 560 |
|
|
else begin //shifting
|
| 561 |
|
|
if (data_mode_i == 3'b100)
|
| 562 |
|
|
begin
|
| 563 |
|
|
w1data[127:112] <= #TCQ {16'h0000};
|
| 564 |
|
|
w1data[111:96] <= #TCQ {w1data[107:96],w1data[111:108]};
|
| 565 |
|
|
w1data[95:80] <= #TCQ {16'h0000};
|
| 566 |
|
|
w1data[79:64] <= #TCQ {w1data[75:64],w1data[79:76]};
|
| 567 |
|
|
|
| 568 |
|
|
|
| 569 |
|
|
w1data[63:48] <= #TCQ {16'h0000};
|
| 570 |
|
|
w1data[47:32] <= #TCQ {w1data[43:32],w1data[47:44]};
|
| 571 |
|
|
w1data[31:16] <= #TCQ {16'h0000};
|
| 572 |
|
|
w1data[15:0] <= #TCQ {w1data[11:0],w1data[15:12]};
|
| 573 |
|
|
|
| 574 |
|
|
end
|
| 575 |
|
|
else begin
|
| 576 |
|
|
w1data[DWIDTH - 1:0] <= #TCQ {
|
| 577 |
|
|
w1data[4*DWIDTH/4 - 9:4*DWIDTH/4 - 16],
|
| 578 |
|
|
w1data[4*DWIDTH/4 - 1 :4*DWIDTH/4 - 8],
|
| 579 |
|
|
w1data[4*DWIDTH/4 - 25:4*DWIDTH/4 -32],
|
| 580 |
|
|
w1data[4*DWIDTH/4 - 17:4*DWIDTH/4 -24],
|
| 581 |
|
|
|
| 582 |
|
|
w1data[3*DWIDTH/4 - 9:3*DWIDTH/4 - 16],
|
| 583 |
|
|
w1data[3*DWIDTH/4 - 1 :3*DWIDTH/4 - 8],
|
| 584 |
|
|
w1data[3*DWIDTH/4 - 25:3*DWIDTH/4 - 32],
|
| 585 |
|
|
w1data[3*DWIDTH/4 - 17:3*DWIDTH/4 - 24],
|
| 586 |
|
|
|
| 587 |
|
|
w1data[2*DWIDTH/4 - 9:2*DWIDTH/4 - 16],
|
| 588 |
|
|
w1data[2*DWIDTH/4 - 1 :2*DWIDTH/4 - 8],
|
| 589 |
|
|
w1data[2*DWIDTH/4 - 25:2*DWIDTH/4 - 32],
|
| 590 |
|
|
w1data[2*DWIDTH/4 - 17:2*DWIDTH/4 - 24],
|
| 591 |
|
|
|
| 592 |
|
|
|
| 593 |
|
|
w1data[1*DWIDTH/4 - 9:1*DWIDTH/4 - 16],
|
| 594 |
|
|
w1data[1*DWIDTH/4 - 1 :1*DWIDTH/4 - 8],
|
| 595 |
|
|
w1data[1*DWIDTH/4 - 25:1*DWIDTH/4 - 32],
|
| 596 |
|
|
w1data[1*DWIDTH/4 - 17 :1*DWIDTH/4 - 24]
|
| 597 |
|
|
};
|
| 598 |
|
|
end
|
| 599 |
|
|
|
| 600 |
|
|
end
|
| 601 |
|
|
|
| 602 |
|
|
end //(DQ_PINS == 16
|
| 603 |
|
|
else if (NUM_DQ_PINS == 8) begin
|
| 604 |
|
|
if(cmd_startC) // loading data pattern according the incoming address
|
| 605 |
|
|
begin
|
| 606 |
|
|
if (data_mode_i == 3'b100)
|
| 607 |
|
|
w1data <= #TCQ {
|
| 608 |
|
|
BLANK,SHIFT_7,BLANK,SHIFT_6,
|
| 609 |
|
|
BLANK,SHIFT_5,BLANK,SHIFT_4,
|
| 610 |
|
|
BLANK,SHIFT_3,BLANK,SHIFT_2,
|
| 611 |
|
|
BLANK,SHIFT_1,BLANK,SHIFT_0
|
| 612 |
|
|
};
|
| 613 |
|
|
else
|
| 614 |
|
|
// w1data <= #TCQ {32'h8040_2010,32'h0804_0201,32'h8040_2010,32'h0804_0201};
|
| 615 |
|
|
w1data <= #TCQ {
|
| 616 |
|
|
SHIFT_7,SHIFT_6,SHIFT_5,SHIFT_4,
|
| 617 |
|
|
SHIFT_3,SHIFT_2,SHIFT_1,SHIFT_0,
|
| 618 |
|
|
SHIFT_7,SHIFT_6,SHIFT_5,SHIFT_4,
|
| 619 |
|
|
SHIFT_3,SHIFT_2,SHIFT_1,SHIFT_0
|
| 620 |
|
|
};
|
| 621 |
|
|
|
| 622 |
|
|
|
| 623 |
|
|
end // (cmd_startC)
|
| 624 |
|
|
else // Shifting
|
| 625 |
|
|
|
| 626 |
|
|
begin
|
| 627 |
|
|
|
| 628 |
|
|
w1data <= #TCQ w1data;//{w1data[96:64], w1data[127:97],w1data[31:0], w1data[63:32]};
|
| 629 |
|
|
end // else
|
| 630 |
|
|
end //(NUM_DQ_PINS == 8)
|
| 631 |
|
|
else
|
| 632 |
|
|
if (data_mode_i == 3'b100)
|
| 633 |
|
|
w1data <= #TCQ 128'h0804_0201_0804_0201_0804_0201_0804_0201;
|
| 634 |
|
|
else
|
| 635 |
|
|
w1data <= #TCQ 128'h8421_8421_8421_8421_8421_8421_8421_8421;
|
| 636 |
|
|
|
| 637 |
|
|
end
|
| 638 |
|
|
end
|
| 639 |
|
|
endgenerate
|
| 640 |
|
|
|
| 641 |
|
|
// HAMMER_PATTERN: Alternating 1s and 0s on DQ pins
|
| 642 |
|
|
// => the rsing data pattern will be 32'b11111111_11111111_11111111_11111111
|
| 643 |
|
|
// => the falling data pattern will be 32'b00000000_00000000_00000000_00000000
|
| 644 |
|
|
generate
|
| 645 |
|
|
if ( DWIDTH == 32 &&( DATA_PATTERN == "DGEN_HAMMER" || DATA_PATTERN == "DGEN_ALL")) begin : HAMMER_PATTERN_32
|
| 646 |
|
|
always @ (posedge clk_i)
|
| 647 |
|
|
begin
|
| 648 |
|
|
if (rst_i)
|
| 649 |
|
|
hdata <= #TCQ 'd0;
|
| 650 |
|
|
else if((fifo_rdy_i && user_burst_cnt != 6'd0) || cmd_startC ) begin
|
| 651 |
|
|
if (NUM_DQ_PINS == 16)
|
| 652 |
|
|
hdata <= #TCQ 32'h0000_FFFF;
|
| 653 |
|
|
else if (NUM_DQ_PINS == 8)
|
| 654 |
|
|
hdata <= #TCQ 32'h00FF_00FF;
|
| 655 |
|
|
else if (NUM_DQ_PINS == 4) // NUM_DQ_PINS == 4
|
| 656 |
|
|
hdata <= #TCQ 32'h0F0F_0F0F;
|
| 657 |
|
|
end
|
| 658 |
|
|
end
|
| 659 |
|
|
end
|
| 660 |
|
|
endgenerate
|
| 661 |
|
|
|
| 662 |
|
|
|
| 663 |
|
|
generate
|
| 664 |
|
|
if ( DWIDTH == 64 && (DATA_PATTERN == "DGEN_HAMMER" || DATA_PATTERN == "DGEN_ALL")) begin : HAMMER_PATTERN_64
|
| 665 |
|
|
always @ (posedge clk_i)
|
| 666 |
|
|
begin
|
| 667 |
|
|
if (rst_i)
|
| 668 |
|
|
hdata <= #TCQ 'd0;
|
| 669 |
|
|
else if((fifo_rdy_i && user_burst_cnt != 6'd0) || cmd_startC )
|
| 670 |
|
|
if (NUM_DQ_PINS == 16)
|
| 671 |
|
|
hdata <= #TCQ 64'h0000FFFF_0000FFFF;
|
| 672 |
|
|
else if (NUM_DQ_PINS == 8)
|
| 673 |
|
|
hdata <= #TCQ 64'h00FF00FF_00FF00FF;
|
| 674 |
|
|
else if (NUM_DQ_PINS == 4) // NUM_DQ_PINS == 4
|
| 675 |
|
|
hdata <= #TCQ 64'h0F0F_0F0F_0F0F_0F0F;
|
| 676 |
|
|
|
| 677 |
|
|
end
|
| 678 |
|
|
end
|
| 679 |
|
|
endgenerate
|
| 680 |
|
|
|
| 681 |
|
|
|
| 682 |
|
|
generate
|
| 683 |
|
|
if ( DWIDTH == 128 && (DATA_PATTERN == "DGEN_HAMMER" || DATA_PATTERN == "DGEN_ALL")) begin : HAMMER_PATTERN_128
|
| 684 |
|
|
always @ (posedge clk_i)
|
| 685 |
|
|
begin
|
| 686 |
|
|
if (rst_i)
|
| 687 |
|
|
hdata <= #TCQ 'd0;
|
| 688 |
|
|
else if((fifo_rdy_i && user_burst_cnt != 6'd0) || cmd_startC )
|
| 689 |
|
|
if (NUM_DQ_PINS == 16)
|
| 690 |
|
|
hdata <= #TCQ 128'h0000FFFF_0000FFFF_0000FFFF_0000FFFF;
|
| 691 |
|
|
else if (NUM_DQ_PINS == 8)
|
| 692 |
|
|
hdata <= #TCQ 128'h00FF00FF_00FF00FF_00FF00FF_00FF00FF;
|
| 693 |
|
|
else if (NUM_DQ_PINS == 4) // NUM_DQ_PINS == 4
|
| 694 |
|
|
hdata <= #TCQ 128'h0F0F_0F0F_0F0F_0F0F_0F0F_0F0F_0F0F_0F0F;
|
| 695 |
|
|
|
| 696 |
|
|
end
|
| 697 |
|
|
end
|
| 698 |
|
|
endgenerate
|
| 699 |
|
|
|
| 700 |
|
|
|
| 701 |
|
|
always @ (w1data,hdata)
|
| 702 |
|
|
begin
|
| 703 |
|
|
for (i=0; i <= DWIDTH - 1; i= i+1)
|
| 704 |
|
|
ndata[i] = hdata[i] ^ w1data[i];
|
| 705 |
|
|
|
| 706 |
|
|
end
|
| 707 |
|
|
|
| 708 |
|
|
|
| 709 |
|
|
|
| 710 |
|
|
|
| 711 |
|
|
// HAMMER_PATTERN_MINUS: generate walking HAMMER data pattern except 1 bit for the whole burst. The incoming addr_i[5:2] determine
|
| 712 |
|
|
// the position of the pin driving oppsite polarity
|
| 713 |
|
|
// addr_i[6:2] = 5'h0f ; 32 bit data port
|
| 714 |
|
|
// => the rsing data pattern will be 32'b11111111_11111111_01111111_11111111
|
| 715 |
|
|
// => the falling data pattern will be 32'b00000000_00000000_00000000_00000000
|
| 716 |
|
|
|
| 717 |
|
|
// ADDRESS_PATTERN: use the address as the 1st data pattern for the whole burst. For example
|
| 718 |
|
|
// Dataport 32 bit width with starting addr_i = 30'h12345678, user burst length 4
|
| 719 |
|
|
// => the 1st data pattern : 32'h12345678
|
| 720 |
|
|
// => the 2nd data pattern : 32'h12345679
|
| 721 |
|
|
// => the 3rd data pattern : 32'h1234567a
|
| 722 |
|
|
// => the 4th data pattern : 32'h1234567b
|
| 723 |
|
|
generate
|
| 724 |
|
|
|
| 725 |
|
|
//data_rdy_i
|
| 726 |
|
|
|
| 727 |
|
|
if (DATA_PATTERN == "DGEN_ADDR" || DATA_PATTERN == "DGEN_ALL") begin : ADDRESS_PATTERN
|
| 728 |
|
|
//data_o logic
|
| 729 |
|
|
always @ (posedge clk_i)
|
| 730 |
|
|
begin
|
| 731 |
|
|
if (cmd_startD)
|
| 732 |
|
|
adata <= #TCQ addr_i;
|
| 733 |
|
|
else if(fifo_rdy_i && data_rdy_i && user_burst_cnt > 6'd1)
|
| 734 |
|
|
if (DWIDTH == 128)
|
| 735 |
|
|
adata <= #TCQ adata + 16;
|
| 736 |
|
|
else if (DWIDTH == 64)
|
| 737 |
|
|
adata <= #TCQ adata + 8;
|
| 738 |
|
|
else // DWIDTH == 32
|
| 739 |
|
|
adata <= #TCQ adata + 4;
|
| 740 |
|
|
end
|
| 741 |
|
|
end
|
| 742 |
|
|
endgenerate
|
| 743 |
|
|
|
| 744 |
|
|
|
| 745 |
|
|
// PRBS_PATTERN: use the address as the PRBS seed data pattern for the whole burst. For example
|
| 746 |
|
|
// Dataport 32 bit width with starting addr_i = 30'h12345678, user burst length 4
|
| 747 |
|
|
//
|
| 748 |
|
|
|
| 749 |
|
|
generate
|
| 750 |
|
|
if (DATA_PATTERN == "DGEN_PRBS" || DATA_PATTERN == "DGEN_ALL") begin : PRBS_PATTERN
|
| 751 |
|
|
|
| 752 |
|
|
// PRBS DATA GENERATION
|
| 753 |
|
|
// xor all the tap positions before feedback to 1st stage.
|
| 754 |
|
|
|
| 755 |
|
|
|
| 756 |
|
|
|
| 757 |
|
|
assign data_clk_en = fifo_rdy_i && data_rdy_i && user_burst_cnt > 6'd1;
|
| 758 |
|
|
|
| 759 |
|
|
|
| 760 |
|
|
data_prbs_gen #
|
| 761 |
|
|
(
|
| 762 |
|
|
.TCQ (TCQ),
|
| 763 |
|
|
.PRBS_WIDTH (32),
|
| 764 |
|
|
.SEED_WIDTH (32)
|
| 765 |
|
|
)
|
| 766 |
|
|
data_prbs_gen
|
| 767 |
|
|
(
|
| 768 |
|
|
.clk_i (clk_i),
|
| 769 |
|
|
.clk_en (data_clk_en),
|
| 770 |
|
|
.rst_i (rst_i),
|
| 771 |
|
|
.prbs_fseed_i (prbs_fseed_i),
|
| 772 |
|
|
.prbs_seed_init (cmd_startE),
|
| 773 |
|
|
.prbs_seed_i (addr_i[31:0]),
|
| 774 |
|
|
.prbs_o (prbs_data)
|
| 775 |
|
|
|
| 776 |
|
|
);
|
| 777 |
|
|
end
|
| 778 |
|
|
endgenerate
|
| 779 |
|
|
|
| 780 |
|
|
|
| 781 |
|
|
endmodule
|
