URL https://opencores.org/ocsvn/usb_fpga_2_14/usb_fpga_2_14/trunk

Subversion Repositories usb_fpga_2_14

[/] [usb_fpga_2_14/] [trunk/] [examples/] [ucecho/] [fpga-2.04b/] [ucecho.ucf] - Blame information for rev 2

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# fxclk_in
NET "fxclk_in" TNM_NET = "fxclk_in";
TIMESPEC "ts_fxclk_in" = PERIOD "fxclk_in" 48 MHz HIGH 50 %;
NET "fxclk_in"  LOC = "J16" | IOSTANDARD = LVCMOS33 ;
 
# reset_in
NET "reset_in"  LOC = "R3" | IOSTANDARD = LVCMOS33 ;            # PA7/FLAGD/SLCS#
 
# LSI signals
NET "lsi_miso"  LOC = "P5" | IOSTANDARD = LVCMOS33 ;            # PC4/GPIFADR4
NET "lsi_mosi"  LOC = "L8" | IOSTANDARD = LVCMOS33 ;            # PC5/GPIFADR5
NET "lsi_clk"   LOC = "L7" | IOSTANDARD = LVCMOS33 ;            # PC6/GPIFADR6
NET "lsi_stop"  LOC = "R5" | IOSTANDARD = LVCMOS33 ;            # PC7/GPIFADR7

Line No.	Rev	Author	Line
1	2	ZTEX	`# fxclk_in`
2			`NET "fxclk_in" TNM_NET = "fxclk_in";`
3			`TIMESPEC "ts_fxclk_in" = PERIOD "fxclk_in" 48 MHz HIGH 50 %;`
4			`NET "fxclk_in" LOC = "J16" \| IOSTANDARD = LVCMOS33 ;`
5
6			`# reset_in`
7			`NET "reset_in" LOC = "R3" \| IOSTANDARD = LVCMOS33 ; # PA7/FLAGD/SLCS#`
8
9			`# LSI signals`
10			`NET "lsi_miso" LOC = "P5" \| IOSTANDARD = LVCMOS33 ; # PC4/GPIFADR4`
11			`NET "lsi_mosi" LOC = "L8" \| IOSTANDARD = LVCMOS33 ; # PC5/GPIFADR5`
12			`NET "lsi_clk" LOC = "L7" \| IOSTANDARD = LVCMOS33 ; # PC6/GPIFADR6`
13			`NET "lsi_stop" LOC = "R5" \| IOSTANDARD = LVCMOS33 ; # PC7/GPIFADR7`

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Subversion Repositories usb_fpga_2_14

[/] [usb_fpga_2_14/] [trunk/] [examples/] [ucecho/] [fpga-2.04b/] [ucecho.ucf] - Blame information for rev 2