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[/] [usb_fpga_2_14/] [trunk/] [fx2/] [ztex-flash1.h] - Blame information for rev 2

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1 2 ZTEX 
/*%
2 
   ZTEX Firmware Kit for EZ-USB FX2 Microcontrollers
3 
   Copyright (C) 2009-2017 ZTEX GmbH.
4 
   http://www.ztex.de
5 
 
6 
   This Source Code Form is subject to the terms of the Mozilla Public
7 
   License, v. 2.0. If a copy of the MPL was not distributed with this file,
8 
   You can obtain one at http://mozilla.org/MPL/2.0/.
9 
 
10 
   Alternatively, the contents of this file may be used under the terms
11 
   of the GNU General Public License Version 3, as described below:
12 
 
13 
   This program is free software; you can redistribute it and/or modify
14 
   it under the terms of the GNU General Public License version 3 as
15 
   published by the Free Software Foundation.
16 
 
17 
   This program is distributed in the hope that it will be useful, but
18 
   WITHOUT ANY WARRANTY; without even the implied warranty of
19 
   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
20 
   General Public License for more details.
21 
 
22 
   You should have received a copy of the GNU General Public License
23 
   along with this program; if not, see http://www.gnu.org/licenses/.
24 
%*/
25 
 
26 
/*
27 
    Support for SD cards in SPI mode.
28 
    This module is not MMC compatible anymore since multi block read/write commands are used.
29 
*/
30 
 
31 
#ifeq[MMC_PORT][E]
32 
#define[MMC_bmMODE]
33 
#elifeq[MMC_PORT][A]
34 
#elifeq[MMC_PORT][B]
35 
#elifeq[MMC_PORT][C]
36 
#elifneq[MMC_PORT][D]
37 
#error[Macro `MMC_PORT' is not defined correctly. Valid values are: `A', `B', `C', `D' and `E'.]
38 
#endif
39 
 
40 
#ifndef[ZTEX_FLASH1_H]
41 
#define[ZTEX_FLASH1_H]
42 
 
43 
#ifeq[FLASH2_ENABLED][1]
44 
#define[@CAPABILITY_FLASH2;]
45 
#define[VCR_OFFS][4]
46 
#else
47 
#define[VCR_OFFS][0]
48 
#define[@CAPABILITY_FLASH;]
49 
#endif
50 
 
51 
#ifndef[MMC_PORT]
52 
#error[MMC_PORT not defined]
53 
#endif
54 
 
55 
#ifndef[MMC_BIT_CS]
56 
#error[MMC_BIT_CS not defined]
57 
#endif
58 
 
59 
#ifndef[MMC_BIT_DI]
60 
#error[MMC_BIT_DI not defined]
61 
#endif
62 
 
63 
#ifndef[MMC_BIT_DO]
64 
#error[MMC_BIT_DO not defined]
65 
#endif
66 
 
67 
#ifndef[MMC_BIT_CLK]
68 
#error[MMC_BIT_CLK not defined]
69 
#endif
70 
 
71 
#ifndef[MMC__PORT_DO]
72 
#define[MMC__PORT_DO][MMC_PORT]
73 
#endif
74 
 
75 
#ifdef[MMC_bmMODE]
76 
#ifneq[MMC__PORT_DO][MMC_PORT]
77 
#error[MMC__PORT_DO and MMC_PORT must be equal]
78 
#endif
79 
#endif
80 
 
81 
#define[MMC_bmCS][bmBITMMC_BIT_CS]
82 
#define[MMC_bmDI][bmBITMMC_BIT_DI]
83 
#define[MMC_bmDO][bmBITMMC_BIT_DO]
84 
#define[MMC_bmCLK][bmBITMMC_BIT_CLK]
85 
 
86 
#define[MMC_IO][IOMMC_PORT]
87 
#define[MMC__IO_DO][IOMMC__PORT_DO]
88 
 
89 
#ifndef[MMC_bmMODE]
90 
#define[MMC_CS][IOMMC_PORTMMC_BIT_CS]
91 
#define[MMC_CLK][IOMMC_PORTMMC_BIT_CLK]
92 
#define[MMC_DI][IOMMC_PORTMMC_BIT_DI]
93 
#define[MMC_DO][IOMMC__PORT_DOMMC_BIT_DO]
94 
#endif
95 
 
96 
// may be redefined if the first sectors are reserved (e.g. for a FPGA bitstream)
97 
#define[FLASH_FIRST_FREE_SECTOR][0]
98 
 
99 
#ifndef[FLASHX]
100 
#define[FLASHX][flash]
101 
#endif
102 
 
103 
__xdata BYTE FLASHX_enabled;            // 0    1: enabled, 0:disabled
104 
__xdata WORD FLASHX_sector_size;        // 1    sector size
105 
__xdata DWORD FLASHX_sectors;           // 3    number of sectors
106 
__xdata BYTE FLASHX_ec;                 // 7    error code
107 
 
108 
__xdata BYTE mmc_last_cmd;      // 0
109 
__xdata BYTE mmc_response;      // 1
110 
__xdata BYTE mmc_version;       // 2
111 
__xdata BYTE mmc_buffer[16];    // 3
112 
 
113 
__xdata BYTE mmc_ep0_wait;
114 
 
115 
#define[FLASH_EC_CMD_ERROR][1]
116 
#define[FLASH_EC_TIMEOUT][2]
117 
#define[FLASH_EC_BUSY][3]
118 
#define[FLASH_EC_PENDING][4]
119 
#define[FLASH_EC_READ_ERROR][5]
120 
#define[FLASH_EC_WRITE_ERROR][6]
121 
#define[FLASH_EC_NOTSUPPORTED][7]
122 
 
123 
/* *********************************************************************
124 
   ***** mmc_clocks ****************************************************
125 
   ********************************************************************* */
126 
// perform c (256 if c=0) clocks
127 
void mmc_clocks (BYTE c) {
128 
        c;                                      // this avoids stupid warnings
129 
__asm
130 
        mov     r2,dpl
131 
#ifdef[MMC_bmMODE]
132 
        mov     a,_MMC_IO
133 
        anl     a, #(~MMC_bmCLK)
134 
        mov     r3, a
135 
        orl     a, #(MMC_bmCLK)
136 
        mov     r4, a
137 
010014$:
138 
        mov     _MMC_IO,r4
139 
        nop
140 
        mov     _MMC_IO,r3
141 
#else
142 
010014$:
143 
        setb    _MMC_CLK
144 
        nop
145 
        clr     _MMC_CLK
146 
#endif
147 
        djnz    r2,010014$
148 
__endasm;
149 
}
150 
 
151 
 
152 
/* *********************************************************************
153 
   ***** FLASHX_read_byte **********************************************
154 
   ********************************************************************* */
155 
// read a single byte from the flash
156 
BYTE FLASHX_read_byte() { // uses r2,r3,r4
157 
__asm
158 
#ifdef[MMC_bmMODE]
159 
        // 8 - 1 + 8*13 + 1 + 6 = 118 clocks
160 
        mov     a,_MMC_IO
161 
        anl     a, #(~MMC_bmCLK)
162 
        mov     r2, a
163 
        orl     a, #(MMC_bmCLK)
164 
        mov     r3, a
165 
 
166 
        mov     a,_MMC_IO       // 7
167 
        anl     a,#(MMC_bmDO)
168 
        mov     _MMC_IO, r3
169 
        subb    a,#1
170 
        rlc     a
171 
        mov     r4,a
172 
        mov     _MMC_IO, r2
173 
 
174 
        mov     a,_MMC_IO       // 6
175 
        anl     a,#(MMC_bmDO)
176 
        mov     _MMC_IO, r3
177 
        subb    a,#1
178 
        mov     a,r4
179 
        rlc     a
180 
        mov     r4,a
181 
        mov     _MMC_IO, r2
182 
 
183 
        mov     a,_MMC_IO       // 5
184 
        anl     a,#(MMC_bmDO)
185 
        mov     _MMC_IO, r3
186 
        subb    a,#1
187 
        mov     a,r4
188 
        rlc     a
189 
        mov     r4,a
190 
        mov     _MMC_IO, r2
191 
 
192 
        mov     a,_MMC_IO       // 4
193 
        anl     a,#(MMC_bmDO)
194 
        mov     _MMC_IO, r3
195 
        subb    a,#1
196 
        mov     a,r4
197 
        rlc     a
198 
        mov     r4,a
199 
        mov     _MMC_IO, r2
200 
 
201 
        mov     a,_MMC_IO       // 3
202 
        anl     a,#(MMC_bmDO)
203 
        mov     _MMC_IO, r3
204 
        subb    a,#1
205 
        mov     a,r4
206 
        rlc     a
207 
        mov     r4,a
208 
        mov     _MMC_IO, r2
209 
 
210 
        mov     a,_MMC_IO       // 2
211 
        anl     a,#(MMC_bmDO)
212 
        mov     _MMC_IO, r3
213 
        subb    a,#1
214 
        mov     a,r4
215 
        rlc     a
216 
        mov     r4,a
217 
        mov     _MMC_IO, r2
218 
 
219 
        mov     a,_MMC_IO       // 1
220 
        anl     a,#(MMC_bmDO)
221 
        mov     _MMC_IO, r3
222 
        subb    a,#1
223 
        mov     a,r4
224 
        rlc     a
225 
        mov     r4,a
226 
        mov     _MMC_IO, r2
227 
 
228 
        mov     a,_MMC_IO       // 0
229 
        anl     a,#(MMC_bmDO)
230 
        mov     _MMC_IO, r3
231 
        subb    a,#1
232 
        mov     a,r4
233 
        rlc     a
234 
        xrl     a,#255
235 
        mov     _MMC_IO, r2
236 
 
237 
#else
238 
        // 8*7 + 6 = 62 clocks
239 
        mov     c,_MMC_DO       // 7
240 
        setb    _MMC_CLK
241 
        rlc     a
242 
        clr     _MMC_CLK
243 
 
244 
        mov     c,_MMC_DO       // 6
245 
        setb    _MMC_CLK
246 
        rlc     a
247 
        clr     _MMC_CLK
248 
 
249 
        mov     c,_MMC_DO       // 5
250 
        setb    _MMC_CLK
251 
        rlc     a
252 
        clr     _MMC_CLK
253 
 
254 
        mov     c,_MMC_DO       // 4
255 
        setb    _MMC_CLK
256 
        rlc     a
257 
        clr     _MMC_CLK
258 
 
259 
        mov     c,_MMC_DO       // 3
260 
        setb    _MMC_CLK
261 
        rlc     a
262 
        clr     _MMC_CLK
263 
 
264 
        mov     c,_MMC_DO       // 2
265 
        setb    _MMC_CLK
266 
        rlc     a
267 
        clr     _MMC_CLK
268 
 
269 
        mov     c,_MMC_DO       // 1
270 
        setb    _MMC_CLK
271 
        rlc     a
272 
        clr     _MMC_CLK
273 
 
274 
        mov     c,_MMC_DO       // 0
275 
        setb    _MMC_CLK
276 
        rlc     a
277 
        clr     _MMC_CLK
278 
#endif
279 
        mov     dpl,a
280 
        ret
281 
__endasm;
282 
        return 0;                // never ever called (just to avoid warnings)
283 
}
284 
 
285 
/* *********************************************************************
286 
   ***** FLASHX_read ***************************************************
287 
   ********************************************************************* */
288 
// read len (256 if len=0) bytes from the flash to the buffer
289 
void FLASHX_read(__xdata BYTE *buf, BYTE len) {
290 
        *buf;                                   // this avoids stupid warnings
291 
        len;                                    // this too
292 
__asm                                           // *buf is in dptr, len is in _FLASHX_read_PARM_2
293 
        mov     r2,_FLASHX_read_PARM_2
294 
#ifdef[MMC_bmMODE]
295 
        mov     a,_MMC_IO
296 
        anl     a, #(~MMC_bmCLK)
297 
        mov     r5, a
298 
        orl     a, #(MMC_bmCLK)
299 
        mov     r3, a
300 
 
301 
010012$:
302 
        // 8 + len*(-1 + 8*13 - 1 + 2 + 9) + 4 = 12 + len*113 clocks
303 
        mov     a,_MMC_IO       // 7
304 
        anl     a,#(MMC_bmDO)
305 
        mov     _MMC_IO, r3
306 
        subb    a,#1
307 
        rlc     a
308 
        mov     r4,a
309 
        mov     _MMC_IO, r5
310 
 
311 
        mov     a,_MMC_IO       // 6
312 
        anl     a,#(MMC_bmDO)
313 
        mov     _MMC_IO, r3
314 
        subb    a,#1
315 
        mov     a,r4
316 
        rlc     a
317 
        mov     r4,a
318 
        mov     _MMC_IO, r5
319 
 
320 
        mov     a,_MMC_IO       // 5
321 
        anl     a,#(MMC_bmDO)
322 
        mov     _MMC_IO, r3
323 
        subb    a,#1
324 
        mov     a,r4
325 
        rlc     a
326 
        mov     r4,a
327 
        mov     _MMC_IO, r5
328 
 
329 
        mov     a,_MMC_IO       // 4
330 
        anl     a,#(MMC_bmDO)
331 
        mov     _MMC_IO, r3
332 
        subb    a,#1
333 
        mov     a,r4
334 
        rlc     a
335 
        mov     r4,a
336 
        mov     _MMC_IO, r5
337 
 
338 
        mov     a,_MMC_IO       // 3
339 
        anl     a,#(MMC_bmDO)
340 
        mov     _MMC_IO, r3
341 
        subb    a,#1
342 
        mov     a,r4
343 
        rlc     a
344 
        mov     r4,a
345 
        mov     _MMC_IO, r5
346 
 
347 
        mov     a,_MMC_IO       // 2
348 
        anl     a,#(MMC_bmDO)
349 
        mov     _MMC_IO, r3
350 
        subb    a,#1
351 
        mov     a,r4
352 
        rlc     a
353 
        mov     r4,a
354 
        mov     _MMC_IO, r5
355 
 
356 
        mov     a,_MMC_IO       // 1
357 
        anl     a,#(MMC_bmDO)
358 
        mov     _MMC_IO, r3
359 
        subb    a,#1
360 
        mov     a,r4
361 
        rlc     a
362 
        mov     r4,a
363 
        mov     _MMC_IO, r5
364 
 
365 
        mov     a,_MMC_IO       // 0
366 
        anl     a,#(MMC_bmDO)
367 
        mov     _MMC_IO, r3
368 
        subb    a,#1
369 
        mov     a,r4
370 
        rlc     a
371 
        xrl     a,#255
372 
        mov     _MMC_IO, r5
373 
#else
374 
010012$:
375 
        // 2 + len*(8*7 + 9) + 4 = 6 + len*65 clocks
376 
        mov     c,_MMC_DO       // 7
377 
        setb    _MMC_CLK
378 
        rlc     a
379 
        clr     _MMC_CLK
380 
 
381 
        mov     c,_MMC_DO       // 6
382 
        setb    _MMC_CLK
383 
        rlc     a
384 
        clr     _MMC_CLK
385 
 
386 
        mov     c,_MMC_DO       // 5
387 
        setb    _MMC_CLK
388 
        rlc     a
389 
        clr     _MMC_CLK
390 
 
391 
        mov     c,_MMC_DO       // 4
392 
        setb    _MMC_CLK
393 
        rlc     a
394 
        clr     _MMC_CLK
395 
 
396 
        mov     c,_MMC_DO       // 3
397 
        setb    _MMC_CLK
398 
        rlc     a
399 
        clr     _MMC_CLK
400 
 
401 
        mov     c,_MMC_DO       // 2
402 
        setb    _MMC_CLK
403 
        rlc     a
404 
        clr     _MMC_CLK
405 
 
406 
        mov     c,_MMC_DO       // 1
407 
        setb    _MMC_CLK
408 
        rlc     a
409 
        clr     _MMC_CLK
410 
 
411 
        mov     c,_MMC_DO       // 0
412 
        setb    _MMC_CLK
413 
        rlc     a
414 
        clr     _MMC_CLK
415 
#endif
416 
        movx    @dptr,a
417 
        inc     dptr
418 
        djnz    r2,010012$
419 
__endasm;
420 
}
421 
 
422 
/* *********************************************************************
423 
   ***** FLASHX_write_byte *********************************************
424 
   ********************************************************************* */
425 
// send one bytes from buffer buf to the card
426 
void FLASHX_write_byte (BYTE b) {       // b is in dpl
427 
        b;                              // this avoids stupid warnings
428 
__asm
429 
#ifdef[MMC_bmMODE]
430 
        // up to 7 + 8*12 + 6 = 109 clocks
431 
        mov     a,_MMC_IO
432 
        anl     a, #(255 - MMC_bmCLK - MMC_bmDI )
433 
        mov     r3, a
434 
        mov     a,dpl
435 
 
436 
        rlc     a               // 7
437 
        mov     _MMC_IO,r3
438 
        jnc     0100157$
439 
        orl     _MMC_IO, #(MMC_bmDI)
440 
0100157$:
441 
        orl     _MMC_IO, #(MMC_bmCLK)
442 
 
443 
        rlc     a               // 6
444 
        mov     _MMC_IO,r3
445 
        jnc     0100156$
446 
        orl     _MMC_IO, #(MMC_bmDI)
447 
0100156$:
448 
        orl     _MMC_IO, #(MMC_bmCLK)
449 
 
450 
        rlc     a               // 5
451 
        mov     _MMC_IO,r3
452 
        jnc     0100155$
453 
        orl     _MMC_IO, #(MMC_bmDI)
454 
0100155$:
455 
        orl     _MMC_IO, #(MMC_bmCLK)
456 
 
457 
        rlc     a               // 4
458 
        mov     _MMC_IO,r3
459 
        jnc     0100154$
460 
        orl     _MMC_IO, #(MMC_bmDI)
461 
0100154$:
462 
        orl     _MMC_IO, #(MMC_bmCLK)
463 
 
464 
        rlc     a               // 3
465 
        mov     _MMC_IO,r3
466 
        jnc     0100153$
467 
        orl     _MMC_IO, #(MMC_bmDI)
468 
0100153$:
469 
        orl     _MMC_IO, #(MMC_bmCLK)
470 
 
471 
        rlc     a               // 2
472 
        mov     _MMC_IO,r3
473 
        jnc     0100152$
474 
        orl     _MMC_IO, #(MMC_bmDI)
475 
0100152$:
476 
        orl     _MMC_IO, #(MMC_bmCLK)
477 
 
478 
        rlc     a               // 1
479 
        mov     _MMC_IO,r3
480 
        jnc     0100151$
481 
        orl     _MMC_IO, #(MMC_bmDI)
482 
0100151$:
483 
        orl     _MMC_IO, #(MMC_bmCLK)
484 
 
485 
        rlc     a               // 0
486 
        mov     _MMC_IO,r3
487 
        jnc     0100150$
488 
        orl     _MMC_IO, #(MMC_bmDI)
489 
0100150$:
490 
        orl     _MMC_IO, #(MMC_bmCLK)
491 
 
492 
        mov     _MMC_IO,r3
493 
#else
494 
        // 3 + 8*7 + 4 = 63 clocks
495 
        mov     a,dpl
496 
        rlc     a               // 7
497 
 
498 
        mov     _MMC_DI,c
499 
        setb    _MMC_CLK
500 
        rlc     a               // 6
501 
        clr     _MMC_CLK
502 
 
503 
        mov     _MMC_DI,c
504 
        setb    _MMC_CLK
505 
        rlc     a               // 5
506 
        clr     _MMC_CLK
507 
 
508 
        mov     _MMC_DI,c
509 
        setb    _MMC_CLK
510 
        rlc     a               // 4
511 
        clr     _MMC_CLK
512 
 
513 
        mov     _MMC_DI,c
514 
        setb    _MMC_CLK
515 
        rlc     a               // 3
516 
        clr     _MMC_CLK
517 
 
518 
        mov     _MMC_DI,c
519 
        setb    _MMC_CLK
520 
        rlc     a               // 2
521 
        clr     _MMC_CLK
522 
 
523 
        mov     _MMC_DI,c
524 
        setb    _MMC_CLK
525 
        rlc     a               // 1
526 
        clr     _MMC_CLK
527 
 
528 
        mov     _MMC_DI,c
529 
        setb    _MMC_CLK
530 
        rlc     a               // 0
531 
        clr     _MMC_CLK
532 
 
533 
        mov     _MMC_DI,c
534 
        setb    _MMC_CLK
535 
        nop
536 
        clr     _MMC_CLK
537 
#endif
538 
__endasm;
539 
}
540 
 
541 
/* *********************************************************************
542 
   ***** FLASHX_write **************************************************
543 
   ********************************************************************* */
544 
// write len (256 id len=0) bytes from the buffer to the flash
545 
void FLASHX_write(__xdata BYTE *buf, BYTE len) {
546 
        *buf;                                   // this avoids stupid warnings
547 
        len;                                    // this too
548 
__asm                                           // *buf is in dptr, len is in _FLASHX_read_PARM_2
549 
        mov     r2,_FLASHX_read_PARM_2
550 
#ifdef[MMC_bmMODE]
551 
        // 7 + len*(2 + 8*12 + 7 ) + 6 = 13 + len*105 clocks
552 
        mov     a,_MMC_IO
553 
        anl     a, #(255 - MMC_bmCLK - MMC_bmDI )
554 
        mov     r3, a
555 
010013$:
556 
        movx    a,@dptr
557 
 
558 
        rlc     a               // 7
559 
        mov     _MMC_IO,r3
560 
        jnc     0100167$
561 
        orl     _MMC_IO, #(MMC_bmDI)
562 
0100167$:
563 
        orl     _MMC_IO, #(MMC_bmCLK)
564 
 
565 
        rlc     a               // 6
566 
        mov     _MMC_IO,r3
567 
        jnc     0100166$
568 
        orl     _MMC_IO, #(MMC_bmDI)
569 
0100166$:
570 
        orl     _MMC_IO, #(MMC_bmCLK)
571 
 
572 
        rlc     a               // 5
573 
        mov     _MMC_IO,r3
574 
        jnc     0100165$
575 
        orl     _MMC_IO, #(MMC_bmDI)
576 
0100165$:
577 
        orl     _MMC_IO, #(MMC_bmCLK)
578 
 
579 
        rlc     a               // 4
580 
        mov     _MMC_IO,r3
581 
        jnc     0100164$
582 
        orl     _MMC_IO, #(MMC_bmDI)
583 
0100164$:
584 
        orl     _MMC_IO, #(MMC_bmCLK)
585 
 
586 
        rlc     a               // 3
587 
        mov     _MMC_IO,r3
588 
        jnc     0100163$
589 
        orl     _MMC_IO, #(MMC_bmDI)
590 
0100163$:
591 
        orl     _MMC_IO, #(MMC_bmCLK)
592 
 
593 
        rlc     a               // 2
594 
        mov     _MMC_IO,r3
595 
        jnc     0100162$
596 
        orl     _MMC_IO, #(MMC_bmDI)
597 
0100162$:
598 
        orl     _MMC_IO, #(MMC_bmCLK)
599 
 
600 
        rlc     a               // 1
601 
        mov     _MMC_IO,r3
602 
        jnc     0100161$
603 
        orl     _MMC_IO, #(MMC_bmDI)
604 
0100161$:
605 
        orl     _MMC_IO, #(MMC_bmCLK)
606 
 
607 
        rlc     a               // 0
608 
        mov     _MMC_IO,r3
609 
        jnc     0100160$
610 
        orl     _MMC_IO, #(MMC_bmDI)
611 
0100160$:
612 
        orl     _MMC_IO, #(MMC_bmCLK)
613 
 
614 
        inc     dptr
615 
        djnz    r2,010013$
616 
 
617 
        mov     _MMC_IO,r3
618 
#else
619 
010013$:
620 
        // 2 + len*(3 + 8*7 - 1 + 7 ) + 4 = 6 + len*65 clocks
621 
        movx    a,@dptr
622 
        rlc     a               // 7
623 
 
624 
        mov     _MMC_DI,c
625 
        setb    _MMC_CLK
626 
        rlc     a               // 6
627 
        clr     _MMC_CLK
628 
 
629 
        mov     _MMC_DI,c
630 
        setb    _MMC_CLK
631 
        rlc     a               // 5
632 
        clr     _MMC_CLK
633 
 
634 
        mov     _MMC_DI,c
635 
        setb    _MMC_CLK
636 
        rlc     a               // 4
637 
        clr     _MMC_CLK
638 
 
639 
        mov     _MMC_DI,c
640 
        setb    _MMC_CLK
641 
        rlc     a               // 3
642 
        clr     _MMC_CLK
643 
 
644 
        mov     _MMC_DI,c
645 
        setb    _MMC_CLK
646 
        rlc     a               // 2
647 
        clr     _MMC_CLK
648 
 
649 
        mov     _MMC_DI,c
650 
        setb    _MMC_CLK
651 
        rlc     a               // 1
652 
        clr     _MMC_CLK
653 
 
654 
        mov     _MMC_DI,c
655 
        setb    _MMC_CLK
656 
        rlc     a               // 0
657 
        clr     _MMC_CLK
658 
 
659 
        mov     _MMC_DI,c
660 
        setb    _MMC_CLK
661 
        inc     dptr
662 
        clr     _MMC_CLK
663 
 
664 
        djnz    r2,010013$
665 
#endif
666 
__endasm;
667 
}
668 
 
669 
/* *********************************************************************
670 
   ***** mmc_wait_busy *************************************************
671 
   ********************************************************************* */
672 
BYTE mmc_wait_busy () {
673 
    WORD i;
674 
    FLASHX_ec = FLASH_EC_BUSY;
675 
    MMC_IO |= MMC_bmDI;                         // avoids that in-data is interpreted as command
676 
    for (i=0; (FLASHX_read_byte()!=255) && i<65535; i++ ) ;
677 
//    for (i=0; (FLASHX_read_byte()==0) && i<65535; i++ ) ;
678 
    if ( MMC__IO_DO & MMC_bmDO ) {
679 
        FLASHX_ec = 0;
680 
        return 0;
681 
    }
682 
    return 1;
683 
}
684 
 
685 
/* *********************************************************************
686 
   ***** mmc_select ****************************************************
687 
   ********************************************************************* */
688 
/*
689 
   select the card (CS) and waits if busy
690 
   returns 1 if busy
691 
*/
692 
BYTE mmc_select() {
693 
    MMC_IO |= MMC_bmCS;                         // CS = 1
694 
    mmc_clocks(8);                              // 8 dummy clocks to finish a previous command
695 
    MMC_IO &= ~MMC_bmCS;                        // CS = 0
696 
 
697 
    return mmc_wait_busy();
698 
}
699 
 
700 
/* *********************************************************************
701 
   ***** mmc_deselect **************************************************
702 
   ********************************************************************* */
703 
// de-select the card (CS) and waits if busy
704 
void mmc_deselect() {
705 
    MMC_IO |= MMC_bmDI;                         // CS = 1
706 
    mmc_clocks(8);                              // 8 dummy clocks to finish a previous command
707 
    MMC_IO |= MMC_bmCS;                         // CS = 1
708 
    mmc_clocks(8);                              // 8 more dummy clocks
709 
}
710 
 
711 
/* *********************************************************************
712 
   ***** mmc_read_response *********************************************
713 
   ********************************************************************* */
714 
// read the first response byte
715 
BYTE mmc_read_response() {
716 
        MMC_IO |= MMC_bmDI;                     // avoids that in-data is interpreted as command
717 
__asm
718 
        mov     r2,#0x255
719 
010010$:
720 
        lcall   _FLASHX_read_byte
721 
        mov     a,dpl
722 
        jnb     acc.7,010011$
723 
        djnz    r2, 010010$
724 
 
725 
010011$:
726 
        mov     dptr,#_mmc_response
727 
        movx    @dptr,a
728 
        mov     dpl,a
729 
        ret
730 
__endasm;
731 
        return 0;                                // never ever called, just to avoid stupid warnings
732 
}
733 
 
734 
/* *********************************************************************
735 
   ***** mmc_send_cmd **************************************************
736 
   ********************************************************************* */
737 
// send a command
738 
#define[mmc_send_cmd(][,$1.$2.$3.$4,$5);][{                     // send a command, argument=0
739 
    mmc_clocks(8);                              // 8 dummy clocks
740 
    mmc_last_cmd = $0;
741 
    mmc_buffer[0] = 64 | ($0 & 127);
742 
    mmc_buffer[1] = $1;
743 
    mmc_buffer[2] = $2;
744 
    mmc_buffer[3] = $3;
745 
    mmc_buffer[4] = $4;
746 
    mmc_buffer[5] = $5 | 1;
747 
    FLASHX_write(mmc_buffer,6);
748 
    mmc_read_response();
749 
}]
750 
 
751 
/* *********************************************************************
752 
   ***** mmc_wait_start ************************************************
753 
   ********************************************************************* */
754 
/*
755 
   wait for the start byte
756 
   returns 1 on error
757 
*/
758 
BYTE mmc_wait_start() {
759 
    WORD to;
760 
    to=0;
761 
    MMC_IO |= MMC_bmDI;                         // avoids that in-data is interpreted as command
762 
    while ( FLASHX_read_byte() != 0xfe ) {      // wait for the start byte
763 
        if ( ++to == 0 )                         // 65536 * 8 clocks
764 
            return 1;
765 
    }
766 
    return 0;
767 
}
768 
 
769 
/* *********************************************************************
770 
   ***** FLASHX_read_init **********************************************
771 
   ********************************************************************* */
772 
/*
773 
   Start the initialization sequence for reading sector s.
774 
   The whole sector must be read.
775 
   returns an error code (FLASH_EC_*). 0 means no error.
776 
*/
777 
BYTE FLASHX_read_init(DWORD s) {
778 
    if ( (MMC_IO & MMC_bmCS) == 0 ) {
779 
        return FLASH_EC_PENDING;                // we interrupted a pending Flash operation
780 
    }
781 
    if ( mmc_select() ) {                       // select the card
782 
        mmc_deselect();
783 
        return FLASH_EC_BUSY;
784 
    }
785 
    mmc_clocks(8);                              // 8 dummy clocks
786 
    mmc_last_cmd = 18;
787 
    mmc_buffer[0] = 18 | 64;
788 
    if ( mmc_version == 0 ) {
789 
        s = s << 1;
790 
        mmc_buffer[1] = s >> 16;
791 
        mmc_buffer[2] = s >> 8;
792 
        mmc_buffer[3] = s;
793 
        mmc_buffer[4] = 0;
794 
    }
795 
    else {
796 
        mmc_buffer[1] = s >> 24;
797 
        mmc_buffer[2] = s >> 16;
798 
        mmc_buffer[3] = s >> 8;
799 
        mmc_buffer[4] = s;
800 
    }
801 
    mmc_buffer[5] = 1;
802 
    FLASHX_write(mmc_buffer,6);
803 
    mmc_read_response();
804 
    if ( mmc_response != 0 ) {
805 
        mmc_deselect();
806 
        return FLASH_EC_CMD_ERROR;
807 
    }
808 
 
809 
    if ( mmc_wait_start() ) {                   // wait for the start byte
810 
        mmc_deselect();
811 
        return FLASH_EC_TIMEOUT;
812 
    }
813 
    return 0;
814 
}
815 
 
816 
/* *********************************************************************
817 
   ***** FLASHX_read_next **********************************************
818 
   ********************************************************************* */
819 
/*
820 
   Initialization sequence for reading the next sector.
821 
   The whole sector must be read.
822 
   returns an error code (FLASH_EC_*). 0 means no error.
823 
*/
824 
BYTE FLASHX_read_next() {
825 
    mmc_clocks(16);                             // 16 CRC clocks
826 
    if ( mmc_wait_start() ) {                   // wait for the start byte
827 
        mmc_deselect();
828 
        return FLASH_EC_TIMEOUT;
829 
    }
830 
    return 0;
831 
}
832 
 
833 
/* *********************************************************************
834 
   ***** FLASHX_read_finish ********************************************
835 
   ********************************************************************* */
836 
/*
837 
   Reads n dummy bytes (the whole sector has to be read out)
838 
   and runs the finalization sequence for a sector read.
839 
*/
840 
void FLASHX_read_finish(WORD n) {
841 
    while ( n > 32 ) {
842 
        mmc_clocks(0);                   // 256 clocks = 32 dummy bytes
843 
        n-=32;
844 
    }
845 
    if ( n>0) mmc_clocks(n << 3);
846 
    mmc_clocks(16);                     // 16 CRC clocks
847 
    mmc_send_cmd(12, 0.0.0.0, 0);        // stop transmission command, errors are ignored
848 
//    mmc_wait_busy();                  // not required here
849 
    mmc_clocks(8);                      // 8 dummy clocks
850 
   mmc_deselect();
851 
}
852 
 
853 
 
854 
/* *********************************************************************
855 
   ***** FLASHX_write_init *********************************************
856 
   ********************************************************************* */
857 
/*
858 
   Start the initialization sequence for writing sector s
859 
   The whole sector must be written.
860 
   returns an error code (FLASH_EC_*). 0 means no error.
861 
*/
862 
BYTE FLASHX_write_init(DWORD s) {
863 
    if ( (MMC_IO & MMC_bmCS) == 0 ) {
864 
        return FLASH_EC_PENDING;                // we interrupted a pending Flash operation
865 
    }
866 
    if ( mmc_select() ) {                       // select the card
867 
        mmc_deselect();
868 
        return FLASH_EC_BUSY;
869 
    }
870 
    mmc_clocks(8);                              // 8 dummy clocks
871 
    mmc_last_cmd = 25;
872 
    mmc_buffer[0] = 25 | 64;
873 
    if ( mmc_version == 0 ) {
874 
        s = s << 1;
875 
        mmc_buffer[1] = s >> 16;
876 
        mmc_buffer[2] = s >> 8;
877 
        mmc_buffer[3] = s;
878 
        mmc_buffer[4] = 0;
879 
    }
880 
    else {
881 
        mmc_buffer[1] = s >> 24;
882 
        mmc_buffer[2] = s >> 16;
883 
        mmc_buffer[3] = s >> 8;
884 
        mmc_buffer[4] = s;
885 
    }
886 
    mmc_buffer[5] = 1;
887 
    FLASHX_write(mmc_buffer,6);
888 
    mmc_read_response();
889 
    if ( mmc_response != 0 ) {
890 
        mmc_deselect();
891 
        return FLASH_EC_CMD_ERROR;
892 
    }
893 
 
894 
    MMC_IO |= MMC_bmDI;
895 
    mmc_clocks(8);                              // send one dummy byte
896 
    FLASHX_write_byte( 0xfc );                  // send the start byte
897 
    return 0;
898 
}
899 
 
900 
/* *********************************************************************
901 
   ***** FLASHX_write_finish_sector ************************************
902 
   ********************************************************************* */
903 
/*
904 
   Writes the rest of the sector (n dummy bytes + CRC, the whole sector has to be written)
905 
   but do not run the finalization procedure. This is done by FLASHX_write_finish
906 
   or FLASHX_write_next, i.e. these functions must be called after FLASHX_write_finish_sector.
907 
 
908 
   Between FLASHX_write_finish / FLASHX_write_next and FLASHX_write_finish_sector some code
909 
   may be executed because FLASHX_write_finish / FLASHX_write_next start with
910 
   mmc_wait_busy().
911 
 
912 
   Returns an error code (FLASH_EC_*). 0 means no error.
913 
*/
914 
BYTE FLASHX_write_finish_sector (WORD n) {
915 
    MMC_IO &= ~MMC_bmDI;                        // value of the dummy data is 0
916 
    while ( n > 32 ) {
917 
        mmc_clocks(0);                           // 256 clocks = 32 dummy bytes
918 
        n-=32;
919 
    }
920 
    if ( n>0) mmc_clocks(n << 3);
921 
 
922 
    MMC_IO |= MMC_bmDI;
923 
    mmc_clocks(16);                             // 16 CRC clocks
924 
 
925 
    if ( (FLASHX_read_byte() & 0xf) != 5 ) {    // data response: last four bits must be 5
926 
       FLASHX_ec = FLASH_EC_WRITE_ERROR;
927 
       mmc_send_cmd(12, 0.0.0.0, 0);             // stop transmission command, errors are ignored
928 
       mmc_clocks(8);                           // 8 dummy clocks
929 
       mmc_deselect();
930 
       return FLASH_EC_WRITE_ERROR;
931 
    }
932 
    return 0;
933 
}
934 
 
935 
/* *********************************************************************
936 
   ***** FLASHX_write_finish *******************************************
937 
   ********************************************************************* */
938 
/*
939 
   Stops the write transimssion, see FLASHX_write_finish1.
940 
*/
941 
void FLASHX_write_finish () {
942 
    mmc_wait_busy();
943 
    FLASHX_write_byte( 0xfd );                  // send the stop byte
944 
    mmc_clocks(8);                              // 8 dummy clocks
945 
    mmc_deselect();
946 
}
947 
 
948 
/* *********************************************************************
949 
   ***** FLASHX_write_next *********************************************
950 
   ********************************************************************* */
951 
/*
952 
   Prepare the nexte sector for writing, see FLASHX_write_finish_sector.
953 
*/
954 
void FLASHX_write_next () {
955 
    mmc_wait_busy();
956 
    FLASHX_write_byte( 0xfc );                  // send the stop byte
957 
}
958 
 
959 
/* *********************************************************************
960 
   ***** FLASHX_init ***************************************************
961 
   ********************************************************************* */
962 
// init the card
963 
void FLASHX_init() {
964 
    BYTE i, j, k;
965 
 
966 
#ifeq[UFM_1_15X_DETECTION_ENABLED][1]
967 
    if ( is_ufm_1_15x ) {
968 
        FLASHX_enabled = 0;
969 
        FLASHX_ec = FLASH_EC_NOTSUPPORTED;
970 
        return;
971 
    }
972 
#endif
973 
 
974 
    FLASHX_enabled = 1;
975 
    FLASHX_sector_size = 512;
976 
    mmc_version = 0;
977 
 
978 
    OEMMC_PORT = OEMMC_PORT | ( MMC_bmCS | MMC_bmDI | MMC_bmCLK );
979 
    OEMMC__PORT_DO = OEMMC__PORT_DO & ~MMC_bmDO;
980 
 
981 
    MMC_IO |= MMC_bmDI;
982 
    MMC_IO |= MMC_bmCS;
983 
    mmc_clocks(0);                               // 256 clocks
984 
 
985 
    mmc_select();                               // select te card
986 
    FLASHX_ec = FLASH_EC_BUSY;
987 
 
988 
    mmc_send_cmd(0, 0.0.0.0, 0x95);              // send reset command
989 
    if ( mmc_response & ~1 ) {                  // check for errors
990 
        wait(50);
991 
        mmc_send_cmd(0, 0.0.0.0, 0x95);          // 2nd try
992 
        if ( mmc_response & ~1 )                // check for errors
993 
            goto mmc_init_cmd_err;
994 
    }
995 
 
996 
    // send cmd8, valid ? 2.0 mode : 1.xx mode
997 
    mmc_send_cmd(8, 0.0.1.0xaa, 0x87);
998 
    if ( ( mmc_response & bmBIT2) == 0 ) {
999 
        if ( (mmc_response & 0xfe) != 0 )
1000 
            goto mmc_init_cmd_err;
1001 
        FLASHX_read(mmc_buffer,4);
1002 
        if ( ( (mmc_buffer[2] & 15) != 1) || (mmc_buffer[3] != 0xaa ) ) {
1003 
            FLASHX_ec = FLASH_EC_NOTSUPPORTED;
1004 
            goto mmc_init_err;
1005 
        }
1006 
        mmc_version=1;
1007 
    }
1008 
 
1009 
    // CMD1 is not recommended, therefore we try ACMD41 first
1010 
    k=mmc_version ? 64 : 0;
1011 
    mmc_send_cmd(55, 0.0.0.0, 0);
1012 
    if ( (mmc_response & 0xfe) == 0 )
1013 
        mmc_send_cmd(41, k.0.0.0, 0);
1014 
    j = mmc_response & 0xfe;
1015 
 
1016 
    for ( i=0; mmc_response != 0 && i<255; i++ ) {        // send the init command and wait wait (up to 1s) until ready
1017 
        wait(4);
1018 
        if ( j ) {
1019 
            mmc_send_cmd(1, k.0.0.0, 0xff);
1020 
        }
1021 
        else {
1022 
            mmc_send_cmd(55, 0.0.0.0, 0);
1023 
            mmc_send_cmd(41, k.0.0.0, 0);
1024 
        }
1025 
    }
1026 
    if ( mmc_response != 0 ) {                   // check for errors
1027 
        goto mmc_init_cmd_err;
1028 
    }
1029 
 
1030 
    if ( mmc_version ) {
1031 
        mmc_send_cmd(58, 0.0.0.0, 0);            // check the high capacity mode
1032 
        if ( mmc_response != 0 )                 // check for errors
1033 
            goto mmc_init_cmd_err;
1034 
        FLASHX_read(mmc_buffer,4);
1035 
        if ( (mmc_buffer[0] & 64) == 0 )  // card in standard capacity mode
1036 
            mmc_version = 0;
1037 
    }
1038 
 
1039 
    mmc_send_cmd(9, 0.0.0.0, 0);         // read the CSD
1040 
    if ( mmc_wait_start() ) {
1041 
        FLASHX_ec = FLASH_EC_TIMEOUT;
1042 
        goto mmc_init_err;
1043 
    }
1044 
    FLASHX_read(mmc_buffer,16);
1045 
    mmc_clocks(16);                             // CRC is clocked out
1046 
 
1047 
    mmc_buffer[0] &= 192;
1048 
    if ( (mmc_buffer[0] & 192) == 0  ) {
1049 
        i = (mmc_buffer[5] & 15) + ((mmc_buffer[10] >> 7) | ((mmc_buffer[9] & 3) << 1)) - 7;
1050 
        FLASHX_sectors = ((mmc_buffer[8] >> 6) | (mmc_buffer[7] << 2) | ((mmc_buffer[6] & 3) << 10)) + 1;
1051 
        FLASHX_sectors = FLASHX_sectors << i;
1052 
    }
1053 
    else if ( (mmc_buffer[0] & 192) == 64  ) { // todo
1054 
        FLASHX_sectors = ( ( ((DWORD)(mmc_buffer[7] & 63) << 16) | (mmc_buffer[8] << 8) | mmc_buffer[9]  ) +1 ) << 10;
1055 
    }
1056 
    else {
1057 
        FLASHX_ec = FLASH_EC_NOTSUPPORTED;
1058 
        goto mmc_init_err;
1059 
    }
1060 
 
1061 
    FLASHX_ec = 0;
1062 
    mmc_deselect();
1063 
 
1064 
    return;
1065 
 
1066 
mmc_init_cmd_err:
1067 
    FLASHX_ec = FLASH_EC_CMD_ERROR;
1068 
mmc_init_err:
1069 
    FLASHX_enabled = 0;
1070 
    mmc_deselect();
1071 
}
1072 
 
1073 
 
1074 
/* *********************************************************************
1075 
   ***** EP0 vendor request 0x40 ***************************************
1076 
   ********************************************************************* */
1077 
// send mmc information structure (card size, error status,  ...) to the host
1078 
ADD_EP0_VENDOR_REQUEST((0x40+VCR_OFFS,,
1079 
    MEM_COPY1(FLASHX_enabled,EP0BUF,8);
1080 
    EP0BCH = 0;
1081 
    EP0BCL = 8;
1082 
,,
1083 
));;
1084 
 
1085 
/* *********************************************************************
1086 
   ***** EP0 vendor request 0x41 ***************************************
1087 
   ********************************************************************* */
1088 
void mmc_read_ep0 () {
1089 
    if ( mmc_ep0_wait ) {
1090 
        mmc_ep0_wait = 0;
1091 
        if ( mmc_wait_start() ) {               // wait for the start byte of the next block
1092 
            FLASHX_ec = FLASH_EC_TIMEOUT;
1093 
            mmc_send_cmd(12, 0.0.0.0, 0);        // stop transmission command
1094 
            mmc_clocks(8);                      // 8 dummy clocks
1095 
            mmc_deselect();
1096 
            return;
1097 
        }
1098 
    }
1099 
 
1100 
    FLASHX_read(EP0BUF, ep0_payload_transfer);
1101 
    if ( ep0_payload_remaining == 0 ) {
1102 
        mmc_clocks(16);                         // 16 CRC clocks
1103 
        mmc_send_cmd(12, 0.0.0.0, 0);            // stop transmission command, errors are ignored
1104 
//      mmc_wait_busy();                        // not required here
1105 
        mmc_clocks(8);                          // 8 dummy clocks
1106 
        mmc_deselect();
1107 
    }
1108 
    else if ( (ep0_payload_remaining & 511) == 0 ) {
1109 
        mmc_clocks(16);                         // 16 CRC clocks
1110 
        mmc_ep0_wait = 1;
1111 
    }
1112 
}
1113 
 
1114 
ADD_EP0_VENDOR_REQUEST((0x41+VCR_OFFS,,                 // read integer number of sectotrs
1115 
    if ( (MMC_IO & MMC_bmCS) == 0 ) {
1116 
        FLASHX_ec = FLASH_EC_PENDING;           // we interrupted a pending Flash operation
1117 
        EP0_STALL;
1118 
    }
1119 
    if ( mmc_select() ) {                       // select the card
1120 
        mmc_deselect();
1121 
        EP0_STALL;
1122 
    }
1123 
    mmc_clocks(8);                              // 8 dummy clocks
1124 
    mmc_last_cmd = 18;
1125 
    mmc_buffer[0] = 18 | 64;
1126 
    if ( mmc_version == 0 ) {
1127 
__asm
1128 
    clr c
1129 
    mov dptr,#(_SETUPDAT + 2)
1130 
    movx a,@dptr
1131 
    mov dptr,#(_mmc_buffer + 3)
1132 
    rlc a
1133 
    movx @dptr,a
1134 
 
1135 
    mov dptr,#(_SETUPDAT + 3)
1136 
    movx a,@dptr
1137 
    mov dptr,#(_mmc_buffer + 2)
1138 
    rlc a
1139 
    movx @dptr,a
1140 
 
1141 
    mov dptr,#(_SETUPDAT + 4)
1142 
    movx a,@dptr
1143 
    mov dptr,#(_mmc_buffer + 1)
1144 
    rlc a
1145 
    movx @dptr,a
1146 
__endasm;
1147 
        mmc_buffer[4] = 0;
1148 
    }
1149 
    else {
1150 
        mmc_buffer[1] = SETUPDAT[5];
1151 
        mmc_buffer[2] = SETUPDAT[4];
1152 
        mmc_buffer[3] = SETUPDAT[3];
1153 
        mmc_buffer[4] = SETUPDAT[2];
1154 
    }
1155 
    mmc_buffer[5] = 1;
1156 
    FLASHX_write(mmc_buffer,6);
1157 
    mmc_read_response();
1158 
    if ( mmc_response != 0 ) {
1159 
        FLASHX_ec = FLASH_EC_CMD_ERROR;
1160 
        mmc_deselect();
1161 
        EP0_STALL;
1162 
    }
1163 
 
1164 
    mmc_ep0_wait = 1;
1165 
    mmc_read_ep0();
1166 
    if ( FLASHX_ec != 0 ) {
1167 
        EP0_STALL;
1168 
    }
1169 
    EP0BCH = 0;
1170 
    EP0BCL = ep0_payload_transfer;
1171 
,,
1172 
    if ( ep0_payload_transfer != 0 ) {
1173 
        FLASHX_ec = 0;
1174 
        mmc_read_ep0();
1175 
        if ( FLASHX_ec != 0 ) {
1176 
            EP0_STALL;
1177 
        }
1178 
    }
1179 
    EP0BCH = 0;
1180 
    EP0BCL = ep0_payload_transfer;
1181 
));;
1182 
 
1183 
/* *********************************************************************
1184 
   ***** EP0 vendor command 0x42 ***************************************
1185 
   ********************************************************************* */
1186 
void mmc_send_ep0 () {
1187 
    if ( mmc_ep0_wait ) {
1188 
        mmc_ep0_wait = 0;
1189 
        mmc_wait_busy();
1190 
        FLASHX_write_byte( 0xfc );                      // send the start byte of the next data block
1191 
    }
1192 
 
1193 
    FLASHX_write(EP0BUF, ep0_payload_transfer);
1194 
    if ( (ep0_payload_remaining & 511) == 0 ) {
1195 
        MMC_IO |= MMC_bmDI;
1196 
        mmc_clocks(16);                                 // 16 CRC clocks
1197 
 
1198 
        if ( (FLASHX_read_byte() & 0xf) != 5 ) {                // data response: last four bits must be 5
1199 
           FLASHX_ec = FLASH_EC_WRITE_ERROR;
1200 
           mmc_send_cmd(12, 0.0.0.0, 0);         // stop transmission command, errors are ignored
1201 
           mmc_clocks(8);                               // 8 dummy clocks
1202 
           mmc_deselect();
1203 
        }
1204 
 
1205 
        if ( ep0_payload_remaining != 0 ) {
1206 
            mmc_ep0_wait = 1;
1207 
        }
1208 
        else {
1209 
            mmc_wait_busy();
1210 
            FLASHX_write_byte( 0xfd );                  // send the stop byte
1211 
            mmc_clocks(8);                              // 8 dummy clocks
1212 
            mmc_deselect();
1213 
        }
1214 
    }
1215 
}
1216 
 
1217 
ADD_EP0_VENDOR_COMMAND((0x42+VCR_OFFS,,                 // write integer number of sectors
1218 
    if ( (MMC_IO & MMC_bmCS) == 0 ) {
1219 
        FLASHX_ec = FLASH_EC_PENDING;           // we interrupted a pending Flash operation
1220 
        EP0_STALL;
1221 
    }
1222 
    if ( mmc_select() ) {                       // select the card
1223 
        mmc_deselect();
1224 
        EP0_STALL;
1225 
    }
1226 
    mmc_clocks(8);                              // 8 dummy clocks
1227 
    mmc_last_cmd = 25;
1228 
    mmc_buffer[0] = 25 | 64;
1229 
    if ( mmc_version == 0 ) {
1230 
__asm
1231 
    clr c
1232 
    mov dptr,#(_SETUPDAT + 2)
1233 
    movx a,@dptr
1234 
    mov dptr,#(_mmc_buffer + 3)
1235 
    rlc a
1236 
    movx @dptr,a
1237 
 
1238 
    mov dptr,#(_SETUPDAT + 3)
1239 
    movx a,@dptr
1240 
    mov dptr,#(_mmc_buffer + 2)
1241 
    rlc a
1242 
    movx @dptr,a
1243 
 
1244 
    mov dptr,#(_SETUPDAT + 4)
1245 
    movx a,@dptr
1246 
    mov dptr,#(_mmc_buffer + 1)
1247 
    rlc a
1248 
    movx @dptr,a
1249 
__endasm;
1250 
        mmc_buffer[4] = 0;
1251 
    }
1252 
    else {
1253 
        mmc_buffer[1] = SETUPDAT[5];
1254 
        mmc_buffer[2] = SETUPDAT[4];
1255 
        mmc_buffer[3] = SETUPDAT[3];
1256 
        mmc_buffer[4] = SETUPDAT[2];
1257 
    }
1258 
 
1259 
    mmc_buffer[5] = 1;
1260 
    FLASHX_write(mmc_buffer,6);
1261 
    mmc_read_response();
1262 
    if ( mmc_response != 0 ) {
1263 
        FLASHX_ec = FLASH_EC_CMD_ERROR;
1264 
        mmc_deselect();
1265 
        EP0_STALL;
1266 
    }
1267 
 
1268 
    MMC_IO |= MMC_bmDI;
1269 
    mmc_clocks(8);                              // send one dummy byte
1270 
    FLASHX_write_byte( 0xfc );                  // send the start byte
1271 
    mmc_ep0_wait = 0;
1272 
,,
1273 
    if ( ep0_payload_transfer != 0 ) {
1274 
        FLASHX_ec = 0;
1275 
        mmc_send_ep0();
1276 
        if ( FLASHX_ec != 0 ) {
1277 
            EP0_STALL;
1278 
        }
1279 
    }
1280 
));;
1281 
 
1282 
/* *********************************************************************
1283 
   ***** EP0 vendor request 0x43 ***************************************
1284 
   ********************************************************************* */
1285 
// send detailed MMC status plus debug information
1286 
ADD_EP0_VENDOR_REQUEST((0x43+VCR_OFFS,,                 // this may interrupt a pending operation
1287 
    MEM_COPY1(FLASHX_ec,EP0BUF+2,20);
1288 
    EP0BUF[22] = (MMC__IO_DO & MMC_bmDO) == 0;
1289 
    mmc_select();
1290 
    mmc_send_cmd(13, 0.0.0.0, 0);
1291 
    EP0BUF[0] = mmc_response;
1292 
    EP0BUF[1] = FLASHX_read_byte();
1293 
    mmc_deselect();
1294 
    EP0BCH = 0;
1295 
    EP0BCL = 23;
1296 
,,
1297 
));;
1298 
 
1299 
#endif  /*ZTEX_FLASH1_H*/

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