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ZTEX |
/*%
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ZTEX Firmware Kit for EZ-USB FX2 Microcontrollers
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Copyright (C) 2009-2017 ZTEX GmbH.
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http://www.ztex.de
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This Source Code Form is subject to the terms of the Mozilla Public
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License, v. 2.0. If a copy of the MPL was not distributed with this file,
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You can obtain one at http://mozilla.org/MPL/2.0/.
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Alternatively, the contents of this file may be used under the terms
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of the GNU General Public License Version 3, as described below:
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License version 3 as
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published by the Free Software Foundation.
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This program is distributed in the hope that it will be useful, but
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WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program; if not, see http://www.gnu.org/licenses/.
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%*/
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/*
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Interrupt routines
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*/
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#ifndef[ZTEX_ISR_H]
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#define[ZTEX_ISR_H]
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__xdata BYTE ep0_prev_setup_request = 0xff;
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__xdata BYTE ep0_vendor_cmd_setup = 0;
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__xdata WORD ISOFRAME_COUNTER[4] = {0, 0, 0, 0}; // counters for iso frames automatically reset by sync frame request
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/* *********************************************************************
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***** toggleData ****************************************************
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********************************************************************* */
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static void resetToggleData () {
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#define[RESET_TOGGLE_DATA_EP(][);][
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#ifeq[EP$0_DIR][OUT]
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TOGCTL = $0; // EP$0 out
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TOGCTL = $0 | bmBIT5;
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#endif
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#ifeq[EP$0_DIR][IN]
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TOGCTL = bmBIT4 | $0; // EP$0 in
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TOGCTL = bmBIT4 | $0 | bmBIT5;
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#endif]
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TOGCTL = 0; // EP0 out
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TOGCTL = 0 | bmBIT5;
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TOGCTL = 0x10; // EP0 in
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TOGCTL = 0x10 | bmBIT5;
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#ifeq[EP1OUT_DIR][OUT]
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TOGCTL = 1; // EP1 out
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TOGCTL = 1 | bmBIT5;
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#endif
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#ifeq[EP1IN_DIR][IN]
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TOGCTL = 0x11; // EP1 in
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TOGCTL = 0x11 | bmBIT5;
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#endif
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RESET_TOGGLE_DATA_EP(2);
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RESET_TOGGLE_DATA_EP(4);
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RESET_TOGGLE_DATA_EP(6);
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RESET_TOGGLE_DATA_EP(8);
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}
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/* *********************************************************************
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***** getStringDescriptor *******************************************
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********************************************************************* */
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#define[SEND_STRING_DESCRIPTOR(][);][sendStringDescriptor(LSB($0), MSB($0), sizeof($0) );]
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static void sendStringDescriptor (BYTE loAddr, BYTE hiAddr, BYTE size)
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{
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BYTE b,i;
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if ( size > 31) size = 31;
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if (SETUPDAT[7] == 0 && SETUPDAT[6]<size ) size = SETUPDAT[6];
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AUTOPTRSETUP = 7;
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AUTOPTRL1 = loAddr;
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AUTOPTRH1 = hiAddr;
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AUTOPTRL2 = (BYTE)(((unsigned short)(&EP0BUF))+1);
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AUTOPTRH2 = (BYTE)((((unsigned short)(&EP0BUF))+1) >> 8);
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XAUTODAT2 = 3;
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b=XAUTODAT1;
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for (i=0; (b!=0) && (i<size); i++) {
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XAUTODAT2 = b;
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XAUTODAT2 = 0;
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b = XAUTODAT1;
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}
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i = (i+1) << 1;
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EP0BUF[0] = i;
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EP0BUF[1] = 3;
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EP0BCH = 0;
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EP0BCL = i;
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}
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/* *********************************************************************
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***** ep0_payload_update ********************************************
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********************************************************************* */
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static void ep0_payload_update() {
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ep0_payload_transfer = ( ep0_payload_remaining > 64 ) ? 64 : ep0_payload_remaining;
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ep0_payload_remaining -= ep0_payload_transfer;
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}
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/* *********************************************************************
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***** ep0_vendor_cmd_su **********************************************
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********************************************************************* */
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static void ep0_vendor_cmd_su() {
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switch ( ep0_prev_setup_request ) {
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EP0_VENDOR_COMMANDS_SU;
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default:
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EP0CS |= 0x01; // set stall, unknown request
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}
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}
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/* *********************************************************************
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***** SUDAV_ISR *****************************************************
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********************************************************************* */
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static void SUDAV_ISR () __interrupt
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{
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BYTE a;
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ep0_prev_setup_request = bRequest;
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SUDPTRCTL = 1;
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// standard USB requests
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switch ( bRequest ) {
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case 0x00: // get status
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switch(SETUPDAT[0]) {
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case 0x80: // self powered and remote
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EP0BUF[0] = 0; // not self-powered, no remote wakeup
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EP0BUF[1] = 0;
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EP0BCH = 0;
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EP0BCL = 2;
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break;
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case 0x81: // interface (reserved)
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EP0BUF[0] = 0; // always return zeros
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EP0BUF[1] = 0;
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EP0BCH = 0;
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EP0BCL = 2;
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break;
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case 0x82:
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switch ( SETUPDAT[4] ) {
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case 0x00 :
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case 0x80 :
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EP0BUF[0] = EP0CS & bmBIT0;
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break;
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case 0x01 :
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EP0BUF[0] = EP1OUTCS & bmBIT0;
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break;
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case 0x81 :
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EP0BUF[0] = EP1INCS & bmBIT0;
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break;
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default:
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EP0BUF[0] = EPXCS[ ((SETUPDAT[4] >> 1)-1) & 3 ] & bmBIT0;
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break;
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}
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EP0BUF[1] = 0;
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EP0BCH = 0;
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EP0BCL = 2;
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break;
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}
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break;
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case 0x01: // disable feature, e.g. remote wake, stall bit
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if ( SETUPDAT[0] == 2 && SETUPDAT[2] == 0 ) {
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switch ( SETUPDAT[4] ) {
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case 0x00 :
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case 0x80 :
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EP0CS &= ~bmBIT0;
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break;
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case 0x01 :
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EP1OUTCS &= ~bmBIT0;
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break;
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case 0x81 :
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EP1INCS &= ~bmBIT0;
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break;
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default:
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EPXCS[ ((SETUPDAT[4] >> 1)-1) & 3 ] &= ~bmBIT0;
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break;
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}
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}
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break;
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case 0x03: // enable feature, e.g. remote wake, test mode, stall bit
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if ( SETUPDAT[0] == 2 && SETUPDAT[2] == 0 ) {
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switch ( SETUPDAT[4] ) {
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case 0x00 :
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case 0x80 :
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EP0CS |= bmBIT0;
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break;
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case 0x01 :
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EP1OUTCS |= bmBIT0;
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break;
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case 0x81 :
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EP1INCS |= bmBIT0;
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break;
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default:
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EPXCS[ ((SETUPDAT[4] >> 1)-1) & 3 ] |= ~bmBIT0;
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break;
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}
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a = ( (SETUPDAT[4] & 0x80) >> 3 ) | (SETUPDAT[4] & 0x0f);
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TOGCTL = a;
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TOGCTL = a | bmBIT5;
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}
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break;
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case 0x06: // get descriptor
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switch(SETUPDAT[3]) {
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case 0x01: // device
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SUDPTRH = MSB(&DeviceDescriptor);
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SUDPTRL = LSB(&DeviceDescriptor);
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break;
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case 0x02: // configuration
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if (USBCS & bmBIT7) {
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SUDPTRH = MSB(&HighSpeedConfigDescriptor);
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SUDPTRL = LSB(&HighSpeedConfigDescriptor);
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}
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else {
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SUDPTRH = MSB(&FullSpeedConfigDescriptor);
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SUDPTRL = LSB(&FullSpeedConfigDescriptor);
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}
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break;
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case 0x03: // strings
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switch (SETUPDAT[2]) {
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case 1:
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SEND_STRING_DESCRIPTOR(manufacturerString);
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break;
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case 2:
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SEND_STRING_DESCRIPTOR(productString);
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break;
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case 3:
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SEND_STRING_DESCRIPTOR(SN_STRING);
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break;
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case 4:
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SEND_STRING_DESCRIPTOR(configurationString);
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break;
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default:
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SUDPTRH = MSB(&LangStringDescriptor);
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SUDPTRL = LSB(&LangStringDescriptor);
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break;
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}
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break;
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case 0x06: // device qualifier
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SUDPTRH = MSB(&DeviceQualifierDescriptor);
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SUDPTRL = LSB(&DeviceQualifierDescriptor);
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break;
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case 0x07: // other speed configuration
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if (USBCS & bmBIT7) {
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SUDPTRH = MSB(&FullSpeedConfigDescriptor);
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SUDPTRL = LSB(&FullSpeedConfigDescriptor);
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}
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else {
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SUDPTRH = MSB(&HighSpeedConfigDescriptor);
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SUDPTRL = LSB(&HighSpeedConfigDescriptor);
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}
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break;
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default:
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EP0CS |= 0x01; // set stall, unknown descriptor
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}
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break;
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case 0x07: // set descriptor
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break;
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case 0x08: // get configuration
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EP0BUF[0] = 0; // only one configuration
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EP0BCH = 0;
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EP0BCL = 1;
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break;
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case 0x09: // set configuration
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resetToggleData();
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break; // do nothing since we have only one configuration
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case 0x0a: // get alternate setting for an interface
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EP0BUF[0] = 0; // only one alternate setting
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EP0BCH = 0;
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EP0BCL = 1;
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break;
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| 276 |
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case 0x0b: // set alternate setting for an interface
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resetToggleData();
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break; // do nothing since we have only on alternate setting
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| 279 |
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case 0x0c: // sync frame
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if ( SETUPDAT[0] == 0x82 ) {
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ISOFRAME_COUNTER[ ((SETUPDAT[4] >> 1)-1) & 3 ] = 0;
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| 282 |
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EP0BUF[0] = USBFRAMEL; // use current frame as sync frame, i hope that works
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| 283 |
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EP0BUF[1] = USBFRAMEH;
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| 284 |
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EP0BCH = 0;
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| 285 |
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EP0BCL = 2;
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| 286 |
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}
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| 287 |
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break; // do nothing since we have only on alternate setting
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| 288 |
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| 289 |
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}
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| 290 |
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| 291 |
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// vendor request and commands
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| 292 |
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switch ( bmRequestType ) {
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| 293 |
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case 0xc0: // vendor request
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| 294 |
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ep0_payload_remaining = (SETUPDAT[7] << 8) | SETUPDAT[6];
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| 295 |
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ep0_payload_update();
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| 296 |
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| 297 |
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switch ( bRequest ) {
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| 298 |
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case 0x22: // get ZTEX descriptor
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| 299 |
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SUDPTRCTL = 0;
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| 300 |
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EP0BCH = 0;
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| 301 |
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EP0BCL = ZTEX_DESCRIPTOR_LEN;
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| 302 |
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SUDPTRH = MSB(ZTEX_DESCRIPTOR_OFFS);
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| 303 |
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SUDPTRL = LSB(ZTEX_DESCRIPTOR_OFFS);
|
| 304 |
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break;
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| 305 |
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EP0_VENDOR_REQUESTS_SU;
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| 306 |
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default:
|
| 307 |
|
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EP0CS |= 0x01; // set stall, unknown request
|
| 308 |
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}
|
| 309 |
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break;
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| 310 |
|
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case 0x40: // vendor command
|
| 311 |
|
|
/* vendor commands may overlap if they are send without pause. To avoid
|
| 312 |
|
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synchronization problems the setup sequences are executed in EP0OUT_ISR, i.e.
|
| 313 |
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after the first packet of payload data received. */
|
| 314 |
|
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if ( SETUPDAT[7]!=0 || SETUPDAT[6]!=0 ) {
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| 315 |
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ep0_vendor_cmd_setup = 1;
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| 316 |
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EP0BCL = 0;
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| 317 |
|
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EXIF &= ~bmBIT4; // clear main USB interrupt flag
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| 318 |
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USBIRQ = bmBIT0; // clear SUADV IRQ
|
| 319 |
|
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return; // don't clear HSNAK bit. This is done after the command has completed
|
| 320 |
|
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}
|
| 321 |
|
|
ep0_vendor_cmd_su(); // setup sequences of vendor command with no payload ara executed immediately
|
| 322 |
|
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EP0BCL = 0;
|
| 323 |
|
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break;
|
| 324 |
|
|
}
|
| 325 |
|
|
|
| 326 |
|
|
EXIF &= ~bmBIT4; // clear main USB interrupt flag
|
| 327 |
|
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USBIRQ = bmBIT0; // clear SUADV IRQ
|
| 328 |
|
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EP0CS |= 0x80; // clear the HSNAK bit
|
| 329 |
|
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}
|
| 330 |
|
|
|
| 331 |
|
|
/* *********************************************************************
|
| 332 |
|
|
***** SOF_ISR *******************************************************
|
| 333 |
|
|
********************************************************************* */
|
| 334 |
|
|
void SOF_ISR() __interrupt
|
| 335 |
|
|
{
|
| 336 |
|
|
EXIF &= ~bmBIT4;
|
| 337 |
|
|
USBIRQ = bmBIT1;
|
| 338 |
|
|
}
|
| 339 |
|
|
|
| 340 |
|
|
/* *********************************************************************
|
| 341 |
|
|
***** SUTOK_ISR *****************************************************
|
| 342 |
|
|
********************************************************************* */
|
| 343 |
|
|
void SUTOK_ISR() __interrupt
|
| 344 |
|
|
{
|
| 345 |
|
|
EXIF &= ~bmBIT4;
|
| 346 |
|
|
USBIRQ = bmBIT2;
|
| 347 |
|
|
}
|
| 348 |
|
|
|
| 349 |
|
|
/* *********************************************************************
|
| 350 |
|
|
***** SUSP_ISR ******************************************************
|
| 351 |
|
|
********************************************************************* */
|
| 352 |
|
|
void SUSP_ISR() __interrupt
|
| 353 |
|
|
{
|
| 354 |
|
|
EXIF &= ~bmBIT4;
|
| 355 |
|
|
USBIRQ = bmBIT3;
|
| 356 |
|
|
}
|
| 357 |
|
|
|
| 358 |
|
|
/* *********************************************************************
|
| 359 |
|
|
***** URES_ISR ******************************************************
|
| 360 |
|
|
********************************************************************* */
|
| 361 |
|
|
void URES_ISR() __interrupt
|
| 362 |
|
|
{
|
| 363 |
|
|
EXIF &= ~bmBIT4;
|
| 364 |
|
|
USBIRQ = bmBIT4;
|
| 365 |
|
|
}
|
| 366 |
|
|
|
| 367 |
|
|
/* *********************************************************************
|
| 368 |
|
|
***** HSGRANT_ISR ***************************************************
|
| 369 |
|
|
********************************************************************* */
|
| 370 |
|
|
void HSGRANT_ISR() __interrupt
|
| 371 |
|
|
{
|
| 372 |
|
|
EXIF &= ~bmBIT4;
|
| 373 |
|
|
// while ( USBIRQ & bmBIT5 )
|
| 374 |
|
|
USBIRQ = bmBIT5;
|
| 375 |
|
|
}
|
| 376 |
|
|
|
| 377 |
|
|
/* *********************************************************************
|
| 378 |
|
|
***** EP0ACK_ISR ****************************************************
|
| 379 |
|
|
********************************************************************* */
|
| 380 |
|
|
void EP0ACK_ISR() __interrupt
|
| 381 |
|
|
{
|
| 382 |
|
|
EXIF &= ~bmBIT4; // clear USB interrupt flag
|
| 383 |
|
|
USBIRQ = bmBIT6; // clear EP0ACK IRQ
|
| 384 |
|
|
}
|
| 385 |
|
|
|
| 386 |
|
|
/* *********************************************************************
|
| 387 |
|
|
***** EP0IN_ISR *****************************************************
|
| 388 |
|
|
********************************************************************* */
|
| 389 |
|
|
static void EP0IN_ISR () __interrupt
|
| 390 |
|
|
{
|
| 391 |
|
|
EUSB = 0; // block all USB interrupts
|
| 392 |
|
|
ep0_payload_update();
|
| 393 |
|
|
switch ( ep0_prev_setup_request ) {
|
| 394 |
|
|
EP0_VENDOR_REQUESTS_DAT;
|
| 395 |
|
|
default:
|
| 396 |
|
|
EP0BCH = 0;
|
| 397 |
|
|
EP0BCL = 0;
|
| 398 |
|
|
}
|
| 399 |
|
|
EXIF &= ~bmBIT4; // clear USB interrupt flag
|
| 400 |
|
|
EPIRQ = bmBIT0; // clear EP0IN IRQ
|
| 401 |
|
|
EUSB = 1;
|
| 402 |
|
|
}
|
| 403 |
|
|
|
| 404 |
|
|
/* *********************************************************************
|
| 405 |
|
|
***** EP0OUT_ISR ****************************************************
|
| 406 |
|
|
********************************************************************* */
|
| 407 |
|
|
static void EP0OUT_ISR () __interrupt
|
| 408 |
|
|
{
|
| 409 |
|
|
EUSB = 0; // block all USB interrupts
|
| 410 |
|
|
if ( ep0_vendor_cmd_setup ) {
|
| 411 |
|
|
ep0_vendor_cmd_setup = 0;
|
| 412 |
|
|
ep0_payload_remaining = (SETUPDAT[7] << 8) | SETUPDAT[6];
|
| 413 |
|
|
ep0_vendor_cmd_su();
|
| 414 |
|
|
}
|
| 415 |
|
|
|
| 416 |
|
|
ep0_payload_update();
|
| 417 |
|
|
|
| 418 |
|
|
switch ( ep0_prev_setup_request ) {
|
| 419 |
|
|
EP0_VENDOR_COMMANDS_DAT;
|
| 420 |
|
|
}
|
| 421 |
|
|
|
| 422 |
|
|
EP0BCL = 0;
|
| 423 |
|
|
|
| 424 |
|
|
EXIF &= ~bmBIT4; // clear main USB interrupt flag
|
| 425 |
|
|
EPIRQ = bmBIT1; // clear EP0OUT IRQ
|
| 426 |
|
|
if ( ep0_payload_remaining == 0 ) {
|
| 427 |
|
|
EP0CS |= 0x80; // clear the HSNAK bit
|
| 428 |
|
|
}
|
| 429 |
|
|
EUSB = 1;
|
| 430 |
|
|
}
|
| 431 |
|
|
|
| 432 |
|
|
|
| 433 |
|
|
/* *********************************************************************
|
| 434 |
|
|
***** EP1IN_ISR *****************************************************
|
| 435 |
|
|
********************************************************************* */
|
| 436 |
|
|
void EP1IN_ISR() __interrupt
|
| 437 |
|
|
{
|
| 438 |
|
|
EXIF &= ~bmBIT4;
|
| 439 |
|
|
EPIRQ = bmBIT2;
|
| 440 |
|
|
|
| 441 |
|
|
}
|
| 442 |
|
|
|
| 443 |
|
|
/* *********************************************************************
|
| 444 |
|
|
***** EP1OUT_ISR ****************************************************
|
| 445 |
|
|
********************************************************************* */
|
| 446 |
|
|
void EP1OUT_ISR() __interrupt
|
| 447 |
|
|
{
|
| 448 |
|
|
EXIF &= ~bmBIT4;
|
| 449 |
|
|
EPIRQ = bmBIT3;
|
| 450 |
|
|
}
|
| 451 |
|
|
|
| 452 |
|
|
/* *********************************************************************
|
| 453 |
|
|
***** EP2_ISR *******************************************************
|
| 454 |
|
|
********************************************************************* */
|
| 455 |
|
|
void EP2_ISR() __interrupt
|
| 456 |
|
|
{
|
| 457 |
|
|
EXIF &= ~bmBIT4;
|
| 458 |
|
|
EPIRQ = bmBIT4;
|
| 459 |
|
|
}
|
| 460 |
|
|
|
| 461 |
|
|
/* *********************************************************************
|
| 462 |
|
|
***** EP4_ISR *******************************************************
|
| 463 |
|
|
********************************************************************* */
|
| 464 |
|
|
void EP4_ISR() __interrupt
|
| 465 |
|
|
{
|
| 466 |
|
|
EXIF &= ~bmBIT4;
|
| 467 |
|
|
EPIRQ = bmBIT5;
|
| 468 |
|
|
}
|
| 469 |
|
|
|
| 470 |
|
|
/* *********************************************************************
|
| 471 |
|
|
***** EP6_ISR *******************************************************
|
| 472 |
|
|
********************************************************************* */
|
| 473 |
|
|
void EP6_ISR() __interrupt
|
| 474 |
|
|
{
|
| 475 |
|
|
EXIF &= ~bmBIT4;
|
| 476 |
|
|
EPIRQ = bmBIT6;
|
| 477 |
|
|
}
|
| 478 |
|
|
|
| 479 |
|
|
/* *********************************************************************
|
| 480 |
|
|
***** EP8_ISR *******************************************************
|
| 481 |
|
|
********************************************************************* */
|
| 482 |
|
|
void EP8_ISR() __interrupt
|
| 483 |
|
|
{
|
| 484 |
|
|
EXIF &= ~bmBIT4;
|
| 485 |
|
|
EPIRQ = bmBIT7;
|
| 486 |
|
|
}
|
| 487 |
|
|
|
| 488 |
|
|
#endif /* ZTEX_ISR_H */
|
