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--altsyncram ADDRESS_ACLR_A="NONE" CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" CYCLONEII_M4K_COMPATIBILITY="ON" DEVICE_FAMILY="Stratix II" INDATA_ACLR_A="NONE" INIT_FILE="adder.mif" LOW_POWER_MODE="AUTO" NUMWORDS_A=512 OPERATION_MODE="SINGLE_PORT" OUTDATA_ACLR_A="NONE" OUTDATA_REG_A="UNREGISTERED" WIDTH_A=12 WIDTHAD_A=9 WRCONTROL_ACLR_A="NONE" address_a clock0 data_a q_a wren_a CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48
--VERSION_BEGIN 9.1SP2 cbx_altsyncram 2010:03:24:20:43:42:SJ cbx_cycloneii 2010:03:24:20:43:43:SJ cbx_lpm_add_sub 2010:03:24:20:43:43:SJ cbx_lpm_compare 2010:03:24:20:43:43:SJ cbx_lpm_decode 2010:03:24:20:43:43:SJ cbx_lpm_mux 2010:03:24:20:43:43:SJ cbx_mgl 2010:03:24:21:01:05:SJ cbx_stratix 2010:03:24:20:43:43:SJ cbx_stratixii 2010:03:24:20:43:43:SJ cbx_stratixiii 2010:03:24:20:43:43:SJ cbx_util_mgl 2010:03:24:20:43:43:SJ  VERSION_END
 
 
-- Copyright (C) 1991-2010 Altera Corporation
--  Your use of Altera Corporation's design tools, logic functions
--  and other software and tools, and its AMPP partner logic
--  functions, and any output files from any of the foregoing
--  (including device programming or simulation files), and any
--  associated documentation or information are expressly subject
--  to the terms and conditions of the Altera Program License
--  Subscription Agreement, Altera MegaCore Function License
--  Agreement, or other applicable license agreement, including,
--  without limitation, that your use is for the sole purpose of
--  programming logic devices manufactured by Altera and sold by
--  Altera or its authorized distributors.  Please refer to the
--  applicable agreement for further details.
 
 
FUNCTION stratixii_ram_block (clk0, clk1, clr0, clr1, ena0, ena1, portaaddr[PORT_A_ADDRESS_WIDTH-1..0], portaaddrstall, portabyteenamasks[PORT_A_BYTE_ENABLE_MASK_WIDTH-1..0], portadatain[PORT_A_DATA_WIDTH-1..0], portawe, portbaddr[PORT_B_ADDRESS_WIDTH-1..0], portbaddrstall, portbbyteenamasks[PORT_B_BYTE_ENABLE_MASK_WIDTH-1..0], portbdatain[PORT_B_DATA_WIDTH-1..0], portbrewe)
WITH ( CONNECTIVITY_CHECKING, DATA_INTERLEAVE_OFFSET_IN_BITS, DATA_INTERLEAVE_WIDTH_IN_BITS, DONT_POWER_OPTIMIZE, INIT_FILE, INIT_FILE_LAYOUT, LOGICAL_RAM_NAME, mem_init0, mem_init1, MIXED_PORT_FEED_THROUGH_MODE, OPERATION_MODE, PORT_A_ADDRESS_WIDTH = 1, PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, PORT_A_BYTE_SIZE, PORT_A_DATA_OUT_CLEAR, PORT_A_DATA_OUT_CLOCK, PORT_A_DATA_WIDTH = 1, PORT_A_DISABLE_CE_ON_INPUT_REGISTERS, PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS, PORT_A_FIRST_ADDRESS, PORT_A_FIRST_BIT_NUMBER, PORT_A_LAST_ADDRESS, PORT_A_LOGICAL_RAM_DEPTH, PORT_A_LOGICAL_RAM_WIDTH, PORT_B_ADDRESS_CLOCK, PORT_B_ADDRESS_WIDTH = 1, PORT_B_BYTE_ENABLE_CLOCK, PORT_B_BYTE_ENABLE_MASK_WIDTH = 1, PORT_B_BYTE_SIZE, PORT_B_DATA_IN_CLOCK, PORT_B_DATA_OUT_CLEAR, PORT_B_DATA_OUT_CLOCK, PORT_B_DATA_WIDTH = 1, PORT_B_DISABLE_CE_ON_INPUT_REGISTERS, PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS, PORT_B_FIRST_ADDRESS, PORT_B_FIRST_BIT_NUMBER, PORT_B_LAST_ADDRESS, PORT_B_LOGICAL_RAM_DEPTH, PORT_B_LOGICAL_RAM_WIDTH, PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK, POWER_UP_UNINITIALIZED, RAM_BLOCK_TYPE)
RETURNS ( portadataout[PORT_A_DATA_WIDTH-1..0], portbdataout[PORT_B_DATA_WIDTH-1..0]);
 
--synthesis_resources = ram_bits (AUTO) 6144
OPTIONS ALTERA_INTERNAL_OPTION = "OPTIMIZE_POWER_DURING_SYNTHESIS=NORMAL_COMPILATION";
 
SUBDESIGN altsyncram_k961
(
        address_a[8..0] :       input;
        clock0  :       input;
        data_a[11..0]   :       input;
        q_a[11..0]      :       output;
        wren_a  :       input;
)
VARIABLE
        ram_block1a0 : stratixii_ram_block
                WITH (
                        CONNECTIVITY_CHECKING = "OFF",
                        INIT_FILE = "adder.mif",
                        INIT_FILE_LAYOUT = "port_a",
                        LOGICAL_RAM_NAME = "ALTSYNCRAM",
                        OPERATION_MODE = "single_port",
                        PORT_A_ADDRESS_WIDTH = 9,
                        PORT_A_DATA_OUT_CLEAR = "none",
                        PORT_A_DATA_OUT_CLOCK = "none",
                        PORT_A_DATA_WIDTH = 1,
                        PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "on",
                        PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS = "on",
                        PORT_A_FIRST_ADDRESS = 0,
                        PORT_A_FIRST_BIT_NUMBER = 0,
                        PORT_A_LAST_ADDRESS = 511,
                        PORT_A_LOGICAL_RAM_DEPTH = 512,
                        PORT_A_LOGICAL_RAM_WIDTH = 12,
                        RAM_BLOCK_TYPE = "AUTO"
                );
        ram_block1a1 : stratixii_ram_block
                WITH (
                        CONNECTIVITY_CHECKING = "OFF",
                        INIT_FILE = "adder.mif",
                        INIT_FILE_LAYOUT = "port_a",
                        LOGICAL_RAM_NAME = "ALTSYNCRAM",
                        OPERATION_MODE = "single_port",
                        PORT_A_ADDRESS_WIDTH = 9,
                        PORT_A_DATA_OUT_CLEAR = "none",
                        PORT_A_DATA_OUT_CLOCK = "none",
                        PORT_A_DATA_WIDTH = 1,
                        PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "on",
                        PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS = "on",
                        PORT_A_FIRST_ADDRESS = 0,
                        PORT_A_FIRST_BIT_NUMBER = 1,
                        PORT_A_LAST_ADDRESS = 511,
                        PORT_A_LOGICAL_RAM_DEPTH = 512,
                        PORT_A_LOGICAL_RAM_WIDTH = 12,
                        RAM_BLOCK_TYPE = "AUTO"
                );
        ram_block1a2 : stratixii_ram_block
                WITH (
                        CONNECTIVITY_CHECKING = "OFF",
                        INIT_FILE = "adder.mif",
                        INIT_FILE_LAYOUT = "port_a",
                        LOGICAL_RAM_NAME = "ALTSYNCRAM",
                        OPERATION_MODE = "single_port",
                        PORT_A_ADDRESS_WIDTH = 9,
                        PORT_A_DATA_OUT_CLEAR = "none",
                        PORT_A_DATA_OUT_CLOCK = "none",
                        PORT_A_DATA_WIDTH = 1,
                        PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "on",
                        PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS = "on",
                        PORT_A_FIRST_ADDRESS = 0,
                        PORT_A_FIRST_BIT_NUMBER = 2,
                        PORT_A_LAST_ADDRESS = 511,
                        PORT_A_LOGICAL_RAM_DEPTH = 512,
                        PORT_A_LOGICAL_RAM_WIDTH = 12,
                        RAM_BLOCK_TYPE = "AUTO"
                );
        ram_block1a3 : stratixii_ram_block
                WITH (
                        CONNECTIVITY_CHECKING = "OFF",
                        INIT_FILE = "adder.mif",
                        INIT_FILE_LAYOUT = "port_a",
                        LOGICAL_RAM_NAME = "ALTSYNCRAM",
                        OPERATION_MODE = "single_port",
                        PORT_A_ADDRESS_WIDTH = 9,
                        PORT_A_DATA_OUT_CLEAR = "none",
                        PORT_A_DATA_OUT_CLOCK = "none",
                        PORT_A_DATA_WIDTH = 1,
                        PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "on",
                        PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS = "on",
                        PORT_A_FIRST_ADDRESS = 0,
                        PORT_A_FIRST_BIT_NUMBER = 3,
                        PORT_A_LAST_ADDRESS = 511,
                        PORT_A_LOGICAL_RAM_DEPTH = 512,
                        PORT_A_LOGICAL_RAM_WIDTH = 12,
                        RAM_BLOCK_TYPE = "AUTO"
                );
        ram_block1a4 : stratixii_ram_block
                WITH (
                        CONNECTIVITY_CHECKING = "OFF",
                        INIT_FILE = "adder.mif",
                        INIT_FILE_LAYOUT = "port_a",
                        LOGICAL_RAM_NAME = "ALTSYNCRAM",
                        OPERATION_MODE = "single_port",
                        PORT_A_ADDRESS_WIDTH = 9,
                        PORT_A_DATA_OUT_CLEAR = "none",
                        PORT_A_DATA_OUT_CLOCK = "none",
                        PORT_A_DATA_WIDTH = 1,
                        PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "on",
                        PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS = "on",
                        PORT_A_FIRST_ADDRESS = 0,
                        PORT_A_FIRST_BIT_NUMBER = 4,
                        PORT_A_LAST_ADDRESS = 511,
                        PORT_A_LOGICAL_RAM_DEPTH = 512,
                        PORT_A_LOGICAL_RAM_WIDTH = 12,
                        RAM_BLOCK_TYPE = "AUTO"
                );
        ram_block1a5 : stratixii_ram_block
                WITH (
                        CONNECTIVITY_CHECKING = "OFF",
                        INIT_FILE = "adder.mif",
                        INIT_FILE_LAYOUT = "port_a",
                        LOGICAL_RAM_NAME = "ALTSYNCRAM",
                        OPERATION_MODE = "single_port",
                        PORT_A_ADDRESS_WIDTH = 9,
                        PORT_A_DATA_OUT_CLEAR = "none",
                        PORT_A_DATA_OUT_CLOCK = "none",
                        PORT_A_DATA_WIDTH = 1,
                        PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "on",
                        PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS = "on",
                        PORT_A_FIRST_ADDRESS = 0,
                        PORT_A_FIRST_BIT_NUMBER = 5,
                        PORT_A_LAST_ADDRESS = 511,
                        PORT_A_LOGICAL_RAM_DEPTH = 512,
                        PORT_A_LOGICAL_RAM_WIDTH = 12,
                        RAM_BLOCK_TYPE = "AUTO"
                );
        ram_block1a6 : stratixii_ram_block
                WITH (
                        CONNECTIVITY_CHECKING = "OFF",
                        INIT_FILE = "adder.mif",
                        INIT_FILE_LAYOUT = "port_a",
                        LOGICAL_RAM_NAME = "ALTSYNCRAM",
                        OPERATION_MODE = "single_port",
                        PORT_A_ADDRESS_WIDTH = 9,
                        PORT_A_DATA_OUT_CLEAR = "none",
                        PORT_A_DATA_OUT_CLOCK = "none",
                        PORT_A_DATA_WIDTH = 1,
                        PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "on",
                        PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS = "on",
                        PORT_A_FIRST_ADDRESS = 0,
                        PORT_A_FIRST_BIT_NUMBER = 6,
                        PORT_A_LAST_ADDRESS = 511,
                        PORT_A_LOGICAL_RAM_DEPTH = 512,
                        PORT_A_LOGICAL_RAM_WIDTH = 12,
                        RAM_BLOCK_TYPE = "AUTO"
                );
        ram_block1a7 : stratixii_ram_block
                WITH (
                        CONNECTIVITY_CHECKING = "OFF",
                        INIT_FILE = "adder.mif",
                        INIT_FILE_LAYOUT = "port_a",
                        LOGICAL_RAM_NAME = "ALTSYNCRAM",
                        OPERATION_MODE = "single_port",
                        PORT_A_ADDRESS_WIDTH = 9,
                        PORT_A_DATA_OUT_CLEAR = "none",
                        PORT_A_DATA_OUT_CLOCK = "none",
                        PORT_A_DATA_WIDTH = 1,
                        PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "on",
                        PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS = "on",
                        PORT_A_FIRST_ADDRESS = 0,
                        PORT_A_FIRST_BIT_NUMBER = 7,
                        PORT_A_LAST_ADDRESS = 511,
                        PORT_A_LOGICAL_RAM_DEPTH = 512,
                        PORT_A_LOGICAL_RAM_WIDTH = 12,
                        RAM_BLOCK_TYPE = "AUTO"
                );
        ram_block1a8 : stratixii_ram_block
                WITH (
                        CONNECTIVITY_CHECKING = "OFF",
                        INIT_FILE = "adder.mif",
                        INIT_FILE_LAYOUT = "port_a",
                        LOGICAL_RAM_NAME = "ALTSYNCRAM",
                        OPERATION_MODE = "single_port",
                        PORT_A_ADDRESS_WIDTH = 9,
                        PORT_A_DATA_OUT_CLEAR = "none",
                        PORT_A_DATA_OUT_CLOCK = "none",
                        PORT_A_DATA_WIDTH = 1,
                        PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "on",
                        PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS = "on",
                        PORT_A_FIRST_ADDRESS = 0,
                        PORT_A_FIRST_BIT_NUMBER = 8,
                        PORT_A_LAST_ADDRESS = 511,
                        PORT_A_LOGICAL_RAM_DEPTH = 512,
                        PORT_A_LOGICAL_RAM_WIDTH = 12,
                        RAM_BLOCK_TYPE = "AUTO"
                );
        ram_block1a9 : stratixii_ram_block
                WITH (
                        CONNECTIVITY_CHECKING = "OFF",
                        INIT_FILE = "adder.mif",
                        INIT_FILE_LAYOUT = "port_a",
                        LOGICAL_RAM_NAME = "ALTSYNCRAM",
                        OPERATION_MODE = "single_port",
                        PORT_A_ADDRESS_WIDTH = 9,
                        PORT_A_DATA_OUT_CLEAR = "none",
                        PORT_A_DATA_OUT_CLOCK = "none",
                        PORT_A_DATA_WIDTH = 1,
                        PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "on",
                        PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS = "on",
                        PORT_A_FIRST_ADDRESS = 0,
                        PORT_A_FIRST_BIT_NUMBER = 9,
                        PORT_A_LAST_ADDRESS = 511,
                        PORT_A_LOGICAL_RAM_DEPTH = 512,
                        PORT_A_LOGICAL_RAM_WIDTH = 12,
                        RAM_BLOCK_TYPE = "AUTO"
                );
        ram_block1a10 : stratixii_ram_block
                WITH (
                        CONNECTIVITY_CHECKING = "OFF",
                        INIT_FILE = "adder.mif",
                        INIT_FILE_LAYOUT = "port_a",
                        LOGICAL_RAM_NAME = "ALTSYNCRAM",
                        OPERATION_MODE = "single_port",
                        PORT_A_ADDRESS_WIDTH = 9,
                        PORT_A_DATA_OUT_CLEAR = "none",
                        PORT_A_DATA_OUT_CLOCK = "none",
                        PORT_A_DATA_WIDTH = 1,
                        PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "on",
                        PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS = "on",
                        PORT_A_FIRST_ADDRESS = 0,
                        PORT_A_FIRST_BIT_NUMBER = 10,
                        PORT_A_LAST_ADDRESS = 511,
                        PORT_A_LOGICAL_RAM_DEPTH = 512,
                        PORT_A_LOGICAL_RAM_WIDTH = 12,
                        RAM_BLOCK_TYPE = "AUTO"
                );
        ram_block1a11 : stratixii_ram_block
                WITH (
                        CONNECTIVITY_CHECKING = "OFF",
                        INIT_FILE = "adder.mif",
                        INIT_FILE_LAYOUT = "port_a",
                        LOGICAL_RAM_NAME = "ALTSYNCRAM",
                        OPERATION_MODE = "single_port",
                        PORT_A_ADDRESS_WIDTH = 9,
                        PORT_A_DATA_OUT_CLEAR = "none",
                        PORT_A_DATA_OUT_CLOCK = "none",
                        PORT_A_DATA_WIDTH = 1,
                        PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "on",
                        PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS = "on",
                        PORT_A_FIRST_ADDRESS = 0,
                        PORT_A_FIRST_BIT_NUMBER = 11,
                        PORT_A_LAST_ADDRESS = 511,
                        PORT_A_LOGICAL_RAM_DEPTH = 512,
                        PORT_A_LOGICAL_RAM_WIDTH = 12,
                        RAM_BLOCK_TYPE = "AUTO"
                );
        address_a_wire[8..0]    : WIRE;
 
BEGIN
        ram_block1a[11..0].clk0 = clock0;
        ram_block1a[11..0].portaaddr[] = ( address_a_wire[8..0]);
        ram_block1a[0].portadatain[] = ( data_a[0..0]);
        ram_block1a[1].portadatain[] = ( data_a[1..1]);
        ram_block1a[2].portadatain[] = ( data_a[2..2]);
        ram_block1a[3].portadatain[] = ( data_a[3..3]);
        ram_block1a[4].portadatain[] = ( data_a[4..4]);
        ram_block1a[5].portadatain[] = ( data_a[5..5]);
        ram_block1a[6].portadatain[] = ( data_a[6..6]);
        ram_block1a[7].portadatain[] = ( data_a[7..7]);
        ram_block1a[8].portadatain[] = ( data_a[8..8]);
        ram_block1a[9].portadatain[] = ( data_a[9..9]);
        ram_block1a[10].portadatain[] = ( data_a[10..10]);
        ram_block1a[11].portadatain[] = ( data_a[11..11]);
        ram_block1a[11..0].portawe = wren_a;
        address_a_wire[] = address_a[];
        q_a[] = ( ram_block1a[11..0].portadataout[0..0]);
END;
--VALID FILE

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[/] [usimplez/] [trunk/] [QuartusII/] [db/] [altsyncram_k961.tdf] - Blame information for rev 3

Line No.	Rev	Author	Line
1	3	pas.	`--altsyncram ADDRESS_ACLR_A="NONE" CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" CYCLONEII_M4K_COMPATIBILITY="ON" DEVICE_FAMILY="Stratix II" INDATA_ACLR_A="NONE" INIT_FILE="adder.mif" LOW_POWER_MODE="AUTO" NUMWORDS_A=512 OPERATION_MODE="SINGLE_PORT" OUTDATA_ACLR_A="NONE" OUTDATA_REG_A="UNREGISTERED" WIDTH_A=12 WIDTHAD_A=9 WRCONTROL_ACLR_A="NONE" address_a clock0 data_a q_a wren_a CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48`
2			`--VERSION_BEGIN 9.1SP2 cbx_altsyncram 2010:03:24:20:43:42:SJ cbx_cycloneii 2010:03:24:20:43:43:SJ cbx_lpm_add_sub 2010:03:24:20:43:43:SJ cbx_lpm_compare 2010:03:24:20:43:43:SJ cbx_lpm_decode 2010:03:24:20:43:43:SJ cbx_lpm_mux 2010:03:24:20:43:43:SJ cbx_mgl 2010:03:24:21:01:05:SJ cbx_stratix 2010:03:24:20:43:43:SJ cbx_stratixii 2010:03:24:20:43:43:SJ cbx_stratixiii 2010:03:24:20:43:43:SJ cbx_util_mgl 2010:03:24:20:43:43:SJ VERSION_END`
3
4
5			`-- Copyright (C) 1991-2010 Altera Corporation`
6			`-- Your use of Altera Corporation's design tools, logic functions`
7			`-- and other software and tools, and its AMPP partner logic`
8			`-- functions, and any output files from any of the foregoing`
9			`-- (including device programming or simulation files), and any`
10			`-- associated documentation or information are expressly subject`
11			`-- to the terms and conditions of the Altera Program License`
12			`-- Subscription Agreement, Altera MegaCore Function License`
13			`-- Agreement, or other applicable license agreement, including,`
14			`-- without limitation, that your use is for the sole purpose of`
15			`-- programming logic devices manufactured by Altera and sold by`
16			`-- Altera or its authorized distributors. Please refer to the`
17			`-- applicable agreement for further details.`
18
19
20			`FUNCTION stratixii_ram_block (clk0, clk1, clr0, clr1, ena0, ena1, portaaddr[PORT_A_ADDRESS_WIDTH-1..0], portaaddrstall, portabyteenamasks[PORT_A_BYTE_ENABLE_MASK_WIDTH-1..0], portadatain[PORT_A_DATA_WIDTH-1..0], portawe, portbaddr[PORT_B_ADDRESS_WIDTH-1..0], portbaddrstall, portbbyteenamasks[PORT_B_BYTE_ENABLE_MASK_WIDTH-1..0], portbdatain[PORT_B_DATA_WIDTH-1..0], portbrewe)`
21			WITH ( CONNECTIVITY_CHECKING, DATA_INTERLEAVE_OFFSET_IN_BITS, DATA_INTERLEAVE_WIDTH_IN_BITS, DONT_POWER_OPTIMIZE, INIT_FILE, INIT_FILE_LAYOUT, LOGICAL_RAM_NAME, mem_init0, mem_init1, MIXED_PORT_FEED_THROUGH_MODE, OPERATION_MODE, PORT_A_ADDRESS_WIDTH = 1, PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, PORT_A_BYTE_SIZE, PORT_A_DATA_OUT_CLEAR, PORT_A_DATA_OUT_CLOCK, PORT_A_DATA_WIDTH = 1, PORT_A_DISABLE_CE_ON_INPUT_REGISTERS, PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS, PORT_A_FIRST_ADDRESS, PORT_A_FIRST_BIT_NUMBER, PORT_A_LAST_ADDRESS, PORT_A_LOGICAL_RAM_DEPTH, PORT_A_LOGICAL_RAM_WIDTH, PORT_B_ADDRESS_CLOCK, PORT_B_ADDRESS_WIDTH = 1, PORT_B_BYTE_ENABLE_CLOCK, PORT_B_BYTE_ENABLE_MASK_WIDTH = 1, PORT_B_BYTE_SIZE, PORT_B_DATA_IN_CLOCK, PORT_B_DATA_OUT_CLEAR, PORT_B_DATA_OUT_CLOCK, PORT_B_DATA_WIDTH = 1, PORT_B_DISABLE_CE_ON_INPUT_REGISTERS, PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS, PORT_B_FIRST_ADDRESS, PORT_B_FIRST_BIT_NUMBER, PORT_B_LAST_ADDRESS, PORT_B_LOGICAL_RAM_DEPTH, PORT_B_LOGICAL_RAM_WIDTH, PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK, POWER_UP_UNINITIALIZED, RAM_BLOCK_TYPE)
22			`RETURNS ( portadataout[PORT_A_DATA_WIDTH-1..0], portbdataout[PORT_B_DATA_WIDTH-1..0]);`
23
24			`--synthesis_resources = ram_bits (AUTO) 6144`
25			`OPTIONS ALTERA_INTERNAL_OPTION = "OPTIMIZE_POWER_DURING_SYNTHESIS=NORMAL_COMPILATION";`
26
27			`SUBDESIGN altsyncram_k961`
28			`(`
29			`address_a[8..0] : input;`
30			`clock0 : input;`
31			`data_a[11..0] : input;`
32			`q_a[11..0] : output;`
33			`wren_a : input;`
34			`)`
35			`VARIABLE`
36			`ram_block1a0 : stratixii_ram_block`
37			`WITH (`
38			`CONNECTIVITY_CHECKING = "OFF",`
39			`INIT_FILE = "adder.mif",`
40			`INIT_FILE_LAYOUT = "port_a",`
41			`LOGICAL_RAM_NAME = "ALTSYNCRAM",`
42			`OPERATION_MODE = "single_port",`
43			`PORT_A_ADDRESS_WIDTH = 9,`
44			`PORT_A_DATA_OUT_CLEAR = "none",`
45			`PORT_A_DATA_OUT_CLOCK = "none",`
46			`PORT_A_DATA_WIDTH = 1,`
47			`PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "on",`
48			`PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS = "on",`
49			`PORT_A_FIRST_ADDRESS = 0,`
50			`PORT_A_FIRST_BIT_NUMBER = 0,`
51			`PORT_A_LAST_ADDRESS = 511,`
52			`PORT_A_LOGICAL_RAM_DEPTH = 512,`
53			`PORT_A_LOGICAL_RAM_WIDTH = 12,`
54			`RAM_BLOCK_TYPE = "AUTO"`
55			`);`
56			`ram_block1a1 : stratixii_ram_block`
57			`WITH (`
58			`CONNECTIVITY_CHECKING = "OFF",`
59			`INIT_FILE = "adder.mif",`
60			`INIT_FILE_LAYOUT = "port_a",`
61			`LOGICAL_RAM_NAME = "ALTSYNCRAM",`
62			`OPERATION_MODE = "single_port",`
63			`PORT_A_ADDRESS_WIDTH = 9,`
64			`PORT_A_DATA_OUT_CLEAR = "none",`
65			`PORT_A_DATA_OUT_CLOCK = "none",`
66			`PORT_A_DATA_WIDTH = 1,`
67			`PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "on",`
68			`PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS = "on",`
69			`PORT_A_FIRST_ADDRESS = 0,`
70			`PORT_A_FIRST_BIT_NUMBER = 1,`
71			`PORT_A_LAST_ADDRESS = 511,`
72			`PORT_A_LOGICAL_RAM_DEPTH = 512,`
73			`PORT_A_LOGICAL_RAM_WIDTH = 12,`
74			`RAM_BLOCK_TYPE = "AUTO"`
75			`);`
76			`ram_block1a2 : stratixii_ram_block`
77			`WITH (`
78			`CONNECTIVITY_CHECKING = "OFF",`
79			`INIT_FILE = "adder.mif",`
80			`INIT_FILE_LAYOUT = "port_a",`
81			`LOGICAL_RAM_NAME = "ALTSYNCRAM",`
82			`OPERATION_MODE = "single_port",`
83			`PORT_A_ADDRESS_WIDTH = 9,`
84			`PORT_A_DATA_OUT_CLEAR = "none",`
85			`PORT_A_DATA_OUT_CLOCK = "none",`
86			`PORT_A_DATA_WIDTH = 1,`
87			`PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "on",`
88			`PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS = "on",`
89			`PORT_A_FIRST_ADDRESS = 0,`
90			`PORT_A_FIRST_BIT_NUMBER = 2,`
91			`PORT_A_LAST_ADDRESS = 511,`
92			`PORT_A_LOGICAL_RAM_DEPTH = 512,`
93			`PORT_A_LOGICAL_RAM_WIDTH = 12,`
94			`RAM_BLOCK_TYPE = "AUTO"`
95			`);`
96			`ram_block1a3 : stratixii_ram_block`
97			`WITH (`
98			`CONNECTIVITY_CHECKING = "OFF",`
99			`INIT_FILE = "adder.mif",`
100			`INIT_FILE_LAYOUT = "port_a",`
101			`LOGICAL_RAM_NAME = "ALTSYNCRAM",`
102			`OPERATION_MODE = "single_port",`
103			`PORT_A_ADDRESS_WIDTH = 9,`
104			`PORT_A_DATA_OUT_CLEAR = "none",`
105			`PORT_A_DATA_OUT_CLOCK = "none",`
106			`PORT_A_DATA_WIDTH = 1,`
107			`PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "on",`
108			`PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS = "on",`
109			`PORT_A_FIRST_ADDRESS = 0,`
110			`PORT_A_FIRST_BIT_NUMBER = 3,`
111			`PORT_A_LAST_ADDRESS = 511,`
112			`PORT_A_LOGICAL_RAM_DEPTH = 512,`
113			`PORT_A_LOGICAL_RAM_WIDTH = 12,`
114			`RAM_BLOCK_TYPE = "AUTO"`
115			`);`
116			`ram_block1a4 : stratixii_ram_block`
117			`WITH (`
118			`CONNECTIVITY_CHECKING = "OFF",`
119			`INIT_FILE = "adder.mif",`
120			`INIT_FILE_LAYOUT = "port_a",`
121			`LOGICAL_RAM_NAME = "ALTSYNCRAM",`
122			`OPERATION_MODE = "single_port",`
123			`PORT_A_ADDRESS_WIDTH = 9,`
124			`PORT_A_DATA_OUT_CLEAR = "none",`
125			`PORT_A_DATA_OUT_CLOCK = "none",`
126			`PORT_A_DATA_WIDTH = 1,`
127			`PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "on",`
128			`PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS = "on",`
129			`PORT_A_FIRST_ADDRESS = 0,`
130			`PORT_A_FIRST_BIT_NUMBER = 4,`
131			`PORT_A_LAST_ADDRESS = 511,`
132			`PORT_A_LOGICAL_RAM_DEPTH = 512,`
133			`PORT_A_LOGICAL_RAM_WIDTH = 12,`
134			`RAM_BLOCK_TYPE = "AUTO"`
135			`);`
136			`ram_block1a5 : stratixii_ram_block`
137			`WITH (`
138			`CONNECTIVITY_CHECKING = "OFF",`
139			`INIT_FILE = "adder.mif",`
140			`INIT_FILE_LAYOUT = "port_a",`
141			`LOGICAL_RAM_NAME = "ALTSYNCRAM",`
142			`OPERATION_MODE = "single_port",`
143			`PORT_A_ADDRESS_WIDTH = 9,`
144			`PORT_A_DATA_OUT_CLEAR = "none",`
145			`PORT_A_DATA_OUT_CLOCK = "none",`
146			`PORT_A_DATA_WIDTH = 1,`
147			`PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "on",`
148			`PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS = "on",`
149			`PORT_A_FIRST_ADDRESS = 0,`
150			`PORT_A_FIRST_BIT_NUMBER = 5,`
151			`PORT_A_LAST_ADDRESS = 511,`
152			`PORT_A_LOGICAL_RAM_DEPTH = 512,`
153			`PORT_A_LOGICAL_RAM_WIDTH = 12,`
154			`RAM_BLOCK_TYPE = "AUTO"`
155			`);`
156			`ram_block1a6 : stratixii_ram_block`
157			`WITH (`
158			`CONNECTIVITY_CHECKING = "OFF",`
159			`INIT_FILE = "adder.mif",`
160			`INIT_FILE_LAYOUT = "port_a",`
161			`LOGICAL_RAM_NAME = "ALTSYNCRAM",`
162			`OPERATION_MODE = "single_port",`
163			`PORT_A_ADDRESS_WIDTH = 9,`
164			`PORT_A_DATA_OUT_CLEAR = "none",`
165			`PORT_A_DATA_OUT_CLOCK = "none",`
166			`PORT_A_DATA_WIDTH = 1,`
167			`PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "on",`
168			`PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS = "on",`
169			`PORT_A_FIRST_ADDRESS = 0,`
170			`PORT_A_FIRST_BIT_NUMBER = 6,`
171			`PORT_A_LAST_ADDRESS = 511,`
172			`PORT_A_LOGICAL_RAM_DEPTH = 512,`
173			`PORT_A_LOGICAL_RAM_WIDTH = 12,`
174			`RAM_BLOCK_TYPE = "AUTO"`
175			`);`
176			`ram_block1a7 : stratixii_ram_block`
177			`WITH (`
178			`CONNECTIVITY_CHECKING = "OFF",`
179			`INIT_FILE = "adder.mif",`
180			`INIT_FILE_LAYOUT = "port_a",`
181			`LOGICAL_RAM_NAME = "ALTSYNCRAM",`
182			`OPERATION_MODE = "single_port",`
183			`PORT_A_ADDRESS_WIDTH = 9,`
184			`PORT_A_DATA_OUT_CLEAR = "none",`
185			`PORT_A_DATA_OUT_CLOCK = "none",`
186			`PORT_A_DATA_WIDTH = 1,`
187			`PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "on",`
188			`PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS = "on",`
189			`PORT_A_FIRST_ADDRESS = 0,`
190			`PORT_A_FIRST_BIT_NUMBER = 7,`
191			`PORT_A_LAST_ADDRESS = 511,`
192			`PORT_A_LOGICAL_RAM_DEPTH = 512,`
193			`PORT_A_LOGICAL_RAM_WIDTH = 12,`
194			`RAM_BLOCK_TYPE = "AUTO"`
195			`);`
196			`ram_block1a8 : stratixii_ram_block`
197			`WITH (`
198			`CONNECTIVITY_CHECKING = "OFF",`
199			`INIT_FILE = "adder.mif",`
200			`INIT_FILE_LAYOUT = "port_a",`
201			`LOGICAL_RAM_NAME = "ALTSYNCRAM",`
202			`OPERATION_MODE = "single_port",`
203			`PORT_A_ADDRESS_WIDTH = 9,`
204			`PORT_A_DATA_OUT_CLEAR = "none",`
205			`PORT_A_DATA_OUT_CLOCK = "none",`
206			`PORT_A_DATA_WIDTH = 1,`
207			`PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "on",`
208			`PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS = "on",`
209			`PORT_A_FIRST_ADDRESS = 0,`
210			`PORT_A_FIRST_BIT_NUMBER = 8,`
211			`PORT_A_LAST_ADDRESS = 511,`
212			`PORT_A_LOGICAL_RAM_DEPTH = 512,`
213			`PORT_A_LOGICAL_RAM_WIDTH = 12,`
214			`RAM_BLOCK_TYPE = "AUTO"`
215			`);`
216			`ram_block1a9 : stratixii_ram_block`
217			`WITH (`
218			`CONNECTIVITY_CHECKING = "OFF",`
219			`INIT_FILE = "adder.mif",`
220			`INIT_FILE_LAYOUT = "port_a",`
221			`LOGICAL_RAM_NAME = "ALTSYNCRAM",`
222			`OPERATION_MODE = "single_port",`
223			`PORT_A_ADDRESS_WIDTH = 9,`
224			`PORT_A_DATA_OUT_CLEAR = "none",`
225			`PORT_A_DATA_OUT_CLOCK = "none",`
226			`PORT_A_DATA_WIDTH = 1,`
227			`PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "on",`
228			`PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS = "on",`
229			`PORT_A_FIRST_ADDRESS = 0,`
230			`PORT_A_FIRST_BIT_NUMBER = 9,`
231			`PORT_A_LAST_ADDRESS = 511,`
232			`PORT_A_LOGICAL_RAM_DEPTH = 512,`
233			`PORT_A_LOGICAL_RAM_WIDTH = 12,`
234			`RAM_BLOCK_TYPE = "AUTO"`
235			`);`
236			`ram_block1a10 : stratixii_ram_block`
237			`WITH (`
238			`CONNECTIVITY_CHECKING = "OFF",`
239			`INIT_FILE = "adder.mif",`
240			`INIT_FILE_LAYOUT = "port_a",`
241			`LOGICAL_RAM_NAME = "ALTSYNCRAM",`
242			`OPERATION_MODE = "single_port",`
243			`PORT_A_ADDRESS_WIDTH = 9,`
244			`PORT_A_DATA_OUT_CLEAR = "none",`
245			`PORT_A_DATA_OUT_CLOCK = "none",`
246			`PORT_A_DATA_WIDTH = 1,`
247			`PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "on",`
248			`PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS = "on",`
249			`PORT_A_FIRST_ADDRESS = 0,`
250			`PORT_A_FIRST_BIT_NUMBER = 10,`
251			`PORT_A_LAST_ADDRESS = 511,`
252			`PORT_A_LOGICAL_RAM_DEPTH = 512,`
253			`PORT_A_LOGICAL_RAM_WIDTH = 12,`
254			`RAM_BLOCK_TYPE = "AUTO"`
255			`);`
256			`ram_block1a11 : stratixii_ram_block`
257			`WITH (`
258			`CONNECTIVITY_CHECKING = "OFF",`
259			`INIT_FILE = "adder.mif",`
260			`INIT_FILE_LAYOUT = "port_a",`
261			`LOGICAL_RAM_NAME = "ALTSYNCRAM",`
262			`OPERATION_MODE = "single_port",`
263			`PORT_A_ADDRESS_WIDTH = 9,`
264			`PORT_A_DATA_OUT_CLEAR = "none",`
265			`PORT_A_DATA_OUT_CLOCK = "none",`
266			`PORT_A_DATA_WIDTH = 1,`
267			`PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "on",`
268			`PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS = "on",`
269			`PORT_A_FIRST_ADDRESS = 0,`
270			`PORT_A_FIRST_BIT_NUMBER = 11,`
271			`PORT_A_LAST_ADDRESS = 511,`
272			`PORT_A_LOGICAL_RAM_DEPTH = 512,`
273			`PORT_A_LOGICAL_RAM_WIDTH = 12,`
274			`RAM_BLOCK_TYPE = "AUTO"`
275			`);`
276			`address_a_wire[8..0] : WIRE;`
277
278			`BEGIN`
279			`ram_block1a[11..0].clk0 = clock0;`
280			`ram_block1a[11..0].portaaddr[] = ( address_a_wire[8..0]);`
281			`ram_block1a[0].portadatain[] = ( data_a[0..0]);`
282			`ram_block1a[1].portadatain[] = ( data_a[1..1]);`
283			`ram_block1a[2].portadatain[] = ( data_a[2..2]);`
284			`ram_block1a[3].portadatain[] = ( data_a[3..3]);`
285			`ram_block1a[4].portadatain[] = ( data_a[4..4]);`
286			`ram_block1a[5].portadatain[] = ( data_a[5..5]);`
287			`ram_block1a[6].portadatain[] = ( data_a[6..6]);`
288			`ram_block1a[7].portadatain[] = ( data_a[7..7]);`
289			`ram_block1a[8].portadatain[] = ( data_a[8..8]);`
290			`ram_block1a[9].portadatain[] = ( data_a[9..9]);`
291			`ram_block1a[10].portadatain[] = ( data_a[10..10]);`
292			`ram_block1a[11].portadatain[] = ( data_a[11..11]);`
293			`ram_block1a[11..0].portawe = wren_a;`
294			`address_a_wire[] = address_a[];`
295			`q_a[] = ( ram_block1a[11..0].portadataout[0..0]);`
296			`END;`
297			`--VALID FILE`