| 1 |
3 |
pas. |
|usimplez_top
|
| 2 |
|
|
clk_i => usimplez_cpu:cpu.clk_i
|
| 3 |
|
|
clk_i => usimplez_ram:ram.clk_i
|
| 4 |
|
|
rst_i => usimplez_cpu:cpu.rst_i
|
| 5 |
|
|
we_o <= usimplez_cpu:cpu.we_o
|
| 6 |
|
|
in0_o <= usimplez_cpu:cpu.in0_o
|
| 7 |
|
|
in1_o <= usimplez_cpu:cpu.in1_o
|
| 8 |
|
|
op0_o <= usimplez_cpu:cpu.op0_o
|
| 9 |
|
|
op1_o <= usimplez_cpu:cpu.op1_o
|
| 10 |
|
|
|
| 11 |
|
|
|
| 12 |
|
|
|usimplez_top|usimplez_cpu:cpu
|
| 13 |
|
|
clk_i => Op1_o~reg0.CLK
|
| 14 |
|
|
clk_i => Op0_o~reg0.CLK
|
| 15 |
|
|
clk_i => In1_o~reg0.CLK
|
| 16 |
|
|
clk_i => In0_o~reg0.CLK
|
| 17 |
|
|
clk_i => we_o~reg0.CLK
|
| 18 |
|
|
clk_i => data_bus_o[0]~reg0.CLK
|
| 19 |
|
|
clk_i => data_bus_o[1]~reg0.CLK
|
| 20 |
|
|
clk_i => data_bus_o[2]~reg0.CLK
|
| 21 |
|
|
clk_i => data_bus_o[3]~reg0.CLK
|
| 22 |
|
|
clk_i => data_bus_o[4]~reg0.CLK
|
| 23 |
|
|
clk_i => data_bus_o[5]~reg0.CLK
|
| 24 |
|
|
clk_i => data_bus_o[6]~reg0.CLK
|
| 25 |
|
|
clk_i => data_bus_o[7]~reg0.CLK
|
| 26 |
|
|
clk_i => data_bus_o[8]~reg0.CLK
|
| 27 |
|
|
clk_i => data_bus_o[9]~reg0.CLK
|
| 28 |
|
|
clk_i => data_bus_o[10]~reg0.CLK
|
| 29 |
|
|
clk_i => data_bus_o[11]~reg0.CLK
|
| 30 |
|
|
clk_i => addr_bus_o[0]~reg0.CLK
|
| 31 |
|
|
clk_i => addr_bus_o[1]~reg0.CLK
|
| 32 |
|
|
clk_i => addr_bus_o[2]~reg0.CLK
|
| 33 |
|
|
clk_i => addr_bus_o[3]~reg0.CLK
|
| 34 |
|
|
clk_i => addr_bus_o[4]~reg0.CLK
|
| 35 |
|
|
clk_i => addr_bus_o[5]~reg0.CLK
|
| 36 |
|
|
clk_i => addr_bus_o[6]~reg0.CLK
|
| 37 |
|
|
clk_i => addr_bus_o[7]~reg0.CLK
|
| 38 |
|
|
clk_i => addr_bus_o[8]~reg0.CLK
|
| 39 |
|
|
clk_i => cp_reg_s[0].CLK
|
| 40 |
|
|
clk_i => cp_reg_s[1].CLK
|
| 41 |
|
|
clk_i => cp_reg_s[2].CLK
|
| 42 |
|
|
clk_i => cp_reg_s[3].CLK
|
| 43 |
|
|
clk_i => cp_reg_s[4].CLK
|
| 44 |
|
|
clk_i => cp_reg_s[5].CLK
|
| 45 |
|
|
clk_i => cp_reg_s[6].CLK
|
| 46 |
|
|
clk_i => cp_reg_s[7].CLK
|
| 47 |
|
|
clk_i => cp_reg_s[8].CLK
|
| 48 |
|
|
clk_i => cd_reg_s[0].CLK
|
| 49 |
|
|
clk_i => cd_reg_s[1].CLK
|
| 50 |
|
|
clk_i => cd_reg_s[2].CLK
|
| 51 |
|
|
clk_i => cd_reg_s[3].CLK
|
| 52 |
|
|
clk_i => cd_reg_s[4].CLK
|
| 53 |
|
|
clk_i => cd_reg_s[5].CLK
|
| 54 |
|
|
clk_i => cd_reg_s[6].CLK
|
| 55 |
|
|
clk_i => cd_reg_s[7].CLK
|
| 56 |
|
|
clk_i => cd_reg_s[8].CLK
|
| 57 |
|
|
clk_i => ac_reg_s[0].CLK
|
| 58 |
|
|
clk_i => ac_reg_s[1].CLK
|
| 59 |
|
|
clk_i => ac_reg_s[2].CLK
|
| 60 |
|
|
clk_i => ac_reg_s[3].CLK
|
| 61 |
|
|
clk_i => ac_reg_s[4].CLK
|
| 62 |
|
|
clk_i => ac_reg_s[5].CLK
|
| 63 |
|
|
clk_i => ac_reg_s[6].CLK
|
| 64 |
|
|
clk_i => ac_reg_s[7].CLK
|
| 65 |
|
|
clk_i => ac_reg_s[8].CLK
|
| 66 |
|
|
clk_i => ac_reg_s[9].CLK
|
| 67 |
|
|
clk_i => ac_reg_s[10].CLK
|
| 68 |
|
|
clk_i => ac_reg_s[11].CLK
|
| 69 |
|
|
clk_i => co_reg_s[0].CLK
|
| 70 |
|
|
clk_i => co_reg_s[1].CLK
|
| 71 |
|
|
clk_i => co_reg_s[2].CLK
|
| 72 |
|
|
clk_i => estado~1.DATAIN
|
| 73 |
|
|
rst_i => co_reg_s.OUTPUTSELECT
|
| 74 |
|
|
rst_i => co_reg_s.OUTPUTSELECT
|
| 75 |
|
|
rst_i => co_reg_s.OUTPUTSELECT
|
| 76 |
|
|
rst_i => ac_reg_s.OUTPUTSELECT
|
| 77 |
|
|
rst_i => ac_reg_s.OUTPUTSELECT
|
| 78 |
|
|
rst_i => ac_reg_s.OUTPUTSELECT
|
| 79 |
|
|
rst_i => ac_reg_s.OUTPUTSELECT
|
| 80 |
|
|
rst_i => ac_reg_s.OUTPUTSELECT
|
| 81 |
|
|
rst_i => ac_reg_s.OUTPUTSELECT
|
| 82 |
|
|
rst_i => ac_reg_s.OUTPUTSELECT
|
| 83 |
|
|
rst_i => ac_reg_s.OUTPUTSELECT
|
| 84 |
|
|
rst_i => ac_reg_s.OUTPUTSELECT
|
| 85 |
|
|
rst_i => ac_reg_s.OUTPUTSELECT
|
| 86 |
|
|
rst_i => ac_reg_s.OUTPUTSELECT
|
| 87 |
|
|
rst_i => ac_reg_s.OUTPUTSELECT
|
| 88 |
|
|
rst_i => cd_reg_s.OUTPUTSELECT
|
| 89 |
|
|
rst_i => cd_reg_s.OUTPUTSELECT
|
| 90 |
|
|
rst_i => cd_reg_s.OUTPUTSELECT
|
| 91 |
|
|
rst_i => cd_reg_s.OUTPUTSELECT
|
| 92 |
|
|
rst_i => cd_reg_s.OUTPUTSELECT
|
| 93 |
|
|
rst_i => cd_reg_s.OUTPUTSELECT
|
| 94 |
|
|
rst_i => cd_reg_s.OUTPUTSELECT
|
| 95 |
|
|
rst_i => cd_reg_s.OUTPUTSELECT
|
| 96 |
|
|
rst_i => cd_reg_s.OUTPUTSELECT
|
| 97 |
|
|
rst_i => cp_reg_s.OUTPUTSELECT
|
| 98 |
|
|
rst_i => cp_reg_s.OUTPUTSELECT
|
| 99 |
|
|
rst_i => cp_reg_s.OUTPUTSELECT
|
| 100 |
|
|
rst_i => cp_reg_s.OUTPUTSELECT
|
| 101 |
|
|
rst_i => cp_reg_s.OUTPUTSELECT
|
| 102 |
|
|
rst_i => cp_reg_s.OUTPUTSELECT
|
| 103 |
|
|
rst_i => cp_reg_s.OUTPUTSELECT
|
| 104 |
|
|
rst_i => cp_reg_s.OUTPUTSELECT
|
| 105 |
|
|
rst_i => cp_reg_s.OUTPUTSELECT
|
| 106 |
|
|
rst_i => addr_bus_o.OUTPUTSELECT
|
| 107 |
|
|
rst_i => addr_bus_o.OUTPUTSELECT
|
| 108 |
|
|
rst_i => addr_bus_o.OUTPUTSELECT
|
| 109 |
|
|
rst_i => addr_bus_o.OUTPUTSELECT
|
| 110 |
|
|
rst_i => addr_bus_o.OUTPUTSELECT
|
| 111 |
|
|
rst_i => addr_bus_o.OUTPUTSELECT
|
| 112 |
|
|
rst_i => addr_bus_o.OUTPUTSELECT
|
| 113 |
|
|
rst_i => addr_bus_o.OUTPUTSELECT
|
| 114 |
|
|
rst_i => addr_bus_o.OUTPUTSELECT
|
| 115 |
|
|
rst_i => data_bus_o.OUTPUTSELECT
|
| 116 |
|
|
rst_i => data_bus_o.OUTPUTSELECT
|
| 117 |
|
|
rst_i => data_bus_o.OUTPUTSELECT
|
| 118 |
|
|
rst_i => data_bus_o.OUTPUTSELECT
|
| 119 |
|
|
rst_i => data_bus_o.OUTPUTSELECT
|
| 120 |
|
|
rst_i => data_bus_o.OUTPUTSELECT
|
| 121 |
|
|
rst_i => data_bus_o.OUTPUTSELECT
|
| 122 |
|
|
rst_i => data_bus_o.OUTPUTSELECT
|
| 123 |
|
|
rst_i => data_bus_o.OUTPUTSELECT
|
| 124 |
|
|
rst_i => data_bus_o.OUTPUTSELECT
|
| 125 |
|
|
rst_i => data_bus_o.OUTPUTSELECT
|
| 126 |
|
|
rst_i => data_bus_o.OUTPUTSELECT
|
| 127 |
|
|
rst_i => we_o.OUTPUTSELECT
|
| 128 |
|
|
rst_i => estado.OUTPUTSELECT
|
| 129 |
|
|
rst_i => estado.OUTPUTSELECT
|
| 130 |
|
|
rst_i => estado.OUTPUTSELECT
|
| 131 |
|
|
rst_i => estado.OUTPUTSELECT
|
| 132 |
|
|
rst_i => In0_o~reg0.ENA
|
| 133 |
|
|
rst_i => In1_o~reg0.ENA
|
| 134 |
|
|
rst_i => Op0_o~reg0.ENA
|
| 135 |
|
|
rst_i => Op1_o~reg0.ENA
|
| 136 |
|
|
data_bus_i[0] => Add2.IN12
|
| 137 |
|
|
data_bus_i[0] => Mux44.IN1
|
| 138 |
|
|
data_bus_i[0] => cd_reg_s.DATAB
|
| 139 |
|
|
data_bus_i[1] => Add2.IN11
|
| 140 |
|
|
data_bus_i[1] => Mux43.IN1
|
| 141 |
|
|
data_bus_i[1] => cd_reg_s.DATAB
|
| 142 |
|
|
data_bus_i[2] => Add2.IN10
|
| 143 |
|
|
data_bus_i[2] => Mux42.IN1
|
| 144 |
|
|
data_bus_i[2] => cd_reg_s.DATAB
|
| 145 |
|
|
data_bus_i[3] => Add2.IN9
|
| 146 |
|
|
data_bus_i[3] => Mux41.IN1
|
| 147 |
|
|
data_bus_i[3] => cd_reg_s.DATAB
|
| 148 |
|
|
data_bus_i[4] => Add2.IN8
|
| 149 |
|
|
data_bus_i[4] => Mux40.IN1
|
| 150 |
|
|
data_bus_i[4] => cd_reg_s.DATAB
|
| 151 |
|
|
data_bus_i[5] => Add2.IN7
|
| 152 |
|
|
data_bus_i[5] => Mux39.IN1
|
| 153 |
|
|
data_bus_i[5] => cd_reg_s.DATAB
|
| 154 |
|
|
data_bus_i[6] => Add2.IN6
|
| 155 |
|
|
data_bus_i[6] => Mux38.IN1
|
| 156 |
|
|
data_bus_i[6] => cd_reg_s.DATAB
|
| 157 |
|
|
data_bus_i[7] => Add2.IN5
|
| 158 |
|
|
data_bus_i[7] => Mux37.IN1
|
| 159 |
|
|
data_bus_i[7] => cd_reg_s.DATAB
|
| 160 |
|
|
data_bus_i[8] => Add2.IN4
|
| 161 |
|
|
data_bus_i[8] => Mux36.IN1
|
| 162 |
|
|
data_bus_i[8] => cd_reg_s.DATAB
|
| 163 |
|
|
data_bus_i[9] => Add2.IN3
|
| 164 |
|
|
data_bus_i[9] => Mux35.IN1
|
| 165 |
|
|
data_bus_i[9] => co_reg_s.DATAB
|
| 166 |
|
|
data_bus_i[10] => Add2.IN2
|
| 167 |
|
|
data_bus_i[10] => Mux34.IN1
|
| 168 |
|
|
data_bus_i[10] => co_reg_s.DATAB
|
| 169 |
|
|
data_bus_i[11] => Add2.IN1
|
| 170 |
|
|
data_bus_i[11] => Mux33.IN1
|
| 171 |
|
|
data_bus_i[11] => co_reg_s.DATAB
|
| 172 |
|
|
data_bus_o[0] <= data_bus_o[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
| 173 |
|
|
data_bus_o[1] <= data_bus_o[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
| 174 |
|
|
data_bus_o[2] <= data_bus_o[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
| 175 |
|
|
data_bus_o[3] <= data_bus_o[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
| 176 |
|
|
data_bus_o[4] <= data_bus_o[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
| 177 |
|
|
data_bus_o[5] <= data_bus_o[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
| 178 |
|
|
data_bus_o[6] <= data_bus_o[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
| 179 |
|
|
data_bus_o[7] <= data_bus_o[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
| 180 |
|
|
data_bus_o[8] <= data_bus_o[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
| 181 |
|
|
data_bus_o[9] <= data_bus_o[9]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
| 182 |
|
|
data_bus_o[10] <= data_bus_o[10]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
| 183 |
|
|
data_bus_o[11] <= data_bus_o[11]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
| 184 |
|
|
addr_bus_o[0] <= addr_bus_o[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
| 185 |
|
|
addr_bus_o[1] <= addr_bus_o[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
| 186 |
|
|
addr_bus_o[2] <= addr_bus_o[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
| 187 |
|
|
addr_bus_o[3] <= addr_bus_o[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
| 188 |
|
|
addr_bus_o[4] <= addr_bus_o[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
| 189 |
|
|
addr_bus_o[5] <= addr_bus_o[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
| 190 |
|
|
addr_bus_o[6] <= addr_bus_o[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
| 191 |
|
|
addr_bus_o[7] <= addr_bus_o[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
| 192 |
|
|
addr_bus_o[8] <= addr_bus_o[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
| 193 |
|
|
we_o <= we_o~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
| 194 |
|
|
In0_o <= In0_o~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
| 195 |
|
|
In1_o <= In1_o~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
| 196 |
|
|
Op0_o <= Op0_o~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
| 197 |
|
|
Op1_o <= Op1_o~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
| 198 |
|
|
|
| 199 |
|
|
|
| 200 |
|
|
|usimplez_top|usimplez_ram:ram
|
| 201 |
|
|
clk_i => ram~21.CLK
|
| 202 |
|
|
clk_i => ram~0.CLK
|
| 203 |
|
|
clk_i => ram~1.CLK
|
| 204 |
|
|
clk_i => ram~2.CLK
|
| 205 |
|
|
clk_i => ram~3.CLK
|
| 206 |
|
|
clk_i => ram~4.CLK
|
| 207 |
|
|
clk_i => ram~5.CLK
|
| 208 |
|
|
clk_i => ram~6.CLK
|
| 209 |
|
|
clk_i => ram~7.CLK
|
| 210 |
|
|
clk_i => ram~8.CLK
|
| 211 |
|
|
clk_i => ram~9.CLK
|
| 212 |
|
|
clk_i => ram~10.CLK
|
| 213 |
|
|
clk_i => ram~11.CLK
|
| 214 |
|
|
clk_i => ram~12.CLK
|
| 215 |
|
|
clk_i => ram~13.CLK
|
| 216 |
|
|
clk_i => ram~14.CLK
|
| 217 |
|
|
clk_i => ram~15.CLK
|
| 218 |
|
|
clk_i => ram~16.CLK
|
| 219 |
|
|
clk_i => ram~17.CLK
|
| 220 |
|
|
clk_i => ram~18.CLK
|
| 221 |
|
|
clk_i => ram~19.CLK
|
| 222 |
|
|
clk_i => ram~20.CLK
|
| 223 |
|
|
clk_i => addr_reg_s[0].CLK
|
| 224 |
|
|
clk_i => addr_reg_s[1].CLK
|
| 225 |
|
|
clk_i => addr_reg_s[2].CLK
|
| 226 |
|
|
clk_i => addr_reg_s[3].CLK
|
| 227 |
|
|
clk_i => addr_reg_s[4].CLK
|
| 228 |
|
|
clk_i => addr_reg_s[5].CLK
|
| 229 |
|
|
clk_i => addr_reg_s[6].CLK
|
| 230 |
|
|
clk_i => addr_reg_s[7].CLK
|
| 231 |
|
|
clk_i => addr_reg_s[8].CLK
|
| 232 |
|
|
clk_i => ram.CLK0
|
| 233 |
|
|
addr_i[0] => ram~8.DATAIN
|
| 234 |
|
|
addr_i[0] => addr_reg_s[0].DATAIN
|
| 235 |
|
|
addr_i[0] => ram.WADDR
|
| 236 |
|
|
addr_i[1] => ram~7.DATAIN
|
| 237 |
|
|
addr_i[1] => addr_reg_s[1].DATAIN
|
| 238 |
|
|
addr_i[1] => ram.WADDR1
|
| 239 |
|
|
addr_i[2] => ram~6.DATAIN
|
| 240 |
|
|
addr_i[2] => addr_reg_s[2].DATAIN
|
| 241 |
|
|
addr_i[2] => ram.WADDR2
|
| 242 |
|
|
addr_i[3] => ram~5.DATAIN
|
| 243 |
|
|
addr_i[3] => addr_reg_s[3].DATAIN
|
| 244 |
|
|
addr_i[3] => ram.WADDR3
|
| 245 |
|
|
addr_i[4] => ram~4.DATAIN
|
| 246 |
|
|
addr_i[4] => addr_reg_s[4].DATAIN
|
| 247 |
|
|
addr_i[4] => ram.WADDR4
|
| 248 |
|
|
addr_i[5] => ram~3.DATAIN
|
| 249 |
|
|
addr_i[5] => addr_reg_s[5].DATAIN
|
| 250 |
|
|
addr_i[5] => ram.WADDR5
|
| 251 |
|
|
addr_i[6] => ram~2.DATAIN
|
| 252 |
|
|
addr_i[6] => addr_reg_s[6].DATAIN
|
| 253 |
|
|
addr_i[6] => ram.WADDR6
|
| 254 |
|
|
addr_i[7] => ram~1.DATAIN
|
| 255 |
|
|
addr_i[7] => addr_reg_s[7].DATAIN
|
| 256 |
|
|
addr_i[7] => ram.WADDR7
|
| 257 |
|
|
addr_i[8] => ram~0.DATAIN
|
| 258 |
|
|
addr_i[8] => addr_reg_s[8].DATAIN
|
| 259 |
|
|
addr_i[8] => ram.WADDR8
|
| 260 |
|
|
data_i[0] => ram~20.DATAIN
|
| 261 |
|
|
data_i[0] => ram.DATAIN
|
| 262 |
|
|
data_i[1] => ram~19.DATAIN
|
| 263 |
|
|
data_i[1] => ram.DATAIN1
|
| 264 |
|
|
data_i[2] => ram~18.DATAIN
|
| 265 |
|
|
data_i[2] => ram.DATAIN2
|
| 266 |
|
|
data_i[3] => ram~17.DATAIN
|
| 267 |
|
|
data_i[3] => ram.DATAIN3
|
| 268 |
|
|
data_i[4] => ram~16.DATAIN
|
| 269 |
|
|
data_i[4] => ram.DATAIN4
|
| 270 |
|
|
data_i[5] => ram~15.DATAIN
|
| 271 |
|
|
data_i[5] => ram.DATAIN5
|
| 272 |
|
|
data_i[6] => ram~14.DATAIN
|
| 273 |
|
|
data_i[6] => ram.DATAIN6
|
| 274 |
|
|
data_i[7] => ram~13.DATAIN
|
| 275 |
|
|
data_i[7] => ram.DATAIN7
|
| 276 |
|
|
data_i[8] => ram~12.DATAIN
|
| 277 |
|
|
data_i[8] => ram.DATAIN8
|
| 278 |
|
|
data_i[9] => ram~11.DATAIN
|
| 279 |
|
|
data_i[9] => ram.DATAIN9
|
| 280 |
|
|
data_i[10] => ram~10.DATAIN
|
| 281 |
|
|
data_i[10] => ram.DATAIN10
|
| 282 |
|
|
data_i[11] => ram~9.DATAIN
|
| 283 |
|
|
data_i[11] => ram.DATAIN11
|
| 284 |
|
|
we_i => ram~21.DATAIN
|
| 285 |
|
|
we_i => ram.WE
|
| 286 |
|
|
data_o[0] <= ram.DATAOUT
|
| 287 |
|
|
data_o[1] <= ram.DATAOUT1
|
| 288 |
|
|
data_o[2] <= ram.DATAOUT2
|
| 289 |
|
|
data_o[3] <= ram.DATAOUT3
|
| 290 |
|
|
data_o[4] <= ram.DATAOUT4
|
| 291 |
|
|
data_o[5] <= ram.DATAOUT5
|
| 292 |
|
|
data_o[6] <= ram.DATAOUT6
|
| 293 |
|
|
data_o[7] <= ram.DATAOUT7
|
| 294 |
|
|
data_o[8] <= ram.DATAOUT8
|
| 295 |
|
|
data_o[9] <= ram.DATAOUT9
|
| 296 |
|
|
data_o[10] <= ram.DATAOUT10
|
| 297 |
|
|
data_o[11] <= ram.DATAOUT11
|
| 298 |
|
|
|
| 299 |
|
|
|
