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[/] [usimplez/] [trunk/] [QuartusII/] [usimplez_top.map.summary] - Blame information for rev 3

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Line No. Rev Author Line
1 3 pas. 
Analysis & Synthesis Status : Successful - Wed Nov 09 11:45:57 2011
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Quartus II Version : 9.1 Build 350 03/24/2010 SP 2 SJ Web Edition
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Revision Name : usimplez_top
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Top-level Entity Name : usimplez_top
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Family : Stratix II
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Logic utilization : N/A
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    Combinational ALUTs : 48
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    Dedicated logic registers : 63
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Total registers : 63
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Total pins : 7
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Total virtual pins : 0
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Total block memory bits : 6,144
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DSP block 9-bit elements : 0
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Total PLLs : 0
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Total DLLs : 0

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