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--!
--! Copyright (C) 2011 - 2014 Creonic GmbH
--!
--! This file is part of the Creonic Viterbi Decoder, which is distributed
--! under the terms of the GNU General Public License version 2.
--!
--! @file
--! @brief  Component declarations for Viterbi decoder
--! @author Markus Fehrenz
--! @date   2011/04/07
--!
--!
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
 
library dec_viterbi;
use dec_viterbi.pkg_param.all;
use dec_viterbi.pkg_param_derived.all;
use dec_viterbi.pkg_types.all;
 
package pkg_components is
 
        component axi4s_buffer is
                generic (
                        DATA_WIDTH : natural := 1
                );
                port (
                clk            : in  std_logic;
                rst            : in  std_logic;
 
                input          : in  std_logic_vector(DATA_WIDTH - 1 downto 0);
                input_valid    : in  std_logic;
                input_last     : in  std_logic;
                input_accept   : out std_logic;
 
                output         : out std_logic_vector(DATA_WIDTH - 1 downto 0);
                output_valid   : out std_logic;
                output_last    : out std_logic;
                output_accept  : in  std_logic
                );
        end component axi4s_buffer;
 
        component branch_distance is
                generic(
                        EDGE_WEIGHT : in std_logic_vector(NUMBER_PARITY_BITS - 1 downto 0)
                );
                port(
                        clk : in std_logic;
                        rst : in std_logic;
 
                        s_axis_input_tvalid : in  std_logic;
                        s_axis_input_tdata  : in  t_input_block;
                        s_axis_input_tlast  : in  std_logic;
                        s_axis_input_tready : out std_logic;
 
                        m_axis_output_tvalid : out std_logic;
                        m_axis_output_tdata  : out std_logic_vector(BW_BRANCH_RESULT - 1 downto 0);
                        m_axis_output_tlast  : out std_logic;
                        m_axis_output_tready : in  std_logic
 
                );
        end component branch_distance;
 
        component acs is
                generic(
                        initialize_value : in signed(BW_MAX_PROBABILITY - 1 downto 0)
                );
                port(
                        clk                    : in std_logic;
                        rst                    : in std_logic;
 
                        s_axis_inbranch_tvalid     : in  std_logic;
                        s_axis_inbranch_tdata_low  : in  std_logic_vector(BW_BRANCH_RESULT - 1 downto 0);
                        s_axis_inbranch_tdata_high : in  std_logic_vector(BW_BRANCH_RESULT - 1 downto 0);
                        s_axis_inbranch_tlast      : in  std_logic;
                        s_axis_inbranch_tready     : out std_logic;
 
                        s_axis_inprev_tvalid     : in  std_logic;
                        s_axis_inprev_tdata_low  : in  std_logic_vector(BW_MAX_PROBABILITY - 1 downto 0);
                        s_axis_inprev_tdata_high : in  std_logic_vector(BW_MAX_PROBABILITY - 1 downto 0);
                        s_axis_inprev_tready     : out std_logic;
 
                        m_axis_outprob_tvalid  : out std_logic;
                        m_axis_outprob_tdata   : out std_logic_vector(BW_MAX_PROBABILITY - 1 downto 0);
                        m_axis_outprob_tready  : in  std_logic;
 
                        m_axis_outdec_tvalid   : out std_logic;
                        m_axis_outdec_tdata    : out std_logic;
                        m_axis_outdec_tlast    : out std_logic;
                        m_axis_outdec_tready   : in  std_logic
                );
        end component acs;
 
        component ram_ctrl is
                port(
                        clk       : in std_logic;
                        rst       : in std_logic;
 
                        s_axis_input_tvalid : in  std_logic;
                        s_axis_input_tdata  : in  std_logic_vector(NUMBER_TRELLIS_STATES - 1 downto 0);
                        s_axis_input_tlast  : in  std_logic;
                        s_axis_input_tready : out std_logic;
 
                        m_axis_output_tvalid       : out std_logic_vector(1 downto 0);
                        m_axis_output_tdata        : out t_ram_rd_data;
                        m_axis_output_tlast        : out std_logic_vector(1 downto 0);
                        m_axis_output_tready       : in  std_logic_vector(1 downto 0);
                        m_axis_output_window_tuser : out std_logic_vector(1 downto 0);
                        m_axis_output_last_tuser   : out std_logic_vector(1 downto 0);
 
                        s_axis_ctrl_tvalid : in  std_logic;
                        s_axis_ctrl_tdata  : in  std_logic_vector(31 downto 0);
                        s_axis_ctrl_tready : out std_logic
                );
        end component ram_ctrl;
 
        component generic_sp_ram is
                generic(
                        DISTR_RAM : boolean;
                        WORDS     : integer;
                        BITWIDTH  : integer
                );
                port(
                        clk : in std_logic;
                        rst : in std_logic;
 
                        wen : in std_logic;
                        en  : in std_logic;
 
                        a   : in std_logic_vector(BW_MAX_WINDOW_LENGTH - 1 downto 0);
                        d   : in  std_logic_vector(BITWIDTH - 1 downto 0 );
                        q   : out std_logic_vector(BITWIDTH - 1 downto 0)
                );
        end component generic_sp_ram;
 
        component trellis_traceback is
                port(
                        clk : in std_logic;
                        rst : in std_logic;
 
                        s_axis_input_tvalid       : in std_logic;
                        s_axis_input_tdata        : in std_logic_vector(NUMBER_TRELLIS_STATES - 1 downto 0);
                        s_axis_input_tlast        : in std_logic;
                        s_axis_input_tready       : out std_logic;
                        s_axis_input_window_tuser : in std_logic;
                        s_axis_input_last_tuser   : in std_logic;
 
                        m_axis_output_tvalid     : out std_logic;
                        m_axis_output_tdata      : out std_logic;
                        m_axis_output_tlast      : out std_logic;
                        m_axis_output_last_tuser : out std_logic;
                        m_axis_output_tready     : in  std_logic
                );
        end component trellis_traceback;
 
        component reorder is
                port(
                        clk : in std_logic;
                        rst : in std_logic;
 
                        s_axis_input_tvalid     : in  std_logic;
                        s_axis_input_tdata      : in  std_logic;
                        s_axis_input_tlast      : in  std_logic;
                        s_axis_input_last_tuser : in  std_logic;
                        s_axis_input_tready     : out std_logic;
 
                        m_axis_output_tvalid     : out std_logic;
                        m_axis_output_tdata      : out std_logic;
                        m_axis_output_tlast      : out std_logic;
                        m_axis_output_last_tuser : out std_logic;
                        m_axis_output_tready     : in  std_logic
                );
        end component reorder;
 
        component recursion is
                port(
                        clk : in std_logic;
                        rst : in std_logic;
 
                        s_axis_input_tvalid     : in  std_logic;
                        s_axis_input_tdata      : in  std_logic;
                        s_axis_input_tlast      : in  std_logic;
                        s_axis_input_tready     : out std_logic;
 
                        m_axis_output_tvalid     : out std_logic;
                        m_axis_output_tdata      : out std_logic;
                        m_axis_output_tlast      : out std_logic;
                        m_axis_output_tready     : in  std_logic
                );
        end component recursion;
 
end package pkg_components;

Line No.	Rev	Author	Line
1	2	mfehrenz	`--!`
2	6	mfehrenz	`--! Copyright (C) 2011 - 2014 Creonic GmbH`
3	2	mfehrenz	`--!`
4			`--! This file is part of the Creonic Viterbi Decoder, which is distributed`
5			`--! under the terms of the GNU General Public License version 2.`
6			`--!`
7			`--! @file`
8			`--! @brief Component declarations for Viterbi decoder`
9			`--! @author Markus Fehrenz`
10			`--! @date 2011/04/07`
11			`--!`
12			`--!`
13
14			`library ieee;`
15			`use ieee.std_logic_1164.all;`
16			`use ieee.numeric_std.all;`
17
18			`library dec_viterbi;`
19			`use dec_viterbi.pkg_param.all;`
20			`use dec_viterbi.pkg_param_derived.all;`
21			`use dec_viterbi.pkg_types.all;`
22
23			`package pkg_components is`
24
25	6	mfehrenz	`component axi4s_buffer is`
26			`generic (`
27			`DATA_WIDTH : natural := 1`
28			`);`
29			`port (`
30			`clk : in std_logic;`
31			`rst : in std_logic;`
32
33			`input : in std_logic_vector(DATA_WIDTH - 1 downto 0);`
34			`input_valid : in std_logic;`
35			`input_last : in std_logic;`
36			`input_accept : out std_logic;`
37
38			`output : out std_logic_vector(DATA_WIDTH - 1 downto 0);`
39			`output_valid : out std_logic;`
40			`output_last : out std_logic;`
41			`output_accept : in std_logic`
42			`);`
43			`end component axi4s_buffer;`
44
45	2	mfehrenz	`component branch_distance is`
46			`generic(`
47			`EDGE_WEIGHT : in std_logic_vector(NUMBER_PARITY_BITS - 1 downto 0)`
48			`);`
49			`port(`
50			`clk : in std_logic;`
51			`rst : in std_logic;`
52
53			`s_axis_input_tvalid : in std_logic;`
54			`s_axis_input_tdata : in t_input_block;`
55			`s_axis_input_tlast : in std_logic;`
56			`s_axis_input_tready : out std_logic;`
57
58			`m_axis_output_tvalid : out std_logic;`
59			`m_axis_output_tdata : out std_logic_vector(BW_BRANCH_RESULT - 1 downto 0);`
60			`m_axis_output_tlast : out std_logic;`
61			`m_axis_output_tready : in std_logic`
62
63			`);`
64			`end component branch_distance;`
65
66			`component acs is`
67			`generic(`
68			`initialize_value : in signed(BW_MAX_PROBABILITY - 1 downto 0)`
69			`);`
70			`port(`
71			`clk : in std_logic;`
72			`rst : in std_logic;`
73
74			`s_axis_inbranch_tvalid : in std_logic;`
75			`s_axis_inbranch_tdata_low : in std_logic_vector(BW_BRANCH_RESULT - 1 downto 0);`
76			`s_axis_inbranch_tdata_high : in std_logic_vector(BW_BRANCH_RESULT - 1 downto 0);`
77			`s_axis_inbranch_tlast : in std_logic;`
78			`s_axis_inbranch_tready : out std_logic;`
79
80			`s_axis_inprev_tvalid : in std_logic;`
81			`s_axis_inprev_tdata_low : in std_logic_vector(BW_MAX_PROBABILITY - 1 downto 0);`
82			`s_axis_inprev_tdata_high : in std_logic_vector(BW_MAX_PROBABILITY - 1 downto 0);`
83			`s_axis_inprev_tready : out std_logic;`
84
85			`m_axis_outprob_tvalid : out std_logic;`
86			`m_axis_outprob_tdata : out std_logic_vector(BW_MAX_PROBABILITY - 1 downto 0);`
87			`m_axis_outprob_tready : in std_logic;`
88
89			`m_axis_outdec_tvalid : out std_logic;`
90			`m_axis_outdec_tdata : out std_logic;`
91			`m_axis_outdec_tlast : out std_logic;`
92			`m_axis_outdec_tready : in std_logic`
93			`);`
94			`end component acs;`
95
96			`component ram_ctrl is`
97			`port(`
98			`clk : in std_logic;`
99			`rst : in std_logic;`
100
101			`s_axis_input_tvalid : in std_logic;`
102			`s_axis_input_tdata : in std_logic_vector(NUMBER_TRELLIS_STATES - 1 downto 0);`
103			`s_axis_input_tlast : in std_logic;`
104			`s_axis_input_tready : out std_logic;`
105
106			`m_axis_output_tvalid : out std_logic_vector(1 downto 0);`
107			`m_axis_output_tdata : out t_ram_rd_data;`
108			`m_axis_output_tlast : out std_logic_vector(1 downto 0);`
109			`m_axis_output_tready : in std_logic_vector(1 downto 0);`
110			`m_axis_output_window_tuser : out std_logic_vector(1 downto 0);`
111			`m_axis_output_last_tuser : out std_logic_vector(1 downto 0);`
112
113			`s_axis_ctrl_tvalid : in std_logic;`
114			`s_axis_ctrl_tdata : in std_logic_vector(31 downto 0);`
115			`s_axis_ctrl_tready : out std_logic`
116			`);`
117			`end component ram_ctrl;`
118
119			`component generic_sp_ram is`
120			`generic(`
121			`DISTR_RAM : boolean;`
122			`WORDS : integer;`
123			`BITWIDTH : integer`
124			`);`
125			`port(`
126			`clk : in std_logic;`
127			`rst : in std_logic;`
128
129			`wen : in std_logic;`
130			`en : in std_logic;`
131
132			`a : in std_logic_vector(BW_MAX_WINDOW_LENGTH - 1 downto 0);`
133			`d : in std_logic_vector(BITWIDTH - 1 downto 0 );`
134			`q : out std_logic_vector(BITWIDTH - 1 downto 0)`
135			`);`
136			`end component generic_sp_ram;`
137
138			`component trellis_traceback is`
139			`port(`
140			`clk : in std_logic;`
141			`rst : in std_logic;`
142
143			`s_axis_input_tvalid : in std_logic;`
144			`s_axis_input_tdata : in std_logic_vector(NUMBER_TRELLIS_STATES - 1 downto 0);`
145			`s_axis_input_tlast : in std_logic;`
146			`s_axis_input_tready : out std_logic;`
147			`s_axis_input_window_tuser : in std_logic;`
148			`s_axis_input_last_tuser : in std_logic;`
149
150			`m_axis_output_tvalid : out std_logic;`
151			`m_axis_output_tdata : out std_logic;`
152			`m_axis_output_tlast : out std_logic;`
153			`m_axis_output_last_tuser : out std_logic;`
154			`m_axis_output_tready : in std_logic`
155			`);`
156			`end component trellis_traceback;`
157
158			`component reorder is`
159			`port(`
160			`clk : in std_logic;`
161			`rst : in std_logic;`
162
163			`s_axis_input_tvalid : in std_logic;`
164			`s_axis_input_tdata : in std_logic;`
165			`s_axis_input_tlast : in std_logic;`
166			`s_axis_input_last_tuser : in std_logic;`
167			`s_axis_input_tready : out std_logic;`
168
169			`m_axis_output_tvalid : out std_logic;`
170			`m_axis_output_tdata : out std_logic;`
171			`m_axis_output_tlast : out std_logic;`
172			`m_axis_output_last_tuser : out std_logic;`
173			`m_axis_output_tready : in std_logic`
174			`);`
175			`end component reorder;`
176
177			`component recursion is`
178			`port(`
179			`clk : in std_logic;`
180			`rst : in std_logic;`
181
182			`s_axis_input_tvalid : in std_logic;`
183			`s_axis_input_tdata : in std_logic;`
184			`s_axis_input_tlast : in std_logic;`
185			`s_axis_input_tready : out std_logic;`
186
187			`m_axis_output_tvalid : out std_logic;`
188			`m_axis_output_tdata : out std_logic;`
189			`m_axis_output_tlast : out std_logic;`
190			`m_axis_output_tready : in std_logic`
191			`);`
192			`end component recursion;`
193
194			`end package pkg_components;`

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[/] [viterbi_decoder_axi4s/] [trunk/] [packages/] [pkg_components.vhd] - Blame information for rev 6