OpenCores
URL https://opencores.org/ocsvn/w11/w11/trunk

Subversion Repositories w11

[/] [w11/] [tags/] [w11a_V0.6/] [Makefile] - Blame information for rev 24

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 22 wfjm
# $Id: Makefile 538 2013-10-06 17:21:25Z mueller $
2 16 wfjm
#
3
# 'Meta Makefile' for whole retro project
4
#   allows to make all synthesis targets
5
#   allows to make all test bench targets
6
#
7
#  Revision History:
8
# Date         Rev Version  Comment
9 22 wfjm
# 2013-09-28   535   1.0.7  add nexys4 port for sys_gen/tst_sram,w11a
10 21 wfjm
# 2013-05-01   513   1.0.6  add clean_sim_tmp and clean_syn_tmp targets
11 17 wfjm
# 2012-12-29   466   1.0.5  add tst_rlink_cuff
12
# 2011-12-26   445   1.0.4  add tst_fx2loop
13
# 2011-12-23   444   1.0.3  enforce -j 1 in sub-makes
14 16 wfjm
# 2011-11-27   433   1.0.2  add new nexys3 ports
15
# 2011-11-18   426   1.0.1  add tst_serport and tst_snhumanio
16
# 2011-07-09   391   1.0    Initial version
17
#
18 17 wfjm
SYN_all += rtl/sys_gen/tst_fx2loop/nexys2/ic
19
SYN_all += rtl/sys_gen/tst_fx2loop/nexys2/ic3
20 21 wfjm
SYN_all += rtl/sys_gen/tst_fx2loop/nexys3/ic
21
SYN_all += rtl/sys_gen/tst_fx2loop/nexys3/ic3
22 16 wfjm
SYN_all += rtl/sys_gen/tst_rlink/nexys2
23
SYN_all += rtl/sys_gen/tst_rlink/nexys3
24
SYN_all += rtl/sys_gen/tst_rlink/s3board
25 17 wfjm
SYN_all += rtl/sys_gen/tst_rlink_cuff/nexys2/ic
26 18 wfjm
SYN_all += rtl/sys_gen/tst_rlink_cuff/nexys2/ic3
27
SYN_all += rtl/sys_gen/tst_rlink_cuff/nexys3/ic
28
SYN_all += rtl/sys_gen/tst_rlink_cuff/atlys/ic
29 16 wfjm
SYN_all += rtl/sys_gen/tst_serloop/nexys2
30
SYN_all += rtl/sys_gen/tst_serloop/nexys3
31
SYN_all += rtl/sys_gen/tst_serloop/s3board
32
SYN_all += rtl/sys_gen/tst_snhumanio/atlys
33
SYN_all += rtl/sys_gen/tst_snhumanio/nexys2
34
SYN_all += rtl/sys_gen/tst_snhumanio/nexys3
35
SYN_all += rtl/sys_gen/tst_snhumanio/s3board
36
SYN_all += rtl/sys_gen/w11a/nexys2
37
SYN_all += rtl/sys_gen/w11a/nexys3
38
SYN_all += rtl/sys_gen/w11a/s3board
39
 
40
SIM_all += rtl/bplib/nxcramlib/tb
41
SIM_all += rtl/sys_gen/tst_rlink/nexys2/tb
42
SIM_all += rtl/sys_gen/tst_rlink/nexys3/tb
43
SIM_all += rtl/sys_gen/tst_rlink/s3board/tb
44 18 wfjm
SIM_all += rtl/sys_gen/tst_rlink_cuff/nexys2/ic/tb
45 21 wfjm
SIM_all += rtl/sys_gen/tst_rlink_cuff/nexys3/ic/tb
46 16 wfjm
SIM_all += rtl/sys_gen/tst_serloop/nexys2/tb
47
SIM_all += rtl/sys_gen/tst_serloop/nexys3/tb
48
SIM_all += rtl/sys_gen/tst_serloop/s3board/tb
49
SIM_all += rtl/sys_gen/w11a/nexys2/tb
50
SIM_all += rtl/sys_gen/w11a/nexys3/tb
51
SIM_all += rtl/sys_gen/w11a/s3board/tb
52
SIM_all += rtl/vlib/rlink/tb
53
SIM_all += rtl/vlib/serport/tb
54
SIM_all += rtl/w11a/tb
55
#
56 21 wfjm
.PHONY : all all_sim all_syn
57
.PHONY : clean clean_sim clean_sim_tmp clean_sym clean_sym_tmp
58 16 wfjm
.PHONY : $(SYN_all) $(SIM_all)
59
#
60
all :
61 19 wfjm
        @echo "no default action defined."
62
        @echo "  for VHDL simulation/synthesis use:"
63
        @echo "    make -j 4 all_sim"
64
        @echo "    make -j 4 all_syn"
65
        @echo "    make clean"
66
        @echo "    make clean_sim"
67
        @echo "    make clean_syn"
68 21 wfjm
        @echo "    make clean_sim_tmp"
69
        @echo "    make clean_syn_tmp"
70 19 wfjm
        @echo "  for tool/documentation generation use:"
71
        @echo "    make -j 4 all_lib"
72
        @echo "    make clean_lib"
73
        @echo "    make all_tcl"
74
        @echo "    make all_dox"
75 16 wfjm
#
76
#
77
clean : clean_sim clean_syn
78
#
79
clean_sim :
80
        for dir in $(SIM_all); do $(MAKE) -C $$dir clean; done
81
clean_syn :
82
        for dir in $(SYN_all); do $(MAKE) -C $$dir clean; done
83
#
84 21 wfjm
clean_sim_tmp :
85
        for dir in $(SIM_all); do $(MAKE) -C $$dir ghdl_tmp_clean; done
86
clean_syn_tmp :
87
        for dir in $(SYN_all); do $(MAKE) -C $$dir ise_tmp_clean; done
88
#
89 16 wfjm
all_sim : $(SIM_all)
90 17 wfjm
#
91 16 wfjm
all_syn : $(SYN_all)
92 17 wfjm
        @if [ -n "`find -name "*_par.log" | xargs grep -L 'All constraints were met'`" ] ; then \
93
          echo "++++++++++ some designs have no timing closure: ++++++++++"; \
94
          find -name "*_par.log" | xargs grep -L 'All constraints were met'; \
95
          echo "++++++++++ ++++++++++++++++++++++++++++++++++++ ++++++++++"; \
96
        fi
97 16 wfjm
#
98 17 wfjm
# Neither ghdl nor xst allow multiple parallel compiles in one directory.
99
# The following ensures that the sub-makes are called with -j 1 and will
100
# not try to run multiple compiles on one directory.
101
#
102 16 wfjm
$(SIM_all):
103 17 wfjm
        $(MAKE) -j 1 -C $@
104 16 wfjm
$(SYN_all):
105 17 wfjm
        $(MAKE) -j 1 -C $@
106 16 wfjm
#
107 19 wfjm
all_lib :
108
        $(MAKE) -C tools/src
109
clean_lib :
110
        $(MAKE) -C tools/src distclean
111
#
112
all_tcl :
113
        (cd tools/tcl; setup_packages)
114
#
115
all_dox :
116
        (cd tools/dox; make_doxy)
117
#
118
all_all : all_sim all_syn all_lib all_tcl

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.