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[/] [warp/] [rtl/] [tmu_pixout.v] - Blame information for rev 7

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1 7 lekernel 
/*
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 * Milkymist VJ SoC
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 * Copyright (C) 2007, 2008, 2009 Sebastien Bourdeauducq
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 *
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 * This program is free and excepted software; you can use it, redistribute it
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 * and/or modify it under the terms of the Exception General Public License as
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 * published by the Exception License Foundation; either version 2 of the
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 * License, or (at your option) any later version.
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 *
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 * This program is distributed in the hope that it will be useful, but WITHOUT
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 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
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 * FOR A PARTICULAR PURPOSE. See the Exception General Public License for more
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 * details.
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 *
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 * You should have received a copy of the Exception General Public License along
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 * with this project; if not, write to the Exception License Foundation.
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 */
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module tmu_pixout #(
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        parameter fml_depth = 26
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) (
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        input sys_clk,
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        input sys_rst,
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        output reg busy,
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        input pipe_stb_i,
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        output reg pipe_ack_o,
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        input [fml_depth-5-1:0] burst_addr,
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        input [15:0] burst_sel,
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        input [255:0] burst_do,
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        output reg [fml_depth-1:0] fml_adr,
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        output reg fml_stb,
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        input fml_ack,
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        output reg [7:0] fml_sel,
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        output reg [63:0] fml_do
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);
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reg [15:0] burst_sel_r;
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reg [255:0] burst_do_r;
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reg load;
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always @(posedge sys_clk) begin
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        if(load) begin
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                fml_adr = {burst_addr, 5'd0};
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                burst_sel_r = burst_sel;
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                burst_do_r = burst_do;
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        end
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end
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reg [1:0] bcounter;
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always @(posedge sys_clk) begin
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        case(bcounter)
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                2'd0: begin
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                        fml_sel <= {
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                                burst_sel_r[15], burst_sel_r[15],
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                                burst_sel_r[14], burst_sel_r[14],
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                                burst_sel_r[13], burst_sel_r[13],
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                                burst_sel_r[12], burst_sel_r[12]
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                                };
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                        fml_do <= burst_do_r[255:192];
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                end
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                2'd1: begin
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                        fml_sel <= {
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                                burst_sel_r[11], burst_sel_r[11],
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                                burst_sel_r[10], burst_sel_r[10],
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                                burst_sel_r[ 9], burst_sel_r[ 9],
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                                burst_sel_r[ 8], burst_sel_r[ 8]
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                                };
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                        fml_do <= burst_do_r[191:128];
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                end
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                2'd2: begin
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                        fml_sel <= {
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                                burst_sel_r[ 7], burst_sel_r[ 7],
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                                burst_sel_r[ 6], burst_sel_r[ 6],
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                                burst_sel_r[ 5], burst_sel_r[ 5],
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                                burst_sel_r[ 4], burst_sel_r[ 4]
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                                };
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                        fml_do <= burst_do_r[127: 64];
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                end
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                2'd3: begin
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                        fml_sel <= {
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                                burst_sel_r[ 3], burst_sel_r[ 3],
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                                burst_sel_r[ 2], burst_sel_r[ 2],
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                                burst_sel_r[ 1], burst_sel_r[ 1],
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                                burst_sel_r[ 0], burst_sel_r[ 0]
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                                };
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                        fml_do <= burst_do_r[ 63:  0];
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                end
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        endcase
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end
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reg [1:0] state;
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reg [1:0] next_state;
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parameter IDLE  = 2'd0;
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parameter WAIT  = 2'd1;
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parameter XFER2 = 2'd2;
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parameter XFER3 = 2'd3;
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always @(posedge sys_clk) begin
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        if(sys_rst)
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                state <= IDLE;
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        else
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                state <= next_state;
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end
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always @(*) begin
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        next_state = state;
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        busy = 1'b1;
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        pipe_ack_o = 1'b0;
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        fml_stb = 1'b0;
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        load = 1'b0;
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        bcounter = 2'bxx;
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        case(state)
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                IDLE: begin
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                        busy = 1'b0;
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                        pipe_ack_o = 1'b1;
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                        bcounter = 2'd0;
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                        if(pipe_stb_i) begin
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                                load = 1'b1;
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                                next_state = WAIT;
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                        end
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                end
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                WAIT: begin
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                        fml_stb = 1'b1;
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                        bcounter = 2'd0;
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                        if(fml_ack) begin
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                                bcounter = 2'd1;
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                                next_state = XFER2;
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                        end
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                end
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                XFER2: begin
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                        bcounter = 2'd2;
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                        next_state = XFER3;
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                end
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                XFER3: begin
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                        bcounter = 2'd3;
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                        next_state = IDLE;
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                end
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        endcase
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end
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endmodule

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