OpenCores
URL https://opencores.org/ocsvn/warp/warp/trunk

Subversion Repositories warp

[/] [warp/] [rtl/] [tmu_reorder.v] - Blame information for rev 7

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 7 lekernel 
/*
2 
 * Milkymist VJ SoC
3 
 * Copyright (C) 2007, 2008, 2009 Sebastien Bourdeauducq
4 
 *
5 
 * This program is free and excepted software; you can use it, redistribute it
6 
 * and/or modify it under the terms of the Exception General Public License as
7 
 * published by the Exception License Foundation; either version 2 of the
8 
 * License, or (at your option) any later version.
9 
 *
10 
 * This program is distributed in the hope that it will be useful, but WITHOUT
11 
 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
12 
 * FOR A PARTICULAR PURPOSE. See the Exception General Public License for more
13 
 * details.
14 
 *
15 
 * You should have received a copy of the Exception General Public License along
16 
 * with this project; if not, write to the Exception License Foundation.
17 
 */
18 
 
19 
module tmu_reorder(
20 
        input sys_clk,
21 
        input sys_rst,
22 
 
23 
        output busy,
24 
 
25 
        input pipe_stb_i,
26 
        output pipe_ack_o,
27 
        input [10:0] A0_S_X,
28 
        input [10:0] A0_S_Y,
29 
        input [10:0] B0_S_X,
30 
        input [10:0] B0_S_Y,
31 
        input [10:0] C0_S_X,
32 
        input [10:0] C0_S_Y,
33 
        input [10:0] A0_D_X,
34 
        input [10:0] A0_D_Y,
35 
        input [10:0] B0_D_X,
36 
        input [10:0] B0_D_Y,
37 
        input [10:0] C0_D_X,
38 
        input [10:0] C0_D_Y,
39 
 
40 
        output pipe_stb_o,
41 
        input pipe_ack_i,
42 
        output reg [10:0] A_S_X,
43 
        output reg [10:0] A_S_Y,
44 
        output reg [10:0] B_S_X,
45 
        output reg [10:0] B_S_Y,
46 
        output reg [10:0] C_S_X,
47 
        output reg [10:0] C_S_Y,
48 
        output reg [10:0] A_D_X,
49 
        output reg [10:0] A_D_Y,
50 
        output reg [10:0] B_D_X,
51 
        output reg [10:0] B_D_Y,
52 
        output reg [10:0] C_D_X,
53 
        output reg [10:0] C_D_Y
54 
);
55 
 
56 
/*
57 
 * See http://www.geocities.com/wronski12/3d_tutor/tri_fillers.html
58 
 * The purpose of this module is to reorder the destination triangle
59 
 * points so that A_Y <= B_Y <= C_Y
60 
 */
61 
 
62 
wire en;
63 
 
64 
/* Stage 1: Compare Y coordinates */
65 
wire s0_valid;
66 
reg s1_valid;
67 
reg s1_A_over_B;
68 
reg s1_A_over_C;
69 
reg s1_B_over_A;
70 
reg s1_B_over_C;
71 
reg s1_C_over_A;
72 
reg s1_C_over_B;
73 
reg [10:0] s1_A_S_X;
74 
reg [10:0] s1_A_S_Y;
75 
reg [10:0] s1_B_S_X;
76 
reg [10:0] s1_B_S_Y;
77 
reg [10:0] s1_C_S_X;
78 
reg [10:0] s1_C_S_Y;
79 
reg [10:0] s1_A_D_X;
80 
reg [10:0] s1_A_D_Y;
81 
reg [10:0] s1_B_D_X;
82 
reg [10:0] s1_B_D_Y;
83 
reg [10:0] s1_C_D_X;
84 
reg [10:0] s1_C_D_Y;
85 
 
86 
always @(posedge sys_clk) begin
87 
        if(sys_rst)
88 
                s1_valid <= 1'b0;
89 
        else if(en)
90 
                s1_valid <= s0_valid;
91 
end
92 
 
93 
always @(posedge sys_clk) begin
94 
        if(en) begin
95 
                s1_A_over_B <= (A0_D_Y <= B0_D_Y);
96 
                s1_A_over_C <= (A0_D_Y <= C0_D_Y);
97 
                s1_B_over_A <= (B0_D_Y <= A0_D_Y);
98 
                s1_B_over_C <= (B0_D_Y <= C0_D_Y);
99 
                s1_C_over_A <= (C0_D_Y <= A0_D_Y);
100 
                s1_C_over_B <= (C0_D_Y <= B0_D_Y);
101 
 
102 
                s1_A_S_X <= A0_S_X;
103 
                s1_A_S_Y <= A0_S_Y;
104 
                s1_B_S_X <= B0_S_X;
105 
                s1_B_S_Y <= B0_S_Y;
106 
                s1_C_S_X <= C0_S_X;
107 
                s1_C_S_Y <= C0_S_Y;
108 
                s1_A_D_X <= A0_D_X;
109 
                s1_A_D_Y <= A0_D_Y;
110 
                s1_B_D_X <= B0_D_X;
111 
                s1_B_D_Y <= B0_D_Y;
112 
                s1_C_D_X <= C0_D_X;
113 
                s1_C_D_Y <= C0_D_Y;
114 
        end
115 
end
116 
 
117 
/* Stage 2: Make the point order choice and mux accordingly. */
118 
reg s2_valid;
119 
 
120 
always @(posedge sys_clk) begin
121 
        if(sys_rst)
122 
                s2_valid <= 1'b0;
123 
        else if(en)
124 
                s2_valid <= s1_valid;
125 
end
126 
 
127 
always @(posedge sys_clk) begin
128 
        if(en) begin
129 
                if(s1_A_over_B & s1_A_over_C) begin
130 
                        A_S_X <= s1_A_S_X;
131 
                        A_S_Y <= s1_A_S_Y;
132 
                        A_D_X <= s1_A_D_X;
133 
                        A_D_Y <= s1_A_D_Y;
134 
 
135 
                        if(s1_B_over_C) begin
136 
                                B_S_X <= s1_B_S_X;
137 
                                B_S_Y <= s1_B_S_Y;
138 
                                B_D_X <= s1_B_D_X;
139 
                                B_D_Y <= s1_B_D_Y;
140 
 
141 
                                C_S_X <= s1_C_S_X;
142 
                                C_S_Y <= s1_C_S_Y;
143 
                                C_D_X <= s1_C_D_X;
144 
                                C_D_Y <= s1_C_D_Y;
145 
                        end else begin
146 
                                B_S_X <= s1_C_S_X;
147 
                                B_S_Y <= s1_C_S_Y;
148 
                                B_D_X <= s1_C_D_X;
149 
                                B_D_Y <= s1_C_D_Y;
150 
 
151 
                                C_S_X <= s1_B_S_X;
152 
                                C_S_Y <= s1_B_S_Y;
153 
                                C_D_X <= s1_B_D_X;
154 
                                C_D_Y <= s1_B_D_Y;
155 
                        end
156 
                end else if(s1_B_over_A & s1_B_over_C) begin
157 
                        A_S_X <= s1_B_S_X;
158 
                        A_S_Y <= s1_B_S_Y;
159 
                        A_D_X <= s1_B_D_X;
160 
                        A_D_Y <= s1_B_D_Y;
161 
 
162 
                        if(s1_A_over_C) begin
163 
                                B_S_X <= s1_A_S_X;
164 
                                B_S_Y <= s1_A_S_Y;
165 
                                B_D_X <= s1_A_D_X;
166 
                                B_D_Y <= s1_A_D_Y;
167 
 
168 
                                C_S_X <= s1_C_S_X;
169 
                                C_S_Y <= s1_C_S_Y;
170 
                                C_D_X <= s1_C_D_X;
171 
                                C_D_Y <= s1_C_D_Y;
172 
                        end else begin
173 
                                B_S_X <= s1_C_S_X;
174 
                                B_S_Y <= s1_C_S_Y;
175 
                                B_D_X <= s1_C_D_X;
176 
                                B_D_Y <= s1_C_D_Y;
177 
 
178 
                                C_S_X <= s1_A_S_X;
179 
                                C_S_Y <= s1_A_S_Y;
180 
                                C_D_X <= s1_A_D_X;
181 
                                C_D_Y <= s1_A_D_Y;
182 
                        end
183 
                end else begin /* s1_C_over_A & s1_C_over_B */
184 
                        A_S_X <= s1_C_S_X;
185 
                        A_S_Y <= s1_C_S_Y;
186 
                        A_D_X <= s1_C_D_X;
187 
                        A_D_Y <= s1_C_D_Y;
188 
 
189 
                        if(s1_A_over_B) begin
190 
                                B_S_X <= s1_A_S_X;
191 
                                B_S_Y <= s1_A_S_Y;
192 
                                B_D_X <= s1_A_D_X;
193 
                                B_D_Y <= s1_A_D_Y;
194 
 
195 
                                C_S_X <= s1_B_S_X;
196 
                                C_S_Y <= s1_B_S_Y;
197 
                                C_D_X <= s1_B_D_X;
198 
                                C_D_Y <= s1_B_D_Y;
199 
                        end else begin
200 
                                B_S_X <= s1_B_S_X;
201 
                                B_S_Y <= s1_B_S_Y;
202 
                                B_D_X <= s1_B_D_X;
203 
                                B_D_Y <= s1_B_D_Y;
204 
 
205 
                                C_S_X <= s1_A_S_X;
206 
                                C_S_Y <= s1_A_S_Y;
207 
                                C_D_X <= s1_A_D_X;
208 
                                C_D_Y <= s1_A_D_Y;
209 
                        end
210 
                end
211 
        end
212 
end
213 
 
214 
/* Pipeline management */
215 
 
216 
assign busy = s1_valid|s2_valid;
217 
 
218 
assign s0_valid = pipe_stb_i;
219 
assign pipe_ack_o = pipe_ack_i;
220 
 
221 
assign en = pipe_ack_i;
222 
assign pipe_stb_o = s2_valid;
223 
 
224 
endmodule

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.