URL https://opencores.org/ocsvn/wb_lcd/wb_lcd/trunk

Subversion Repositories wb_lcd

[/] [wb_lcd/] [trunk/] [myhdl/] [wb_lcd_workspace/] [boards/] [s3esk-mm_lcd/] [synthesis/] [Makefile] - Blame information for rev 2

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#############################################################################
# Master path definitions
 
TOPDIR?=$(shell pwd)
TOOLS_DIR=$(TOPDIR)/../../../tools
CORE_DIR=$(TOPDIR)/../../../rtl
BOARD_DIR=$(TOPDIR)/../rtl
#CHIPSCOPE_DIR=$(TOPDIR)/../chipscope
 
#############################################################################
# Board and core source files for synthesis and simulation
 
BOARD_SYN=$(wildcard $(BOARD_DIR)/*.v)
BOARD_SIM=$(wildcard $(BOARD_DIR)/*.v)
 
CORE_SRCS=$(wildcard $(CORE_DIR)/*.v)
#CHIPSCOPE_SRCS=$(wildcard $(CHIPSCOPE_DIR)/*.v)
 
SYN_SRC=                \
        $(BOARD_SYN)    \
        $(CORE_SRCS)
 
#SYN_SRC=               \
#       $(BOARD_SYN)    \
#       $(CORE_SRCS)    \
#       $(CHIPSCOPE_SRCS)
 
SIM_SRC=                \
        $(BOARD_SYN)    \
        $(CORE_SRCS)
 
VINCDIR=                \
        -I$(CORE_DIR)   \
        -I$(BOARD_DIR)
 
 
#############################################################################
# Syntheis constants
SYNCLEAN=system.bgn system.drc system.mrp system.ngd system.pcf
SYNCLEAN+=system.bld system.lso system.ncd system.ngm system.srp
SYNCLEAN+=system.bit system_signalbrowser.* system-routed_pad.tx system.bin
SYNCLEAN+=system.map system_summary.xml timing.twr
SYNCLEAN+=system-routed* system_usage* system.ngc param.opt netlist.lst
SYNCLEAN+=xst system.prj system.prm
# for ISE 10.1
SYNCLEAN+=xlnx_auto_0.ise system_par.xrpt smartpreview.twr system.ngc_xst.xrpt
SYNCLEAN+=system_ngdbuild.xrpt system_map.xrpt xlnx_auto_0_xdb _impactbatch.log
 
USAGE_DEPTH=5
SMARTGUIDE=
#############################################################################
# Simulation constants
SIMCLEAN=system_sim.vvp system_sim.vcd verilog.log system_sim.vvp.list
 
CVER=cver
GTKWAVE=gtkwave
IVERILOG=iverilog
VVP=vvp
 
#############################################################################
#
all: system.bit system.bin
sim: system_sim.vcd
syn: system.bit
view: system_sim.view
 
#############################################################################
# Icarus verilog simulation
 
system_sim.vvp: $(SIM_SRC)
        rm -f $@.list
        @for i in `echo $^`; do \
            echo $$i >> $@.list; \
        done
        $(IVERILOG) -o $@ $(VINCDIR) -c $@.list -s $(@:.vvp=) -s glbl
 
%.vcd: %.vvp
        $(VVP) $<
 
#############################################################################
# ISE Synthesis
 
system.prj: $(SYN_SRC)
        rm -f system.prj
        @for i in `echo $^`; do \
            echo "verilog work $$i" >> system.prj; \
        done
 
system.ngc: system.prj
        xst -ifn system.xst
 
system.ngd: system.ngc system.ucf
        ngdbuild -uc system.ucf system.ngc
#       ngdbuild -uc system.ucf -sd $(CHIPSCOPE_DIR) system.ngc
 
system.ncd: system.ngd
        map $(SMARTGUIDE) system.ngd
 
system-routed.ncd: system.ncd
        par $(SMARTGUIDE) -ol high -w system.ncd system-routed.ncd
 
system.bit: system-routed.ncd
        bitgen -w system-routed.ncd system.bit
 
system.bin: system.bit
        promgen -u 0x0 system.bit -p bin -w
 
system.mcs: system.bit
        promgen -u 0 system
 
system-routed.xdl: system-routed.ncd
        xdl -ncd2xdl system-routed.ncd system-routed.xdl
 
system-routed.twr: system-routed.ncd
        trce -v 10 system-routed.ncd system.pcf
 
timing: system-routed.twr
 
usage: system-routed.xdl
        $(TOOLS_DIR)/xdlanalyze/xdlanalyze.pl system-routed.xdl $(USAGE_DEPTH)
 
####################################################################
# final targets
 
load: system.bit
        impact -batch impact.batch
 
#analyze: load
#       analyzer.sh
 
%.view: %.vcd
        $(GTKWAVE) $< $<.save
 
clean:
        rm -Rf $(SYNCLEAN) $(SIMCLEAN)
 
.PHONY: clean view
 

Line No.	Rev	Author	Line
1	2	jvillar	`#############################################################################`
2			`# Master path definitions`
3
4			`TOPDIR?=$(shell pwd)`
5			`TOOLS_DIR=$(TOPDIR)/../../../tools`
6			`CORE_DIR=$(TOPDIR)/../../../rtl`
7			`BOARD_DIR=$(TOPDIR)/../rtl`
8			`#CHIPSCOPE_DIR=$(TOPDIR)/../chipscope`
9
10			`#############################################################################`
11			`# Board and core source files for synthesis and simulation`
12
13			`BOARD_SYN=$(wildcard $(BOARD_DIR)/*.v)`
14			`BOARD_SIM=$(wildcard $(BOARD_DIR)/*.v)`
15
16			`CORE_SRCS=$(wildcard $(CORE_DIR)/*.v)`
17			`#CHIPSCOPE_SRCS=$(wildcard $(CHIPSCOPE_DIR)/*.v)`
18
19			`SYN_SRC= \`
20			`$(BOARD_SYN) \`
21			`$(CORE_SRCS)`
22
23			`#SYN_SRC= \`
24			`# $(BOARD_SYN) \`
25			`# $(CORE_SRCS) \`
26			`# $(CHIPSCOPE_SRCS)`
27
28			`SIM_SRC= \`
29			`$(BOARD_SYN) \`
30			`$(CORE_SRCS)`
31
32			`VINCDIR= \`
33			`-I$(CORE_DIR) \`
34			`-I$(BOARD_DIR)`
35
36
37			`#############################################################################`
38			`# Syntheis constants`
39			`SYNCLEAN=system.bgn system.drc system.mrp system.ngd system.pcf`
40			`SYNCLEAN+=system.bld system.lso system.ncd system.ngm system.srp`
41			`SYNCLEAN+=system.bit system_signalbrowser.* system-routed_pad.tx system.bin`
42			`SYNCLEAN+=system.map system_summary.xml timing.twr`
43			`SYNCLEAN+=system-routed* system_usage* system.ngc param.opt netlist.lst`
44			`SYNCLEAN+=xst system.prj system.prm`
45			`# for ISE 10.1`
46			`SYNCLEAN+=xlnx_auto_0.ise system_par.xrpt smartpreview.twr system.ngc_xst.xrpt`
47			`SYNCLEAN+=system_ngdbuild.xrpt system_map.xrpt xlnx_auto_0_xdb _impactbatch.log`
48
49			`USAGE_DEPTH=5`
50			`SMARTGUIDE=`
51			`#############################################################################`
52			`# Simulation constants`
53			`SIMCLEAN=system_sim.vvp system_sim.vcd verilog.log system_sim.vvp.list`
54
55			`CVER=cver`
56			`GTKWAVE=gtkwave`
57			`IVERILOG=iverilog`
58			`VVP=vvp`
59
60			`#############################################################################`
61			`#`
62			`all: system.bit system.bin`
63			`sim: system_sim.vcd`
64			`syn: system.bit`
65			`view: system_sim.view`
66
67			`#############################################################################`
68			`# Icarus verilog simulation`
69
70			`system_sim.vvp: $(SIM_SRC)`
71			`rm -f $@.list`
72			@for i in `echo $^`; do \
73			`echo $$i >> $@.list; \`
74			`done`
75			`$(IVERILOG) -o $@ $(VINCDIR) -c $@.list -s $(@:.vvp=) -s glbl`
76
77			`%.vcd: %.vvp`
78			`$(VVP) $<`
79
80			`#############################################################################`
81			`# ISE Synthesis`
82
83			`system.prj: $(SYN_SRC)`
84			`rm -f system.prj`
85			@for i in `echo $^`; do \
86			`echo "verilog work $$i" >> system.prj; \`
87			`done`
88
89			`system.ngc: system.prj`
90			`xst -ifn system.xst`
91
92			`system.ngd: system.ngc system.ucf`
93			`ngdbuild -uc system.ucf system.ngc`
94			`# ngdbuild -uc system.ucf -sd $(CHIPSCOPE_DIR) system.ngc`
95
96			`system.ncd: system.ngd`
97			`map $(SMARTGUIDE) system.ngd`
98
99			`system-routed.ncd: system.ncd`
100			`par $(SMARTGUIDE) -ol high -w system.ncd system-routed.ncd`
101
102			`system.bit: system-routed.ncd`
103			`bitgen -w system-routed.ncd system.bit`
104
105			`system.bin: system.bit`
106			`promgen -u 0x0 system.bit -p bin -w`
107
108			`system.mcs: system.bit`
109			`promgen -u 0 system`
110
111			`system-routed.xdl: system-routed.ncd`
112			`xdl -ncd2xdl system-routed.ncd system-routed.xdl`
113
114			`system-routed.twr: system-routed.ncd`
115			`trce -v 10 system-routed.ncd system.pcf`
116
117			`timing: system-routed.twr`
118
119			`usage: system-routed.xdl`
120			`$(TOOLS_DIR)/xdlanalyze/xdlanalyze.pl system-routed.xdl $(USAGE_DEPTH)`
121
122			`####################################################################`
123			`# final targets`
124
125			`load: system.bit`
126			`impact -batch impact.batch`
127
128			`#analyze: load`
129			`# analyzer.sh`
130
131			`%.view: %.vcd`
132			`$(GTKWAVE) $< $<.save`
133
134			`clean:`
135			`rm -Rf $(SYNCLEAN) $(SIMCLEAN)`
136
137			`.PHONY: clean view`
138

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Subversion Repositories wb_lcd

[/] [wb_lcd/] [trunk/] [myhdl/] [wb_lcd_workspace/] [boards/] [s3esk-mm_lcd/] [synthesis/] [Makefile] - Blame information for rev 2