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[/] [wb_lcd/] [trunk/] [myhdl/] [wb_lcd_workspace/] [boards/] [s3esk-wb_lcd/] [rtl/] [system.v] - Blame information for rev 2

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1 2 jvillar
//////////////////////////////////////////////////////////////////////
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////                                                              ////
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////  system.v                                                    ////
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////                                                              ////
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////  This file is part of:                                       ////
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////  WISHBONE/MEM MAPPED CONTROLLER FOR LCD CHARACTER DISPLAYS   ////
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////  http://www.opencores.org/projects/wb_lcd/                   ////
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////                                                              ////
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////  Description                                                 ////
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////   - Wishbone controller testbench implementation for         ////
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////     Spartan 3E Starter Kit (XC3S500E) board from Digilent.   ////
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////  To Do:                                                      ////
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////   - nothing really                                           ////
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////                                                              ////
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////  Author(s):                                                  ////
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////   - José Ignacio Villar, jose@dte.us.es , jvillar@gmail.com  ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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////                                                              ////
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//// Copyright (C) 2009 José Ignacio Villar - jvillar@gmail.com   ////
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////                                                              ////
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//// This source file may be used and distributed without         ////
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//// restriction provided that this copyright statement is not    ////
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//// removed from the file and that any derivative work contains  ////
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//// the original copyright notice and the associated disclaimer. ////
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////                                                              ////
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//// This source file is free software; you can redistribute it   ////
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//// and/or modify it under the terms of the GNU Lesser General   ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 3 of the License, or (at your option) any     ////
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//// later version.                                               ////
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////                                                              ////
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//// This source is distributed in the hope that it will be       ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
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//// PURPOSE.  See the GNU Lesser General Public License for more ////
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//// details.                                                     ////
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////                                                              ////
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//// You should have received a copy of the GNU Lesser General    ////
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//// Public License along with this source; if not, download it   ////
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//// from http://www.gnu.org/licenses/lgpl.txt                    ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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`include "lcd_defines.v"
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module system(
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        input clk,
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        input reset,
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        input  [2:0] rot,
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        output [3:0] SF_D,
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        output LCD_E,
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        output LCD_RS,
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        output LCD_RW,
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        output SF_CE0,
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        output reg [7:0] led
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        );
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//----------------------------------------------------------------------------
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// rotary decoder
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//----------------------------------------------------------------------------
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wire rot_btn;
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wire rot_event;
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wire rot_left;
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rotary rotdec0 (
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        .clk(       clk        ),
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        .reset(     reset      ),
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        .rot(       rot        ),
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        // output
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        .rot_btn(   rot_btn    ),
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        .rot_event( rot_event  ),
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        .rot_left(  rot_left   )
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);
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//----------------------------------------------------------------------------
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// LCD Display
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//----------------------------------------------------------------------------
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reg     [`DAT_RNG]      dat = 8'b00100000;
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wire    [`WB_DAT_RNG]   wb_dat = {24'b0, dat};
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reg     [`ADDR_WIDTH:0]  addr = 0;
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wire    [`WB_ADDR_RNG]  wb_addr = {24'b0, addr};
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wire    [`WB_DAT_RNG]   status;
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wire                    busy = status[0];
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reg cs = 0;
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reg we = 0;
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wire ack;
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wb_lcd lcd  (
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        //
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        // I/O Ports
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        //
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        .wb_clk_i       ( clk ),
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        .wb_rst_i       ( reset),
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        //
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        // WB slave interface
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        //
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        .wb_dat_i       ( wb_dat ),
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        .wb_dat_o       ( status ),
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        .wb_adr_i       ( wb_addr ),
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        .wb_sel_i       (  ),
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        .wb_we_i        ( we ),
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        .wb_cyc_i       ( cs  ),
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        .wb_stb_i       ( cs ),
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        .wb_ack_o       ( ack ),
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        .wb_err_o       (  ),
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        //
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        // LCD interface
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        //
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        .SF_D   ( SF_D ),
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        .LCD_E  ( LCD_E ),
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        .LCD_RS ( LCD_RS ),
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        .LCD_RW ( LCD_RW )
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        );
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//----------------------------------------------------------------------------
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// Behavioural description
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//----------------------------------------------------------------------------
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assign SF_CE0 = 1'b1; // disable intel strataflash
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// Handles "start displaying character" shift
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reg [`DAT_RNG]  start_dat = 8'b00100000;
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reg wait_for_ack = 0;
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wire stall;
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assign stall = (wait_for_ack & ~ack);
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// Handles transfers to the display
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integer i = 0;
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always @(posedge clk)
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begin
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        if(reset) begin
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                i <= 0;
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                cs <= 1;
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                we <= 1;
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                addr <= 0;
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                dat <= start_dat;
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                led <= 8'b00100000;
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                start_dat <= 8'b00100000;
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        end else if(~stall) begin
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                if (i < 104) begin
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                        i <= i + 1;
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                        cs <= 1;
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                        we <= 1'b1;
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                        addr <= addr + 1;
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                        dat <= dat + 1;
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                        wait_for_ack <= 1;
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                end else if (i == 104) begin
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                        if(!busy) begin
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                                i <= i + 1;
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                                cs <= 1;
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                                addr <= 8'b10000000; // Command register
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                                dat <=  8'b00000001; // Repaint command
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                                we <= 1'b1;
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                                wait_for_ack <= 1;
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                        end else begin
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                                cs <= 0;
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                                wait_for_ack <= 0;
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                        end
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                end else if (i == 105) begin
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                        i <= i + 1;
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                        cs <= 0;
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                        we <= 1'b0;
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                        wait_for_ack <= 0;
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                end else if (rot_event && rot_left && !busy) begin
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                        i <= 0;
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                        led <= led - 1;
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                        start_dat <= start_dat - 1;
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                        cs <= 1;
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                        addr <= 0;
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                        we <= 1'b1;
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                        dat <= start_dat - 1;
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                        wait_for_ack <= 1;
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                end else if (rot_event && !busy) begin
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                        i <= 0;
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                        led <= led + 1;
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                        start_dat <= start_dat + 1;
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                        cs <= 1;
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                        addr <= 0;
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                        we <= 1'b1;
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                        dat <= start_dat + 1;
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                        wait_for_ack <= 1;
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                end
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        end
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end
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//                1'b1
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//                2'b01, 
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//                4'b0011,
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//                8'b00001111,
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//               16'b0000000011111111,
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//               32'b00000000000000001111111111111111
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//      {reset, busy, cs, we, ack, wb_dat[7:0], status[7:0], i, {10,1'b0}}
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endmodule

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