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// File: lcd.v
// Generated by MyHDL 0.6
// Date: Mon Apr 13 20:53:49 2009
 
`timescale 1ns/10ps
 
module lcd (
    clk,
    reset,
    dat,
    addr,
    we,
    repaint,
    busy,
    SF_D,
    LCD_E,
    LCD_RS,
    LCD_RW
);
 
input clk;
input reset;
input [31:0] dat;
input [6:0] addr;
input we;
input repaint;
output busy;
wire busy;
output [3:0] SF_D;
reg [3:0] SF_D;
output LCD_E;
reg LCD_E;
output LCD_RS;
wire LCD_RS;
output LCD_RW;
wire LCD_RW;
 
wire tx_init;
reg [6:0] pos;
wire delay_load;
reg tx_done;
reg [3:0] SF_D1;
reg [3:0] SF_D0;
reg LCD_E1;
reg LCD_E0;
wire delay_done;
reg [7:0] tx_byte;
wire output_selector;
reg [4:0] state;
reg [19:0] tx_delay_value;
reg [19:0] main_delay_value;
reg tx_delay_load;
reg [19:0] delay_value;
reg main_delay_load;
reg [2:0] tx_state;
reg [20:0] counter_counter;
 
reg [30:0] ram [0:67-1];
 
 
 
assign output_selector = ((state == 5'b00000) | (state == 5'b00001) | (state == 5'b00010) | (state == 5'b00011) | (state == 5'b00100) | (state == 5'b00101) | (state == 5'b00110) | (state == 5'b00111) | (state == 5'b01000) | (state == 5'b01001));
 
always @(main_delay_value, tx_delay_load, tx_delay_value) begin: LCD_CONUNTER_SHARING_VALUE
    if (tx_delay_load) begin
        delay_value <= tx_delay_value;
    end
    else begin
        delay_value <= main_delay_value;
    end
end
 
always @(posedge clk, posedge reset) begin: LCD_TXFSM
    if ((reset == 1)) begin
        tx_state <= 3'b110;
        SF_D0 <= 0;
        LCD_E0 <= 0;
    end
    else begin
        tx_delay_load <= 0;
 
        tx_delay_value <= 0;
 
        // synthesis parallel_case full_case
        casez (tx_state)
            3'b000: begin
                LCD_E0 <= 0;
                SF_D0 <= tx_byte[8-1:4];
                tx_delay_load <= 0;
                if (delay_done) begin
                    tx_state <= 3'b001;
                    tx_delay_load <= 1;
                    tx_delay_value <= 12;
                end
            end
            3'b001: begin
                LCD_E0 <= 1;
                SF_D0 <= tx_byte[8-1:4];
                tx_delay_load <= 0;
                if (delay_done) begin
                    tx_state <= 3'b010;
                    tx_delay_load <= 1;
                    tx_delay_value <= 50;
                end
            end
            3'b010: begin
                LCD_E0 <= 0;
                tx_delay_load <= 0;
                if (delay_done) begin
                    tx_state <= 3'b011;
                    tx_delay_load <= 1;
                    tx_delay_value <= 2;
                end
            end
            3'b011: begin
                LCD_E0 <= 0;
                SF_D0 <= tx_byte[4-1:0];
                tx_delay_load <= 0;
                if (delay_done) begin
                    tx_state <= 3'b100;
                    tx_delay_load <= 1;
                    tx_delay_value <= 12;
                end
            end
            3'b100: begin
                LCD_E0 <= 1;
                SF_D0 <= tx_byte[4-1:0];
                tx_delay_load <= 0;
                if (delay_done) begin
                    tx_state <= 3'b101;
                    tx_delay_load <= 1;
                    tx_delay_value <= 2000;
                end
            end
            3'b101: begin
                LCD_E0 <= 0;
                tx_delay_load <= 0;
                if (delay_done) begin
                    tx_state <= 3'b110;
                    tx_done <= 1;
                end
            end
            3'b110: begin
                LCD_E0 <= 0;
                tx_done <= 0;
                tx_delay_load <= 0;
                if (tx_init) begin
                    tx_state <= 3'b000;
                    tx_delay_load <= 1;
                    tx_delay_value <= 2;
                end
            end
            default: begin
                $finish;
            end
        endcase
    end
end
 
 
assign delay_load = (tx_delay_load || main_delay_load);
 
 
assign busy = (state != 5'b10100);
assign LCD_RW = 0;
 
always @(SF_D1, SF_D0, LCD_E1, LCD_E0, output_selector) begin: LCD_OUTPUT_TX_OR_INIT_MUX
    if (output_selector) begin
        SF_D <= SF_D1;
        LCD_E <= LCD_E1;
    end
    else begin
        SF_D <= SF_D0;
        LCD_E <= LCD_E0;
    end
end
 
always @(posedge clk) begin: LCD_MEMWRITE
    if (we) begin
        ram[addr] <= dat;
    end
end
 
always @(posedge clk, posedge reset) begin: LCD_DISPLAYFSM
    if ((reset == 1)) begin
        state <= 5'b00000;
        main_delay_load <= 0;
        main_delay_value <= 0;
        SF_D1 <= 0;
        LCD_E1 <= 0;
        tx_byte <= 0;
        pos <= 0;
    end
    else begin
        main_delay_load <= 0;
 
        main_delay_value <= 0;
 
        // synthesis parallel_case full_case
        casez (state)
            5'b00000: begin
                tx_byte <= 0;
                state <= 5'b00001;
                main_delay_load <= 1;
                main_delay_value <= 750000;
            end
            5'b00001: begin
                main_delay_load <= 0;
                if (delay_done) begin
                    state <= 5'b00010;
 
                    main_delay_load <= 1;
                    main_delay_value <= 11;
                end
            end
            5'b00010: begin
                main_delay_load <= 0;
                SF_D1 <= 3;
                LCD_E1 <= 1;
                if (delay_done) begin
                    state <= 5'b00011;
 
                    main_delay_load <= 1;
                    main_delay_value <= 205000;
                end
            end
            5'b00011: begin
                main_delay_load <= 0;
                LCD_E1 <= 0;
                if (delay_done) begin
                    state <= 5'b00100;
 
                    main_delay_load <= 1;
                    main_delay_value <= 11;
                end
            end
            5'b00100: begin
                main_delay_load <= 0;
                SF_D1 <= 3;
                LCD_E1 <= 1;
                if (delay_done) begin
                    state <= 5'b00101;
 
                    main_delay_load <= 1;
                    main_delay_value <= 5000;
                end
            end
            5'b00101: begin
                main_delay_load <= 0;
                LCD_E1 <= 0;
                if (delay_done) begin
                    state <= 5'b00110;
 
                    main_delay_load <= 1;
                    main_delay_value <= 11;
                end
            end
            5'b00110: begin
                main_delay_load <= 0;
                SF_D1 <= 3;
                LCD_E1 <= 1;
                if (delay_done) begin
                    state <= 5'b00111;
 
                    main_delay_load <= 1;
                    main_delay_value <= 2000;
                end
            end
            5'b00111: begin
                main_delay_load <= 0;
                LCD_E1 <= 0;
                if (delay_done) begin
                    state <= 5'b01000;
 
                    main_delay_load <= 1;
                    main_delay_value <= 11;
                end
            end
            5'b01000: begin
                main_delay_load <= 0;
                SF_D1 <= 2;
                LCD_E1 <= 1;
                if (delay_done) begin
                    state <= 5'b01001;
 
                    main_delay_load <= 1;
                    main_delay_value <= 2000;
                end
            end
            5'b01001: begin
                main_delay_load <= 0;
                LCD_E1 <= 0;
                if (delay_done) begin
                    state <= 5'b01010;
 
                end
            end
            5'b01010: begin
                tx_byte <= 40;
                if (tx_done) begin
                    state <= 5'b01011;
                end
            end
            5'b01011: begin
                tx_byte <= 6;
                if (tx_done) begin
                    state <= 5'b01100;
                end
            end
            5'b01100: begin
                tx_byte <= 12;
                if (tx_done) begin
                    state <= 5'b01101;
                end
            end
            5'b01101: begin
                tx_byte <= 1;
                if (tx_done) begin
                    state <= 5'b01110;
                    main_delay_load <= 1;
                    main_delay_value <= 82000;
                end
            end
            5'b01110: begin
                state <= 5'b01111;
            end
            5'b01111: begin
                tx_byte <= 0;
                if (delay_done) begin
                    state <= 5'b10000;
 
                end
            end
            5'b10000: begin
                tx_byte <= 128;
                if (tx_done) begin
                    state <= 5'b10001;
                    pos <= 0;
                end
            end
            5'b10001: begin
                tx_byte <= ram[pos];
                if (tx_done) begin
                    if ((pos == 21)) begin
                        state <= 5'b10010;
 
                    end
                    else begin
                        pos <= (pos + 1);
                    end
                end
            end
            5'b10010: begin
                tx_byte <= 192;
                if (tx_done) begin
                    state <= 5'b10011;
                    pos <= 64;
                end
            end
            5'b10011: begin
                tx_byte <= ram[pos];
                if (tx_done) begin
                    if ((pos == 85)) begin
                        state <= 5'b10100;
 
                    end
                    else begin
                        pos <= (pos + 1);
                    end
                end
            end
            5'b10100: begin
                tx_byte <= 0;
                if (repaint) begin
                    state <= 5'b01010;
                end
                else begin
                    state <= 5'b10100;
                end
            end
            default: begin
                $finish;
            end
        endcase
    end
end
 
 
assign delay_done = (counter_counter == 0);
 
always @(posedge clk) begin: LCD_COUNTER_COUNTDOWN_LOGIC
    if (delay_load) begin
        counter_counter <= delay_value;
    end
    else begin
        counter_counter <= (counter_counter - 1);
    end
end
 
 
assign tx_init = ((~tx_done) & ((state == 5'b01010) | (state == 5'b01011) | (state == 5'b01100) | (state == 5'b01101) | (state == 5'b10000) | (state == 5'b10001) | (state == 5'b10010) | (state == 5'b10011)));
assign LCD_RS = (~(((state == 5'b01010) != 0) | (state == 5'b01011) | (state == 5'b01100) | (state == 5'b01101) | (state == 5'b10000) | (state == 5'b10010)));
 
endmodule

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[/] [wb_lcd/] [trunk/] [myhdl/] [wb_lcd_workspace/] [workspace/] [.metadata/] [.plugins/] [org.eclipse.core.resources/] [.history/] [e9/] [50b3ea0f5e28001e10c48e21aa01bda3] - Blame information for rev 2

Line No.	Rev	Author	Line
1	2	jvillar	`// File: lcd.v`
2			`// Generated by MyHDL 0.6`
3			`// Date: Mon Apr 13 20:53:49 2009`
4
5			`timescale 1ns/10ps
6
7			`module lcd (`
8			`clk,`
9			`reset,`
10			`dat,`
11			`addr,`
12			`we,`
13			`repaint,`
14			`busy,`
15			`SF_D,`
16			`LCD_E,`
17			`LCD_RS,`
18			`LCD_RW`
19			`);`
20
21			`input clk;`
22			`input reset;`
23			`input [31:0] dat;`
24			`input [6:0] addr;`
25			`input we;`
26			`input repaint;`
27			`output busy;`
28			`wire busy;`
29			`output [3:0] SF_D;`
30			`reg [3:0] SF_D;`
31			`output LCD_E;`
32			`reg LCD_E;`
33			`output LCD_RS;`
34			`wire LCD_RS;`
35			`output LCD_RW;`
36			`wire LCD_RW;`
37
38			`wire tx_init;`
39			`reg [6:0] pos;`
40			`wire delay_load;`
41			`reg tx_done;`
42			`reg [3:0] SF_D1;`
43			`reg [3:0] SF_D0;`
44			`reg LCD_E1;`
45			`reg LCD_E0;`
46			`wire delay_done;`
47			`reg [7:0] tx_byte;`
48			`wire output_selector;`
49			`reg [4:0] state;`
50			`reg [19:0] tx_delay_value;`
51			`reg [19:0] main_delay_value;`
52			`reg tx_delay_load;`
53			`reg [19:0] delay_value;`
54			`reg main_delay_load;`
55			`reg [2:0] tx_state;`
56			`reg [20:0] counter_counter;`
57
58			`reg [30:0] ram [0:67-1];`
59
60
61
62			`assign output_selector = ((state == 5'b00000) \| (state == 5'b00001) \| (state == 5'b00010) \| (state == 5'b00011) \| (state == 5'b00100) \| (state == 5'b00101) \| (state == 5'b00110) \| (state == 5'b00111) \| (state == 5'b01000) \| (state == 5'b01001));`
63
64			`always @(main_delay_value, tx_delay_load, tx_delay_value) begin: LCD_CONUNTER_SHARING_VALUE`
65			`if (tx_delay_load) begin`
66			`delay_value <= tx_delay_value;`
67			`end`
68			`else begin`
69			`delay_value <= main_delay_value;`
70			`end`
71			`end`
72
73			`always @(posedge clk, posedge reset) begin: LCD_TXFSM`
74			`if ((reset == 1)) begin`
75			`tx_state <= 3'b110;`
76			`SF_D0 <= 0;`
77			`LCD_E0 <= 0;`
78			`end`
79			`else begin`
80			`tx_delay_load <= 0;`
81
82			`tx_delay_value <= 0;`
83
84			`// synthesis parallel_case full_case`
85			`casez (tx_state)`
86			`3'b000: begin`
87			`LCD_E0 <= 0;`
88			`SF_D0 <= tx_byte[8-1:4];`
89			`tx_delay_load <= 0;`
90			`if (delay_done) begin`
91			`tx_state <= 3'b001;`
92			`tx_delay_load <= 1;`
93			`tx_delay_value <= 12;`
94			`end`
95			`end`
96			`3'b001: begin`
97			`LCD_E0 <= 1;`
98			`SF_D0 <= tx_byte[8-1:4];`
99			`tx_delay_load <= 0;`
100			`if (delay_done) begin`
101			`tx_state <= 3'b010;`
102			`tx_delay_load <= 1;`
103			`tx_delay_value <= 50;`
104			`end`
105			`end`
106			`3'b010: begin`
107			`LCD_E0 <= 0;`
108			`tx_delay_load <= 0;`
109			`if (delay_done) begin`
110			`tx_state <= 3'b011;`
111			`tx_delay_load <= 1;`
112			`tx_delay_value <= 2;`
113			`end`
114			`end`
115			`3'b011: begin`
116			`LCD_E0 <= 0;`
117			`SF_D0 <= tx_byte[4-1:0];`
118			`tx_delay_load <= 0;`
119			`if (delay_done) begin`
120			`tx_state <= 3'b100;`
121			`tx_delay_load <= 1;`
122			`tx_delay_value <= 12;`
123			`end`
124			`end`
125			`3'b100: begin`
126			`LCD_E0 <= 1;`
127			`SF_D0 <= tx_byte[4-1:0];`
128			`tx_delay_load <= 0;`
129			`if (delay_done) begin`
130			`tx_state <= 3'b101;`
131			`tx_delay_load <= 1;`
132			`tx_delay_value <= 2000;`
133			`end`
134			`end`
135			`3'b101: begin`
136			`LCD_E0 <= 0;`
137			`tx_delay_load <= 0;`
138			`if (delay_done) begin`
139			`tx_state <= 3'b110;`
140			`tx_done <= 1;`
141			`end`
142			`end`
143			`3'b110: begin`
144			`LCD_E0 <= 0;`
145			`tx_done <= 0;`
146			`tx_delay_load <= 0;`
147			`if (tx_init) begin`
148			`tx_state <= 3'b000;`
149			`tx_delay_load <= 1;`
150			`tx_delay_value <= 2;`
151			`end`
152			`end`
153			`default: begin`
154			`$finish;`
155			`end`
156			`endcase`
157			`end`
158			`end`
159
160
161			`assign delay_load = (tx_delay_load \|\| main_delay_load);`
162
163
164			`assign busy = (state != 5'b10100);`
165			`assign LCD_RW = 0;`
166
167			`always @(SF_D1, SF_D0, LCD_E1, LCD_E0, output_selector) begin: LCD_OUTPUT_TX_OR_INIT_MUX`
168			`if (output_selector) begin`
169			`SF_D <= SF_D1;`
170			`LCD_E <= LCD_E1;`
171			`end`
172			`else begin`
173			`SF_D <= SF_D0;`
174			`LCD_E <= LCD_E0;`
175			`end`
176			`end`
177
178			`always @(posedge clk) begin: LCD_MEMWRITE`
179			`if (we) begin`
180			`ram[addr] <= dat;`
181			`end`
182			`end`
183
184			`always @(posedge clk, posedge reset) begin: LCD_DISPLAYFSM`
185			`if ((reset == 1)) begin`
186			`state <= 5'b00000;`
187			`main_delay_load <= 0;`
188			`main_delay_value <= 0;`
189			`SF_D1 <= 0;`
190			`LCD_E1 <= 0;`
191			`tx_byte <= 0;`
192			`pos <= 0;`
193			`end`
194			`else begin`
195			`main_delay_load <= 0;`
196
197			`main_delay_value <= 0;`
198
199			`// synthesis parallel_case full_case`
200			`casez (state)`
201			`5'b00000: begin`
202			`tx_byte <= 0;`
203			`state <= 5'b00001;`
204			`main_delay_load <= 1;`
205			`main_delay_value <= 750000;`
206			`end`
207			`5'b00001: begin`
208			`main_delay_load <= 0;`
209			`if (delay_done) begin`
210			`state <= 5'b00010;`
211
212			`main_delay_load <= 1;`
213			`main_delay_value <= 11;`
214			`end`
215			`end`
216			`5'b00010: begin`
217			`main_delay_load <= 0;`
218			`SF_D1 <= 3;`
219			`LCD_E1 <= 1;`
220			`if (delay_done) begin`
221			`state <= 5'b00011;`
222
223			`main_delay_load <= 1;`
224			`main_delay_value <= 205000;`
225			`end`
226			`end`
227			`5'b00011: begin`
228			`main_delay_load <= 0;`
229			`LCD_E1 <= 0;`
230			`if (delay_done) begin`
231			`state <= 5'b00100;`
232
233			`main_delay_load <= 1;`
234			`main_delay_value <= 11;`
235			`end`
236			`end`
237			`5'b00100: begin`
238			`main_delay_load <= 0;`
239			`SF_D1 <= 3;`
240			`LCD_E1 <= 1;`
241			`if (delay_done) begin`
242			`state <= 5'b00101;`
243
244			`main_delay_load <= 1;`
245			`main_delay_value <= 5000;`
246			`end`
247			`end`
248			`5'b00101: begin`
249			`main_delay_load <= 0;`
250			`LCD_E1 <= 0;`
251			`if (delay_done) begin`
252			`state <= 5'b00110;`
253
254			`main_delay_load <= 1;`
255			`main_delay_value <= 11;`
256			`end`
257			`end`
258			`5'b00110: begin`
259			`main_delay_load <= 0;`
260			`SF_D1 <= 3;`
261			`LCD_E1 <= 1;`
262			`if (delay_done) begin`
263			`state <= 5'b00111;`
264
265			`main_delay_load <= 1;`
266			`main_delay_value <= 2000;`
267			`end`
268			`end`
269			`5'b00111: begin`
270			`main_delay_load <= 0;`
271			`LCD_E1 <= 0;`
272			`if (delay_done) begin`
273			`state <= 5'b01000;`
274
275			`main_delay_load <= 1;`
276			`main_delay_value <= 11;`
277			`end`
278			`end`
279			`5'b01000: begin`
280			`main_delay_load <= 0;`
281			`SF_D1 <= 2;`
282			`LCD_E1 <= 1;`
283			`if (delay_done) begin`
284			`state <= 5'b01001;`
285
286			`main_delay_load <= 1;`
287			`main_delay_value <= 2000;`
288			`end`
289			`end`
290			`5'b01001: begin`
291			`main_delay_load <= 0;`
292			`LCD_E1 <= 0;`
293			`if (delay_done) begin`
294			`state <= 5'b01010;`
295
296			`end`
297			`end`
298			`5'b01010: begin`
299			`tx_byte <= 40;`
300			`if (tx_done) begin`
301			`state <= 5'b01011;`
302			`end`
303			`end`
304			`5'b01011: begin`
305			`tx_byte <= 6;`
306			`if (tx_done) begin`
307			`state <= 5'b01100;`
308			`end`
309			`end`
310			`5'b01100: begin`
311			`tx_byte <= 12;`
312			`if (tx_done) begin`
313			`state <= 5'b01101;`
314			`end`
315			`end`
316			`5'b01101: begin`
317			`tx_byte <= 1;`
318			`if (tx_done) begin`
319			`state <= 5'b01110;`
320			`main_delay_load <= 1;`
321			`main_delay_value <= 82000;`
322			`end`
323			`end`
324			`5'b01110: begin`
325			`state <= 5'b01111;`
326			`end`
327			`5'b01111: begin`
328			`tx_byte <= 0;`
329			`if (delay_done) begin`
330			`state <= 5'b10000;`
331
332			`end`
333			`end`
334			`5'b10000: begin`
335			`tx_byte <= 128;`
336			`if (tx_done) begin`
337			`state <= 5'b10001;`
338			`pos <= 0;`
339			`end`
340			`end`
341			`5'b10001: begin`
342			`tx_byte <= ram[pos];`
343			`if (tx_done) begin`
344			`if ((pos == 21)) begin`
345			`state <= 5'b10010;`
346
347			`end`
348			`else begin`
349			`pos <= (pos + 1);`
350			`end`
351			`end`
352			`end`
353			`5'b10010: begin`
354			`tx_byte <= 192;`
355			`if (tx_done) begin`
356			`state <= 5'b10011;`
357			`pos <= 64;`
358			`end`
359			`end`
360			`5'b10011: begin`
361			`tx_byte <= ram[pos];`
362			`if (tx_done) begin`
363			`if ((pos == 85)) begin`
364			`state <= 5'b10100;`
365
366			`end`
367			`else begin`
368			`pos <= (pos + 1);`
369			`end`
370			`end`
371			`end`
372			`5'b10100: begin`
373			`tx_byte <= 0;`
374			`if (repaint) begin`
375			`state <= 5'b01010;`
376			`end`
377			`else begin`
378			`state <= 5'b10100;`
379			`end`
380			`end`
381			`default: begin`
382			`$finish;`
383			`end`
384			`endcase`
385			`end`
386			`end`
387
388
389			`assign delay_done = (counter_counter == 0);`
390
391			`always @(posedge clk) begin: LCD_COUNTER_COUNTDOWN_LOGIC`
392			`if (delay_load) begin`
393			`counter_counter <= delay_value;`
394			`end`
395			`else begin`
396			`counter_counter <= (counter_counter - 1);`
397			`end`
398			`end`
399
400
401			`assign tx_init = ((~tx_done) & ((state == 5'b01010) \| (state == 5'b01011) \| (state == 5'b01100) \| (state == 5'b01101) \| (state == 5'b10000) \| (state == 5'b10001) \| (state == 5'b10010) \| (state == 5'b10011)));`
402			`assign LCD_RS = (~(((state == 5'b01010) != 0) \| (state == 5'b01011) \| (state == 5'b01100) \| (state == 5'b01101) \| (state == 5'b10000) \| (state == 5'b10010)));`
403
404			`endmodule`