URL https://opencores.org/ocsvn/wb_lcd/wb_lcd/trunk

Subversion Repositories wb_lcd

[/] [wb_lcd/] [trunk/] [myhdl/] [wb_lcd_workspace_ramless/] [workspace/] [lcd_display/] [src/] [wb_lcd.v] - Blame information for rev 2

Details | Compare with Previous | View Log


// File: wb_lcd.v
// Generated by MyHDL 0.6
// Date: Mon Apr 20 03:13:34 2009
 
`timescale 1ns/10ps
 
module wb_lcd (
    wb_clk_i,
    wb_rst_i,
    wb_dat_i,
    wb_dat_o,
    wb_adr_i,
    wb_sel_i,
    wb_we_i,
    wb_cyc_i,
    wb_stb_i,
    wb_ack_o,
    SF_D,
    LCD_E,
    LCD_RS,
    LCD_RW
);
 
input wb_clk_i;
input wb_rst_i;
input [31:0] wb_dat_i;
output [31:0] wb_dat_o;
reg [31:0] wb_dat_o;
input [31:0] wb_adr_i;
input [3:0] wb_sel_i;
input wb_we_i;
input wb_cyc_i;
input wb_stb_i;
output wb_ack_o;
reg wb_ack_o;
output [3:0] SF_D;
reg [3:0] SF_D;
output LCD_E;
reg LCD_E;
output LCD_RS;
wire LCD_RS;
output LCD_RW;
wire LCD_RW;
 
wire busy;
reg lcd_we;
wire mylcd_tx_init;
wire mylcd_delay_load;
reg mylcd_tx_done;
reg [3:0] mylcd_SF_D1;
reg [3:0] mylcd_SF_D0;
reg mylcd_LCD_E1;
reg mylcd_LCD_E0;
wire mylcd_delay_done;
reg [7:0] mylcd_tx_byte;
reg [6:0] mylcd_wr_addr;
wire mylcd_output_selector;
reg [4:0] mylcd_state;
reg [19:0] mylcd_tx_delay_value;
reg [19:0] mylcd_main_delay_value;
reg mylcd_tx_delay_load;
reg [19:0] mylcd_delay_value;
reg [6:0] mylcd_wr_dat;
reg mylcd_main_delay_load;
reg [2:0] mylcd_tx_state;
reg [20:0] mylcd_counter_counter;
 
 
 
always @(busy, wb_we_i, wb_stb_i, wb_cyc_i, wb_adr_i) begin: WB_LCD_WISHBONE_LOGIC
    wb_ack_o <= (wb_cyc_i & wb_stb_i);
 
    lcd_we <= (wb_cyc_i & wb_stb_i & wb_we_i & (wb_adr_i != 128));
    if (busy) begin
        wb_dat_o <= 1;
    end
    else begin
        wb_dat_o <= 0;
    end
end
 
 
assign mylcd_output_selector = ((mylcd_state == 5'b00000) | (mylcd_state == 5'b00001) | (mylcd_state == 5'b00010) | (mylcd_state == 5'b00011) | (mylcd_state == 5'b00100) | (mylcd_state == 5'b00101) | (mylcd_state == 5'b00110) | (mylcd_state == 5'b00111) | (mylcd_state == 5'b01000) | (mylcd_state == 5'b01001));
 
always @(mylcd_main_delay_value, mylcd_tx_delay_load, mylcd_tx_delay_value) begin: WB_LCD_MYLCD_CONUNTER_SHARING_VALUE
    if (mylcd_tx_delay_load) begin
        mylcd_delay_value <= mylcd_tx_delay_value;
    end
    else begin
        mylcd_delay_value <= mylcd_main_delay_value;
    end
end
 
always @(posedge wb_clk_i, posedge wb_rst_i) begin: WB_LCD_MYLCD_DISPLAYFSM
    if ((wb_rst_i == 1)) begin
        mylcd_state <= 5'b00000;
        mylcd_main_delay_load <= 0;
        mylcd_main_delay_value <= 0;
        mylcd_SF_D1 <= 0;
        mylcd_LCD_E1 <= 0;
        mylcd_tx_byte <= 0;
    end
    else begin
        mylcd_main_delay_load <= 0;
 
        mylcd_main_delay_value <= 0;
 
        // synthesis parallel_case full_case
        casez (mylcd_state)
            5'b00000: begin
                mylcd_tx_byte <= 0;
                mylcd_state <= 5'b00001;
                mylcd_main_delay_load <= 1;
                mylcd_main_delay_value <= 750000;
            end
            5'b00001: begin
                mylcd_main_delay_load <= 0;
                if (mylcd_delay_done) begin
                    mylcd_state <= 5'b00010;
 
                    mylcd_main_delay_load <= 1;
                    mylcd_main_delay_value <= 11;
                end
            end
            5'b00010: begin
                mylcd_main_delay_load <= 0;
                mylcd_SF_D1 <= 3;
                mylcd_LCD_E1 <= 1;
                if (mylcd_delay_done) begin
                    mylcd_state <= 5'b00011;
 
                    mylcd_main_delay_load <= 1;
                    mylcd_main_delay_value <= 205000;
                end
            end
            5'b00011: begin
                mylcd_main_delay_load <= 0;
                mylcd_LCD_E1 <= 0;
                if (mylcd_delay_done) begin
                    mylcd_state <= 5'b00100;
 
                    mylcd_main_delay_load <= 1;
                    mylcd_main_delay_value <= 11;
                end
            end
            5'b00100: begin
                mylcd_main_delay_load <= 0;
                mylcd_SF_D1 <= 3;
                mylcd_LCD_E1 <= 1;
                if (mylcd_delay_done) begin
                    mylcd_state <= 5'b00101;
 
                    mylcd_main_delay_load <= 1;
                    mylcd_main_delay_value <= 5000;
                end
            end
            5'b00101: begin
                mylcd_main_delay_load <= 0;
                mylcd_LCD_E1 <= 0;
                if (mylcd_delay_done) begin
                    mylcd_state <= 5'b00110;
 
                    mylcd_main_delay_load <= 1;
                    mylcd_main_delay_value <= 11;
                end
            end
            5'b00110: begin
                mylcd_main_delay_load <= 0;
                mylcd_SF_D1 <= 3;
                mylcd_LCD_E1 <= 1;
                if (mylcd_delay_done) begin
                    mylcd_state <= 5'b00111;
 
                    mylcd_main_delay_load <= 1;
                    mylcd_main_delay_value <= 2000;
                end
            end
            5'b00111: begin
                mylcd_main_delay_load <= 0;
                mylcd_LCD_E1 <= 0;
                if (mylcd_delay_done) begin
                    mylcd_state <= 5'b01000;
 
                    mylcd_main_delay_load <= 1;
                    mylcd_main_delay_value <= 11;
                end
            end
            5'b01000: begin
                mylcd_main_delay_load <= 0;
                mylcd_SF_D1 <= 2;
                mylcd_LCD_E1 <= 1;
                if (mylcd_delay_done) begin
                    mylcd_state <= 5'b01001;
 
                    mylcd_main_delay_load <= 1;
                    mylcd_main_delay_value <= 2000;
                end
            end
            5'b01001: begin
                mylcd_main_delay_load <= 0;
                mylcd_LCD_E1 <= 0;
                if (mylcd_delay_done) begin
                    mylcd_state <= 5'b01010;
 
                end
            end
            5'b01010: begin
                mylcd_tx_byte <= 40;
                if (mylcd_tx_done) begin
                    mylcd_state <= 5'b01011;
                end
            end
            5'b01011: begin
                mylcd_tx_byte <= 6;
                if (mylcd_tx_done) begin
                    mylcd_state <= 5'b01100;
                end
            end
            5'b01100: begin
                mylcd_tx_byte <= 12;
                if (mylcd_tx_done) begin
                    mylcd_state <= 5'b01101;
                end
            end
            5'b01101: begin
                mylcd_tx_byte <= 1;
                if (mylcd_tx_done) begin
                    mylcd_state <= 5'b01111;
                    mylcd_main_delay_load <= 1;
                    mylcd_main_delay_value <= 82000;
                end
            end
            5'b01110: begin
                mylcd_state <= 5'b01111;
            end
            5'b01111: begin
                mylcd_tx_byte <= 0;
                if (mylcd_delay_done) begin
                    mylcd_state <= 5'b10000;
 
                end
            end
            5'b10000: begin
                mylcd_tx_byte <= 0;
                if (lcd_we) begin
                    mylcd_state <= 5'b10001;
                    mylcd_wr_addr <= wb_adr_i;
                    mylcd_wr_dat <= wb_dat_i;
                end
                else begin
                    mylcd_state <= 5'b10000;
                end
            end
            5'b10001: begin
                mylcd_tx_byte <= (128 | mylcd_wr_addr);
                if (mylcd_tx_done) begin
                    mylcd_state <= 5'b10010;
                end
            end
            5'b10010: begin
                mylcd_tx_byte <= mylcd_wr_dat;
                if (mylcd_tx_done) begin
                    mylcd_state <= 5'b10000;
 
                end
            end
        endcase
    end
end
 
always @(posedge wb_clk_i, posedge wb_rst_i) begin: WB_LCD_MYLCD_TXFSM
    if ((wb_rst_i == 1)) begin
        mylcd_tx_state <= 3'b110;
        mylcd_SF_D0 <= 0;
        mylcd_LCD_E0 <= 0;
    end
    else begin
        mylcd_tx_delay_load <= 0;
 
        mylcd_tx_delay_value <= 0;
 
        // synthesis parallel_case full_case
        casez (mylcd_tx_state)
            3'b000: begin
                mylcd_LCD_E0 <= 0;
                mylcd_SF_D0 <= mylcd_tx_byte[8-1:4];
                mylcd_tx_delay_load <= 0;
                if (mylcd_delay_done) begin
                    mylcd_tx_state <= 3'b001;
                    mylcd_tx_delay_load <= 1;
                    mylcd_tx_delay_value <= 12;
                end
            end
            3'b001: begin
                mylcd_LCD_E0 <= 1;
                mylcd_SF_D0 <= mylcd_tx_byte[8-1:4];
                mylcd_tx_delay_load <= 0;
                if (mylcd_delay_done) begin
                    mylcd_tx_state <= 3'b010;
                    mylcd_tx_delay_load <= 1;
                    mylcd_tx_delay_value <= 50;
                end
            end
            3'b010: begin
                mylcd_LCD_E0 <= 0;
                mylcd_tx_delay_load <= 0;
                if (mylcd_delay_done) begin
                    mylcd_tx_state <= 3'b011;
                    mylcd_tx_delay_load <= 1;
                    mylcd_tx_delay_value <= 2;
                end
            end
            3'b011: begin
                mylcd_LCD_E0 <= 0;
                mylcd_SF_D0 <= mylcd_tx_byte[4-1:0];
                mylcd_tx_delay_load <= 0;
                if (mylcd_delay_done) begin
                    mylcd_tx_state <= 3'b100;
                    mylcd_tx_delay_load <= 1;
                    mylcd_tx_delay_value <= 12;
                end
            end
            3'b100: begin
                mylcd_LCD_E0 <= 1;
                mylcd_SF_D0 <= mylcd_tx_byte[4-1:0];
                mylcd_tx_delay_load <= 0;
                if (mylcd_delay_done) begin
                    mylcd_tx_state <= 3'b101;
                    mylcd_tx_delay_load <= 1;
                    mylcd_tx_delay_value <= 2000;
                end
            end
            3'b101: begin
                mylcd_LCD_E0 <= 0;
                mylcd_tx_delay_load <= 0;
                if (mylcd_delay_done) begin
                    mylcd_tx_state <= 3'b110;
                    mylcd_tx_done <= 1;
                end
            end
            3'b110: begin
                mylcd_LCD_E0 <= 0;
                mylcd_tx_done <= 0;
                mylcd_tx_delay_load <= 0;
                if (mylcd_tx_init) begin
                    mylcd_tx_state <= 3'b000;
                    mylcd_tx_delay_load <= 1;
                    mylcd_tx_delay_value <= 2;
                end
            end
        endcase
    end
end
 
 
assign mylcd_delay_load = (mylcd_tx_delay_load || mylcd_main_delay_load);
 
 
assign busy = (mylcd_state != 5'b10000);
assign LCD_RW = 0;
 
always @(mylcd_SF_D1, mylcd_SF_D0, mylcd_LCD_E1, mylcd_LCD_E0, mylcd_output_selector) begin: WB_LCD_MYLCD_OUTPUT_TX_OR_INIT_MUX
    if (mylcd_output_selector) begin
        SF_D <= mylcd_SF_D1;
        LCD_E <= mylcd_LCD_E1;
    end
    else begin
        SF_D <= mylcd_SF_D0;
        LCD_E <= mylcd_LCD_E0;
    end
end
 
 
assign mylcd_tx_init = ((~mylcd_tx_done) & ((mylcd_state == 5'b01010) | (mylcd_state == 5'b01011) | (mylcd_state == 5'b01100) | (mylcd_state == 5'b01101) | (mylcd_state == 5'b10001) | (mylcd_state == 5'b10010)));
assign LCD_RS = (~(((mylcd_state == 5'b01010) != 0) | (mylcd_state == 5'b01011) | (mylcd_state == 5'b01100) | (mylcd_state == 5'b01101) | (mylcd_state == 5'b10001)));
 
 
assign mylcd_delay_done = (mylcd_counter_counter == 0);
 
always @(posedge wb_clk_i) begin: WB_LCD_MYLCD_COUNTER_COUNTDOWN_LOGIC
    if (mylcd_delay_load) begin
        mylcd_counter_counter <= mylcd_delay_value;
    end
    else begin
        mylcd_counter_counter <= (mylcd_counter_counter - 1);
    end
end
 
endmodule

Browse

Tools

Subversion Repositories wb_lcd

[/] [wb_lcd/] [trunk/] [myhdl/] [wb_lcd_workspace_ramless/] [workspace/] [lcd_display/] [src/] [wb_lcd.v] - Blame information for rev 2

Line No.	Rev	Author	Line
1	2	jvillar	`// File: wb_lcd.v`
2			`// Generated by MyHDL 0.6`
3			`// Date: Mon Apr 20 03:13:34 2009`
4
5			`timescale 1ns/10ps
6
7			`module wb_lcd (`
8			`wb_clk_i,`
9			`wb_rst_i,`
10			`wb_dat_i,`
11			`wb_dat_o,`
12			`wb_adr_i,`
13			`wb_sel_i,`
14			`wb_we_i,`
15			`wb_cyc_i,`
16			`wb_stb_i,`
17			`wb_ack_o,`
18			`SF_D,`
19			`LCD_E,`
20			`LCD_RS,`
21			`LCD_RW`
22			`);`
23
24			`input wb_clk_i;`
25			`input wb_rst_i;`
26			`input [31:0] wb_dat_i;`
27			`output [31:0] wb_dat_o;`
28			`reg [31:0] wb_dat_o;`
29			`input [31:0] wb_adr_i;`
30			`input [3:0] wb_sel_i;`
31			`input wb_we_i;`
32			`input wb_cyc_i;`
33			`input wb_stb_i;`
34			`output wb_ack_o;`
35			`reg wb_ack_o;`
36			`output [3:0] SF_D;`
37			`reg [3:0] SF_D;`
38			`output LCD_E;`
39			`reg LCD_E;`
40			`output LCD_RS;`
41			`wire LCD_RS;`
42			`output LCD_RW;`
43			`wire LCD_RW;`
44
45			`wire busy;`
46			`reg lcd_we;`
47			`wire mylcd_tx_init;`
48			`wire mylcd_delay_load;`
49			`reg mylcd_tx_done;`
50			`reg [3:0] mylcd_SF_D1;`
51			`reg [3:0] mylcd_SF_D0;`
52			`reg mylcd_LCD_E1;`
53			`reg mylcd_LCD_E0;`
54			`wire mylcd_delay_done;`
55			`reg [7:0] mylcd_tx_byte;`
56			`reg [6:0] mylcd_wr_addr;`
57			`wire mylcd_output_selector;`
58			`reg [4:0] mylcd_state;`
59			`reg [19:0] mylcd_tx_delay_value;`
60			`reg [19:0] mylcd_main_delay_value;`
61			`reg mylcd_tx_delay_load;`
62			`reg [19:0] mylcd_delay_value;`
63			`reg [6:0] mylcd_wr_dat;`
64			`reg mylcd_main_delay_load;`
65			`reg [2:0] mylcd_tx_state;`
66			`reg [20:0] mylcd_counter_counter;`
67
68
69
70			`always @(busy, wb_we_i, wb_stb_i, wb_cyc_i, wb_adr_i) begin: WB_LCD_WISHBONE_LOGIC`
71			`wb_ack_o <= (wb_cyc_i & wb_stb_i);`
72
73			`lcd_we <= (wb_cyc_i & wb_stb_i & wb_we_i & (wb_adr_i != 128));`
74			`if (busy) begin`
75			`wb_dat_o <= 1;`
76			`end`
77			`else begin`
78			`wb_dat_o <= 0;`
79			`end`
80			`end`
81
82
83			`assign mylcd_output_selector = ((mylcd_state == 5'b00000) \| (mylcd_state == 5'b00001) \| (mylcd_state == 5'b00010) \| (mylcd_state == 5'b00011) \| (mylcd_state == 5'b00100) \| (mylcd_state == 5'b00101) \| (mylcd_state == 5'b00110) \| (mylcd_state == 5'b00111) \| (mylcd_state == 5'b01000) \| (mylcd_state == 5'b01001));`
84
85			`always @(mylcd_main_delay_value, mylcd_tx_delay_load, mylcd_tx_delay_value) begin: WB_LCD_MYLCD_CONUNTER_SHARING_VALUE`
86			`if (mylcd_tx_delay_load) begin`
87			`mylcd_delay_value <= mylcd_tx_delay_value;`
88			`end`
89			`else begin`
90			`mylcd_delay_value <= mylcd_main_delay_value;`
91			`end`
92			`end`
93
94			`always @(posedge wb_clk_i, posedge wb_rst_i) begin: WB_LCD_MYLCD_DISPLAYFSM`
95			`if ((wb_rst_i == 1)) begin`
96			`mylcd_state <= 5'b00000;`
97			`mylcd_main_delay_load <= 0;`
98			`mylcd_main_delay_value <= 0;`
99			`mylcd_SF_D1 <= 0;`
100			`mylcd_LCD_E1 <= 0;`
101			`mylcd_tx_byte <= 0;`
102			`end`
103			`else begin`
104			`mylcd_main_delay_load <= 0;`
105
106			`mylcd_main_delay_value <= 0;`
107
108			`// synthesis parallel_case full_case`
109			`casez (mylcd_state)`
110			`5'b00000: begin`
111			`mylcd_tx_byte <= 0;`
112			`mylcd_state <= 5'b00001;`
113			`mylcd_main_delay_load <= 1;`
114			`mylcd_main_delay_value <= 750000;`
115			`end`
116			`5'b00001: begin`
117			`mylcd_main_delay_load <= 0;`
118			`if (mylcd_delay_done) begin`
119			`mylcd_state <= 5'b00010;`
120
121			`mylcd_main_delay_load <= 1;`
122			`mylcd_main_delay_value <= 11;`
123			`end`
124			`end`
125			`5'b00010: begin`
126			`mylcd_main_delay_load <= 0;`
127			`mylcd_SF_D1 <= 3;`
128			`mylcd_LCD_E1 <= 1;`
129			`if (mylcd_delay_done) begin`
130			`mylcd_state <= 5'b00011;`
131
132			`mylcd_main_delay_load <= 1;`
133			`mylcd_main_delay_value <= 205000;`
134			`end`
135			`end`
136			`5'b00011: begin`
137			`mylcd_main_delay_load <= 0;`
138			`mylcd_LCD_E1 <= 0;`
139			`if (mylcd_delay_done) begin`
140			`mylcd_state <= 5'b00100;`
141
142			`mylcd_main_delay_load <= 1;`
143			`mylcd_main_delay_value <= 11;`
144			`end`
145			`end`
146			`5'b00100: begin`
147			`mylcd_main_delay_load <= 0;`
148			`mylcd_SF_D1 <= 3;`
149			`mylcd_LCD_E1 <= 1;`
150			`if (mylcd_delay_done) begin`
151			`mylcd_state <= 5'b00101;`
152
153			`mylcd_main_delay_load <= 1;`
154			`mylcd_main_delay_value <= 5000;`
155			`end`
156			`end`
157			`5'b00101: begin`
158			`mylcd_main_delay_load <= 0;`
159			`mylcd_LCD_E1 <= 0;`
160			`if (mylcd_delay_done) begin`
161			`mylcd_state <= 5'b00110;`
162
163			`mylcd_main_delay_load <= 1;`
164			`mylcd_main_delay_value <= 11;`
165			`end`
166			`end`
167			`5'b00110: begin`
168			`mylcd_main_delay_load <= 0;`
169			`mylcd_SF_D1 <= 3;`
170			`mylcd_LCD_E1 <= 1;`
171			`if (mylcd_delay_done) begin`
172			`mylcd_state <= 5'b00111;`
173
174			`mylcd_main_delay_load <= 1;`
175			`mylcd_main_delay_value <= 2000;`
176			`end`
177			`end`
178			`5'b00111: begin`
179			`mylcd_main_delay_load <= 0;`
180			`mylcd_LCD_E1 <= 0;`
181			`if (mylcd_delay_done) begin`
182			`mylcd_state <= 5'b01000;`
183
184			`mylcd_main_delay_load <= 1;`
185			`mylcd_main_delay_value <= 11;`
186			`end`
187			`end`
188			`5'b01000: begin`
189			`mylcd_main_delay_load <= 0;`
190			`mylcd_SF_D1 <= 2;`
191			`mylcd_LCD_E1 <= 1;`
192			`if (mylcd_delay_done) begin`
193			`mylcd_state <= 5'b01001;`
194
195			`mylcd_main_delay_load <= 1;`
196			`mylcd_main_delay_value <= 2000;`
197			`end`
198			`end`
199			`5'b01001: begin`
200			`mylcd_main_delay_load <= 0;`
201			`mylcd_LCD_E1 <= 0;`
202			`if (mylcd_delay_done) begin`
203			`mylcd_state <= 5'b01010;`
204
205			`end`
206			`end`
207			`5'b01010: begin`
208			`mylcd_tx_byte <= 40;`
209			`if (mylcd_tx_done) begin`
210			`mylcd_state <= 5'b01011;`
211			`end`
212			`end`
213			`5'b01011: begin`
214			`mylcd_tx_byte <= 6;`
215			`if (mylcd_tx_done) begin`
216			`mylcd_state <= 5'b01100;`
217			`end`
218			`end`
219			`5'b01100: begin`
220			`mylcd_tx_byte <= 12;`
221			`if (mylcd_tx_done) begin`
222			`mylcd_state <= 5'b01101;`
223			`end`
224			`end`
225			`5'b01101: begin`
226			`mylcd_tx_byte <= 1;`
227			`if (mylcd_tx_done) begin`
228			`mylcd_state <= 5'b01111;`
229			`mylcd_main_delay_load <= 1;`
230			`mylcd_main_delay_value <= 82000;`
231			`end`
232			`end`
233			`5'b01110: begin`
234			`mylcd_state <= 5'b01111;`
235			`end`
236			`5'b01111: begin`
237			`mylcd_tx_byte <= 0;`
238			`if (mylcd_delay_done) begin`
239			`mylcd_state <= 5'b10000;`
240
241			`end`
242			`end`
243			`5'b10000: begin`
244			`mylcd_tx_byte <= 0;`
245			`if (lcd_we) begin`
246			`mylcd_state <= 5'b10001;`
247			`mylcd_wr_addr <= wb_adr_i;`
248			`mylcd_wr_dat <= wb_dat_i;`
249			`end`
250			`else begin`
251			`mylcd_state <= 5'b10000;`
252			`end`
253			`end`
254			`5'b10001: begin`
255			`mylcd_tx_byte <= (128 \| mylcd_wr_addr);`
256			`if (mylcd_tx_done) begin`
257			`mylcd_state <= 5'b10010;`
258			`end`
259			`end`
260			`5'b10010: begin`
261			`mylcd_tx_byte <= mylcd_wr_dat;`
262			`if (mylcd_tx_done) begin`
263			`mylcd_state <= 5'b10000;`
264
265			`end`
266			`end`
267			`endcase`
268			`end`
269			`end`
270
271			`always @(posedge wb_clk_i, posedge wb_rst_i) begin: WB_LCD_MYLCD_TXFSM`
272			`if ((wb_rst_i == 1)) begin`
273			`mylcd_tx_state <= 3'b110;`
274			`mylcd_SF_D0 <= 0;`
275			`mylcd_LCD_E0 <= 0;`
276			`end`
277			`else begin`
278			`mylcd_tx_delay_load <= 0;`
279
280			`mylcd_tx_delay_value <= 0;`
281
282			`// synthesis parallel_case full_case`
283			`casez (mylcd_tx_state)`
284			`3'b000: begin`
285			`mylcd_LCD_E0 <= 0;`
286			`mylcd_SF_D0 <= mylcd_tx_byte[8-1:4];`
287			`mylcd_tx_delay_load <= 0;`
288			`if (mylcd_delay_done) begin`
289			`mylcd_tx_state <= 3'b001;`
290			`mylcd_tx_delay_load <= 1;`
291			`mylcd_tx_delay_value <= 12;`
292			`end`
293			`end`
294			`3'b001: begin`
295			`mylcd_LCD_E0 <= 1;`
296			`mylcd_SF_D0 <= mylcd_tx_byte[8-1:4];`
297			`mylcd_tx_delay_load <= 0;`
298			`if (mylcd_delay_done) begin`
299			`mylcd_tx_state <= 3'b010;`
300			`mylcd_tx_delay_load <= 1;`
301			`mylcd_tx_delay_value <= 50;`
302			`end`
303			`end`
304			`3'b010: begin`
305			`mylcd_LCD_E0 <= 0;`
306			`mylcd_tx_delay_load <= 0;`
307			`if (mylcd_delay_done) begin`
308			`mylcd_tx_state <= 3'b011;`
309			`mylcd_tx_delay_load <= 1;`
310			`mylcd_tx_delay_value <= 2;`
311			`end`
312			`end`
313			`3'b011: begin`
314			`mylcd_LCD_E0 <= 0;`
315			`mylcd_SF_D0 <= mylcd_tx_byte[4-1:0];`
316			`mylcd_tx_delay_load <= 0;`
317			`if (mylcd_delay_done) begin`
318			`mylcd_tx_state <= 3'b100;`
319			`mylcd_tx_delay_load <= 1;`
320			`mylcd_tx_delay_value <= 12;`
321			`end`
322			`end`
323			`3'b100: begin`
324			`mylcd_LCD_E0 <= 1;`
325			`mylcd_SF_D0 <= mylcd_tx_byte[4-1:0];`
326			`mylcd_tx_delay_load <= 0;`
327			`if (mylcd_delay_done) begin`
328			`mylcd_tx_state <= 3'b101;`
329			`mylcd_tx_delay_load <= 1;`
330			`mylcd_tx_delay_value <= 2000;`
331			`end`
332			`end`
333			`3'b101: begin`
334			`mylcd_LCD_E0 <= 0;`
335			`mylcd_tx_delay_load <= 0;`
336			`if (mylcd_delay_done) begin`
337			`mylcd_tx_state <= 3'b110;`
338			`mylcd_tx_done <= 1;`
339			`end`
340			`end`
341			`3'b110: begin`
342			`mylcd_LCD_E0 <= 0;`
343			`mylcd_tx_done <= 0;`
344			`mylcd_tx_delay_load <= 0;`
345			`if (mylcd_tx_init) begin`
346			`mylcd_tx_state <= 3'b000;`
347			`mylcd_tx_delay_load <= 1;`
348			`mylcd_tx_delay_value <= 2;`
349			`end`
350			`end`
351			`endcase`
352			`end`
353			`end`
354
355
356			`assign mylcd_delay_load = (mylcd_tx_delay_load \|\| mylcd_main_delay_load);`
357
358
359			`assign busy = (mylcd_state != 5'b10000);`
360			`assign LCD_RW = 0;`
361
362			`always @(mylcd_SF_D1, mylcd_SF_D0, mylcd_LCD_E1, mylcd_LCD_E0, mylcd_output_selector) begin: WB_LCD_MYLCD_OUTPUT_TX_OR_INIT_MUX`
363			`if (mylcd_output_selector) begin`
364			`SF_D <= mylcd_SF_D1;`
365			`LCD_E <= mylcd_LCD_E1;`
366			`end`
367			`else begin`
368			`SF_D <= mylcd_SF_D0;`
369			`LCD_E <= mylcd_LCD_E0;`
370			`end`
371			`end`
372
373
374			`assign mylcd_tx_init = ((~mylcd_tx_done) & ((mylcd_state == 5'b01010) \| (mylcd_state == 5'b01011) \| (mylcd_state == 5'b01100) \| (mylcd_state == 5'b01101) \| (mylcd_state == 5'b10001) \| (mylcd_state == 5'b10010)));`
375			`assign LCD_RS = (~(((mylcd_state == 5'b01010) != 0) \| (mylcd_state == 5'b01011) \| (mylcd_state == 5'b01100) \| (mylcd_state == 5'b01101) \| (mylcd_state == 5'b10001)));`
376
377
378			`assign mylcd_delay_done = (mylcd_counter_counter == 0);`
379
380			`always @(posedge wb_clk_i) begin: WB_LCD_MYLCD_COUNTER_COUNTDOWN_LOGIC`
381			`if (mylcd_delay_load) begin`
382			`mylcd_counter_counter <= mylcd_delay_value;`
383			`end`
384			`else begin`
385			`mylcd_counter_counter <= (mylcd_counter_counter - 1);`
386			`end`
387			`end`
388
389			`endmodule`