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[/] [wb_lcd/] [trunk/] [verilog/] [wb_lcd/] [boards/] [s3esk-wb_lcd/] [rtl/] [glbl.v] - Blame information for rev 2

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Line No. Rev Author Line
1 2 jvillar
`timescale  1 ns / 1 ps
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module glbl ();
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    wire GR;
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    wire GSR;
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    wire GTS;
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    wire PRLD;
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endmodule

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