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[/] [wb_lcd/] [trunk/] [verilog/] [wb_lcd/] [boards/] [s3esk-wb_lcd/] [rtl/] [system_sim.v] - Blame information for rev 2

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1 2 jvillar
//////////////////////////////////////////////////////////////////////
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////                                                              ////
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////  system_sim.v                                                ////
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////                                                              ////
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////  This file is part of:                                       ////
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////  WISHBONE/MEM MAPPED CONTROLLER FOR LCD CHARACTER DISPLAYS   ////
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////  http://www.opencores.org/projects/wb_lcd/                   ////
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////                                                              ////
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////  Description                                                 ////
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////   - Simulation testbench for SPARTAN-3E STARTER KIT          ////
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////     clock and reset.                                         ////
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////  To Do:                                                      ////
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////   - nothing really                                           ////
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////                                                              ////
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////  Author(s):                                                  ////
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////   - José Ignacio Villar, jose@dte.us.es , jvillar@gmail.com  ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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////                                                              ////
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//// Copyright (C) 2009 José Ignacio Villar - jvillar@gmail.com   ////
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////                                                              ////
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//// This source file may be used and distributed without         ////
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//// restriction provided that this copyright statement is not    ////
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//// removed from the file and that any derivative work contains  ////
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//// the original copyright notice and the associated disclaimer. ////
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////                                                              ////
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//// This source file is free software; you can redistribute it   ////
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//// and/or modify it under the terms of the GNU Lesser General   ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 3 of the License, or (at your option) any     ////
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//// later version.                                               ////
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////                                                              ////
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//// This source is distributed in the hope that it will be       ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
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//// PURPOSE.  See the GNU Lesser General Public License for more ////
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//// details.                                                     ////
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////                                                              ////
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//// You should have received a copy of the GNU Lesser General    ////
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//// Public License along with this source; if not, download it   ////
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//// from http://www.gnu.org/licenses/lgpl.txt                    ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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`include "lcd_defines.v"
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//----------------------------------------------------------------------------
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// Simulation testbench for SPARTAN-3E STARTER KIT clock and reset
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//----------------------------------------------------------------------------
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`timescale 1ns / 1ps
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module system_sim;
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reg clk = 0;
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reg reset = 1;
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//----------------------------------------------------------------------------
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// Memory-Tester System
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//----------------------------------------------------------------------------
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system dut (
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      .clk   ( clk   ),
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      .reset   ( reset )
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);
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//----------------------------------------------------------------------------
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// Clock Generation (50 MHZ)
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//----------------------------------------------------------------------------
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initial clk <= 1'b0;
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always #10 clk <=  ~clk;
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//----------------------------------------------------------------------------
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// Reset Generation
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//----------------------------------------------------------------------------
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initial begin
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        $dumpfile("system_sim.vcd");
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        $dumpvars;
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        #0       reset <= 1'b1;
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        #80      reset <= 1'b0;
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//      #10000000000  $finish;
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end
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endmodule
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// vim: set ts=4

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