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////////////////////////////////////////////////////////////////////////////////
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//
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// Filename: pdmdemo.cpp
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//
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// Project: A Wishbone Controlled PWM (audio) controller
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//
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// Purpose: A Verilator driver to demonstrate, off-line, if the PDM
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// approach used by wbpwmaudio works.
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//
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// Creator: Dan Gisselquist, Ph.D.
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// Gisselquist Technology, LLC
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//
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////////////////////////////////////////////////////////////////////////////////
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//
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// Copyright (C) 2015-2017, Gisselquist Technology, LLC
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//
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// This program is free software (firmware): you can redistribute it and/or
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// modify it under the terms of the GNU General Public License as published
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// by the Free Software Foundation, either version 3 of the License, or (at
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// your option) any later version.
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//
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// This program is distributed in the hope that it will be useful, but WITHOUT
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// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
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// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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// for more details.
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//
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// You should have received a copy of the GNU General Public License along
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// with this program. (It's in the $(ROOT)/doc directory. Run make with no
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// target there if the PDF file isn't present.) If not, see
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// <http://www.gnu.org/licenses/> for a copy.
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//
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// License: GPL, v3, as defined and found on www.gnu.org,
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// http://www.gnu.org/licenses/gpl.html
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//
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//
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////////////////////////////////////////////////////////////////////////////////
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//
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//
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#include <stdio.h>
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#include <math.h>
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#include <verilated.h>
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#include <verilated_vcd_c.h>
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#include "Vtoplevel.h"
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#include "testb.h"
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// Verilator changed their naming convention somewhere around version 3.9 or
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// so.
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#ifdef NEW_VERILATOR
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#define seq_step toplevel__DOT__seq_step
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#else
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#define seq_step v__DOT__seq_step
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#endif
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#define CLOCK_RATE_HZ 100000000 // FPGA clock rate
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#define SAMPLE_RATE_HZ 44100 // Our output (generated) sample rate
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#define AUDIO_TOP_HZ 22000 // The filter's cutoff frequency
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//
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// We are going to use an overkill filter, generated via the crude manner of
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// windowing an "ideal" filter. ("ideal" filters are never "ideal" ... but
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// that's beside the point.) The problem with this is that the filter has
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// arbitrarily way too many taps. Hence, we'll use a filter with FIRLEN
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// taps and leave examples with fewer taps for any paying customers.
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const int FIRLEN = 65536*8;
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//
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// class PDMDEMO is a wrapper class around the Verilator generated simulation
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// component.
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//
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class PDMDEMO : public TESTB<Vtoplevel> {
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// Resampling filter taps
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double *m_taps;
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// Resampler variables, telling us when to produce the next output
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double m_subsample, m_step;
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// The file to place these values into
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FILE *m_wavfp;
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// Filter memory
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int *m_firmem, m_firpos;
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public:
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PDMDEMO(void) {
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// Our filter cutoff
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const double fc = (double)AUDIO_TOP_HZ
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/ (double)CLOCK_RATE_HZ;
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// Allocate memory for taps and data values
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m_taps = new double[FIRLEN];
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m_firmem = new int[FIRLEN];
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m_firpos = 0;
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for(int i=0; i<FIRLEN; i++) {
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double window, t;
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m_firmem[i] = 0;
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// Blackman Window --- see Oppenheim and Schafer
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// for more info.
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t = (i+1.0)/(FIRLEN+1.0);
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window = 0.42
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-0.50 * cos(2.0*M_PI*t)
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+0.08 * cos(4.0*M_PI*t);
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// An "ideal" lowpass filter, with cutoff at fc
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// (fc is in units of normalized frequency)
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t = (i+1.0-FIRLEN/2);
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m_taps[i] = sin(2.0 * M_PI * fc * t) / (M_PI * t);
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// Apply the window to the filter tap
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m_taps[i] *= window;
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}
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// We'll set the middle tap special, since sin(x)/x isn't
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// known for its convergence when x=0.
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m_taps[FIRLEN/2-1] = fc;
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// In case you'd like to look at this filter, we'll dump its
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// taps to a file.
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m_wavfp = fopen("filter.dbl","w");
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fwrite(m_taps, sizeof(m_taps[0]), FIRLEN, m_wavfp);
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fclose(m_wavfp);
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// Otherwise, everything is going to be dumped to the
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// wavfp.dbl file.
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m_wavfp = fopen("wavfp.dbl","w");
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// Initialize the values we need to use for determining our
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// resample clock.
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m_subsample = 0.0;
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m_step = (double)SAMPLE_RATE_HZ / (double)CLOCK_RATE_HZ;
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}
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~PDMDEMO(void) {
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// Close our output waveform file
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if (m_wavfp)
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fclose(m_wavfp);
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}
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void tick(void) {
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int output;
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// Tick the clock.
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TESTB<Vtoplevel>::tick();
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// Examine the output
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output = TESTB<Vtoplevel>::m_core->o_pwm;
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// If we are writing to an output file (should always be true)
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// then ...
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if (m_wavfp) {
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// Turn this output into a "voltage" centered upon
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// zero. If the output is not shutdown, the voltage
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// will be dependent upon the pins value, and will
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// either be +/- one. Otherwise, we'll just output a
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// zero value.
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if (m_core->o_shutdown_n)
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output = 2*m_core->o_pwm - 1;
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else
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output = 0;
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// Add this value to our filter memory, and adjust the
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// pointer to the oldest sample in memory.
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m_firmem[m_firpos++] = output;
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if (m_firpos >= FIRLEN)
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m_firpos = 0;
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// If it's time to run the filter to calculate a result,
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// ...
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m_subsample += m_step;
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if (m_subsample >= 1.0) {
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// Then apply the taps from the filter to our
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// data smaples. Note that there will be some
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// amount of phase noise from using this
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// approach, since it essentially amounts to
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// applying a filter to get an instantaneous
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// output and then using a nearest neighbour
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// interpolator---rather than properly
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// getting any subsample resolution.
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//
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// For our purposes today, this should be good
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// enough.
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double acc = 0.0;
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// First run through memory from the oldest
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// value until the end of the buffer
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for(int i=0; i+m_firpos < FIRLEN; i++)
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acc += m_taps[i] * m_firmem[m_firpos+i];
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// Then continue from the beginning of the
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// buffer to the most recent value.
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for(int i=FIRLEN-m_firpos; i < FIRLEN; i++)
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acc += m_taps[i] * m_firmem[m_firpos+i-FIRLEN];
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// Write the output out into a file.
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// The value is of type double.
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fwrite(&acc, sizeof(double), 1, m_wavfp);
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// Set us up to calculate when the next
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// sample will be at this rate.
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m_subsample -= 1.0;
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}
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}
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}
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};
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int main(int argc, char **argv) {
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Verilated::commandArgs(argc, argv);
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// Create a class containing our design
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PDMDEMO *tb = new PDMDEMO;
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// This should really be a command line parameter ...
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// Adjust this value to true to produce a traditional PWM output, false
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// to produce the "improved" PDM output.
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const bool traditional_pwm = true;
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printf("\n\n");
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if (traditional_pwm) {
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printf("Creating the output for a traditional PWM\n");
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tb->m_core->i_sw = 0;
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} else {
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printf("Creating the output for the modified/improved PDM\n");
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tb->m_core->i_sw = 1;
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}
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printf("\n\n");
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// If you want to see a trace from this run, then uncomment the line
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// below. Be aware, the trace file can quickly become many GB in
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// length!
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//
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// tb->opentrace("pdmdemo.vcd");
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//
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// Simulate ten seconds of our waveform generator
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for(int k=0; k< 10 * CLOCK_RATE_HZ; k++) {
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// Just so we believe its doing something, let's output
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// what step we are on, and what frequency is going into the
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// frequency generator.
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if ((k % (CLOCK_RATE_HZ/1000))==0) {
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double secs = k / (double)CLOCK_RATE_HZ;
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if (tb->m_core->o_shutdown_n) {
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double f = tb->m_core->seq_step;
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f = f * CLOCK_RATE_HZ / pow(2,34);
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printf("k = %10d clocks, %5.2f secs, f = %8.1f Hz\n", k, secs, f);
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} else
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printf("k = %10d clocks, %5.2f secs\n", k, secs);
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}
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// Step the simulation forward by a single clock tick
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tb->tick();
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}
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// Now that we're all done, delete the simulation and exit
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delete tb;
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exit(EXIT_SUCCESS);
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}
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