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dgisselq |
# A Wishbone Controlled Scope for FPGA's
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This is a generic/library routine for providing a bus accessed 'scope' or
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(perhaps more appropriately) a bus accessed logic analyzer for use internal to
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an FPGA. The general operation is such that this 'scope' can record and report
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on any 32 bit value transiting through the FPGA. Once started and reset, the
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scope records a copy of the input data every time the clock ticks with the
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circuit enabled. That is, it records these values up until the trigger. Once
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the trigger goes high, the scope will record for ``bw_holdoff`` more counts
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before stopping. Values may then be read from the buffer, oldest to most
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recent. After reading, the scope may then be reset for another run.
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In general, therefore, operation happens in this fashion:
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1. A reset is issued.
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2. Recording starts, in a circular buffer, and continues until
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3. The trigger line is asserted.
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The scope registers the asserted trigger by setting the ``o_triggered`` output flag.
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4. A counter then ticks until the last value is written.
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The scope registers that it has stopped recording by setting the ``o_stopped`` output flag.
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5. The scope recording is then paused until the next reset.
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6. While stopped, the CPU can read the data from the scope
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- oldest to most recent
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- one value per bus clock
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7. Writes to the data register reset the address to the beginning of the buffer
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# Commercial Applications
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Should you find the GPLv3 license insufficient for your needs, other licenses
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can be purchased from Gisselquist Technology, LLC.
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