1 |
17 |
jeaander |
|wiegand_tx_top
|
2 |
|
|
one_o <= one_o~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
3 |
|
|
zero_o <= zero_o~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
4 |
|
|
wb_clk_i => wb_clk_i.IN1
|
5 |
|
|
wb_rst_i => wb_rst_i.IN1
|
6 |
|
|
wb_dat_i[0] => wb_dat_i[0].IN1
|
7 |
|
|
wb_dat_i[1] => wb_dat_i[1].IN1
|
8 |
|
|
wb_dat_i[2] => wb_dat_i[2].IN1
|
9 |
|
|
wb_dat_i[3] => wb_dat_i[3].IN1
|
10 |
|
|
wb_dat_i[4] => wb_dat_i[4].IN1
|
11 |
|
|
wb_dat_i[5] => wb_dat_i[5].IN1
|
12 |
|
|
wb_dat_i[6] => wb_dat_i[6].IN1
|
13 |
|
|
wb_dat_i[7] => wb_dat_i[7].IN1
|
14 |
|
|
wb_dat_i[8] => wb_dat_i[8].IN1
|
15 |
|
|
wb_dat_i[9] => wb_dat_i[9].IN1
|
16 |
|
|
wb_dat_i[10] => wb_dat_i[10].IN1
|
17 |
|
|
wb_dat_i[11] => wb_dat_i[11].IN1
|
18 |
|
|
wb_dat_i[12] => wb_dat_i[12].IN1
|
19 |
|
|
wb_dat_i[13] => wb_dat_i[13].IN1
|
20 |
|
|
wb_dat_i[14] => wb_dat_i[14].IN1
|
21 |
|
|
wb_dat_i[15] => wb_dat_i[15].IN1
|
22 |
|
|
wb_dat_i[16] => wb_dat_i[16].IN1
|
23 |
|
|
wb_dat_i[17] => wb_dat_i[17].IN1
|
24 |
|
|
wb_dat_i[18] => wb_dat_i[18].IN1
|
25 |
|
|
wb_dat_i[19] => wb_dat_i[19].IN1
|
26 |
|
|
wb_dat_i[20] => wb_dat_i[20].IN1
|
27 |
|
|
wb_dat_i[21] => wb_dat_i[21].IN1
|
28 |
|
|
wb_dat_i[22] => wb_dat_i[22].IN1
|
29 |
|
|
wb_dat_i[23] => wb_dat_i[23].IN1
|
30 |
|
|
wb_dat_i[24] => wb_dat_i[24].IN1
|
31 |
|
|
wb_dat_i[25] => wb_dat_i[25].IN1
|
32 |
|
|
wb_dat_i[26] => wb_dat_i[26].IN1
|
33 |
|
|
wb_dat_i[27] => wb_dat_i[27].IN1
|
34 |
|
|
wb_dat_i[28] => wb_dat_i[28].IN1
|
35 |
|
|
wb_dat_i[29] => wb_dat_i[29].IN1
|
36 |
|
|
wb_dat_i[30] => wb_dat_i[30].IN1
|
37 |
|
|
wb_dat_i[31] => wb_dat_i[31].IN1
|
38 |
|
|
wb_dat_o[0] <= wb_interface_wieg:wb_interface.port8
|
39 |
|
|
wb_dat_o[1] <= wb_interface_wieg:wb_interface.port8
|
40 |
|
|
wb_dat_o[2] <= wb_interface_wieg:wb_interface.port8
|
41 |
|
|
wb_dat_o[3] <= wb_interface_wieg:wb_interface.port8
|
42 |
|
|
wb_dat_o[4] <= wb_interface_wieg:wb_interface.port8
|
43 |
|
|
wb_dat_o[5] <= wb_interface_wieg:wb_interface.port8
|
44 |
|
|
wb_dat_o[6] <= wb_interface_wieg:wb_interface.port8
|
45 |
|
|
wb_dat_o[7] <= wb_interface_wieg:wb_interface.port8
|
46 |
|
|
wb_dat_o[8] <= wb_interface_wieg:wb_interface.port8
|
47 |
|
|
wb_dat_o[9] <= wb_interface_wieg:wb_interface.port8
|
48 |
|
|
wb_dat_o[10] <= wb_interface_wieg:wb_interface.port8
|
49 |
|
|
wb_dat_o[11] <= wb_interface_wieg:wb_interface.port8
|
50 |
|
|
wb_dat_o[12] <= wb_interface_wieg:wb_interface.port8
|
51 |
|
|
wb_dat_o[13] <= wb_interface_wieg:wb_interface.port8
|
52 |
|
|
wb_dat_o[14] <= wb_interface_wieg:wb_interface.port8
|
53 |
|
|
wb_dat_o[15] <= wb_interface_wieg:wb_interface.port8
|
54 |
|
|
wb_dat_o[16] <= wb_interface_wieg:wb_interface.port8
|
55 |
|
|
wb_dat_o[17] <= wb_interface_wieg:wb_interface.port8
|
56 |
|
|
wb_dat_o[18] <= wb_interface_wieg:wb_interface.port8
|
57 |
|
|
wb_dat_o[19] <= wb_interface_wieg:wb_interface.port8
|
58 |
|
|
wb_dat_o[20] <= wb_interface_wieg:wb_interface.port8
|
59 |
|
|
wb_dat_o[21] <= wb_interface_wieg:wb_interface.port8
|
60 |
|
|
wb_dat_o[22] <= wb_interface_wieg:wb_interface.port8
|
61 |
|
|
wb_dat_o[23] <= wb_interface_wieg:wb_interface.port8
|
62 |
|
|
wb_dat_o[24] <= wb_interface_wieg:wb_interface.port8
|
63 |
|
|
wb_dat_o[25] <= wb_interface_wieg:wb_interface.port8
|
64 |
|
|
wb_dat_o[26] <= wb_interface_wieg:wb_interface.port8
|
65 |
|
|
wb_dat_o[27] <= wb_interface_wieg:wb_interface.port8
|
66 |
|
|
wb_dat_o[28] <= wb_interface_wieg:wb_interface.port8
|
67 |
|
|
wb_dat_o[29] <= wb_interface_wieg:wb_interface.port8
|
68 |
|
|
wb_dat_o[30] <= wb_interface_wieg:wb_interface.port8
|
69 |
|
|
wb_dat_o[31] <= wb_interface_wieg:wb_interface.port8
|
70 |
|
|
wb_cyc_i => wb_cyc_i.IN1
|
71 |
|
|
wb_stb_i => wb_stb_i.IN1
|
72 |
|
|
wb_cti_i[0] => wb_cti_i[0].IN1
|
73 |
|
|
wb_cti_i[1] => wb_cti_i[1].IN1
|
74 |
|
|
wb_cti_i[2] => wb_cti_i[2].IN1
|
75 |
|
|
wb_sel_i[0] => wb_sel_i[0].IN1
|
76 |
|
|
wb_sel_i[1] => wb_sel_i[1].IN1
|
77 |
|
|
wb_sel_i[2] => wb_sel_i[2].IN1
|
78 |
|
|
wb_sel_i[3] => wb_sel_i[3].IN1
|
79 |
|
|
wb_we_i => wb_we_i.IN1
|
80 |
|
|
wb_adr_i[0] => wb_adr_i[0].IN1
|
81 |
|
|
wb_adr_i[1] => wb_adr_i[1].IN1
|
82 |
|
|
wb_adr_i[2] => wb_adr_i[2].IN1
|
83 |
|
|
wb_adr_i[3] => wb_adr_i[3].IN1
|
84 |
|
|
wb_adr_i[4] => wb_adr_i[4].IN1
|
85 |
|
|
wb_adr_i[5] => wb_adr_i[5].IN1
|
86 |
|
|
wb_ack_o <= wb_interface_wieg:wb_interface.port3
|
87 |
|
|
wb_err_o <= wb_interface_wieg:wb_interface.port11
|
88 |
|
|
wb_rty_o <= wb_interface_wieg:wb_interface.port12
|
89 |
|
|
|
90 |
|
|
|
91 |
|
|
|wiegand_tx_top|fifo_wieg:datafifowrite
|
92 |
|
|
clk_rd => clk_rd.IN4
|
93 |
|
|
clk_wr => clk_wr.IN4
|
94 |
|
|
d_i[0] => d_i[0].IN1
|
95 |
|
|
d_i[1] => d_i[1].IN1
|
96 |
|
|
d_i[2] => d_i[2].IN1
|
97 |
|
|
d_i[3] => d_i[3].IN1
|
98 |
|
|
d_i[4] => d_i[4].IN1
|
99 |
|
|
d_i[5] => d_i[5].IN1
|
100 |
|
|
d_i[6] => d_i[6].IN1
|
101 |
|
|
d_i[7] => d_i[7].IN1
|
102 |
|
|
d_i[8] => d_i[8].IN1
|
103 |
|
|
d_i[9] => d_i[9].IN1
|
104 |
|
|
d_i[10] => d_i[10].IN1
|
105 |
|
|
d_i[11] => d_i[11].IN1
|
106 |
|
|
d_i[12] => d_i[12].IN1
|
107 |
|
|
d_i[13] => d_i[13].IN1
|
108 |
|
|
d_i[14] => d_i[14].IN1
|
109 |
|
|
d_i[15] => d_i[15].IN1
|
110 |
|
|
d_i[16] => d_i[16].IN1
|
111 |
|
|
d_i[17] => d_i[17].IN1
|
112 |
|
|
d_i[18] => d_i[18].IN1
|
113 |
|
|
d_i[19] => d_i[19].IN1
|
114 |
|
|
d_i[20] => d_i[20].IN1
|
115 |
|
|
d_i[21] => d_i[21].IN1
|
116 |
|
|
d_i[22] => d_i[22].IN1
|
117 |
|
|
d_i[23] => d_i[23].IN1
|
118 |
|
|
d_i[24] => d_i[24].IN1
|
119 |
|
|
d_i[25] => d_i[25].IN1
|
120 |
|
|
d_i[26] => d_i[26].IN1
|
121 |
|
|
d_i[27] => d_i[27].IN1
|
122 |
|
|
d_i[28] => d_i[28].IN1
|
123 |
|
|
d_i[29] => d_i[29].IN1
|
124 |
|
|
d_i[30] => d_i[30].IN1
|
125 |
|
|
d_i[31] => d_i[31].IN1
|
126 |
|
|
d_o[0] <= custom_fifo_dp:custom_fifo_dp8.port3
|
127 |
|
|
d_o[1] <= custom_fifo_dp:custom_fifo_dp8.port3
|
128 |
|
|
d_o[2] <= custom_fifo_dp:custom_fifo_dp8.port3
|
129 |
|
|
d_o[3] <= custom_fifo_dp:custom_fifo_dp8.port3
|
130 |
|
|
d_o[4] <= custom_fifo_dp:custom_fifo_dp8.port3
|
131 |
|
|
d_o[5] <= custom_fifo_dp:custom_fifo_dp8.port3
|
132 |
|
|
d_o[6] <= custom_fifo_dp:custom_fifo_dp8.port3
|
133 |
|
|
d_o[7] <= custom_fifo_dp:custom_fifo_dp8.port3
|
134 |
|
|
d_o[8] <= custom_fifo_dp:custom_fifo_dp7.port3
|
135 |
|
|
d_o[9] <= custom_fifo_dp:custom_fifo_dp7.port3
|
136 |
|
|
d_o[10] <= custom_fifo_dp:custom_fifo_dp7.port3
|
137 |
|
|
d_o[11] <= custom_fifo_dp:custom_fifo_dp7.port3
|
138 |
|
|
d_o[12] <= custom_fifo_dp:custom_fifo_dp7.port3
|
139 |
|
|
d_o[13] <= custom_fifo_dp:custom_fifo_dp7.port3
|
140 |
|
|
d_o[14] <= custom_fifo_dp:custom_fifo_dp7.port3
|
141 |
|
|
d_o[15] <= custom_fifo_dp:custom_fifo_dp7.port3
|
142 |
|
|
d_o[16] <= custom_fifo_dp:custom_fifo_dp6.port3
|
143 |
|
|
d_o[17] <= custom_fifo_dp:custom_fifo_dp6.port3
|
144 |
|
|
d_o[18] <= custom_fifo_dp:custom_fifo_dp6.port3
|
145 |
|
|
d_o[19] <= custom_fifo_dp:custom_fifo_dp6.port3
|
146 |
|
|
d_o[20] <= custom_fifo_dp:custom_fifo_dp6.port3
|
147 |
|
|
d_o[21] <= custom_fifo_dp:custom_fifo_dp6.port3
|
148 |
|
|
d_o[22] <= custom_fifo_dp:custom_fifo_dp6.port3
|
149 |
|
|
d_o[23] <= custom_fifo_dp:custom_fifo_dp6.port3
|
150 |
|
|
d_o[24] <= custom_fifo_dp:custom_fifo_dp5.port3
|
151 |
|
|
d_o[25] <= custom_fifo_dp:custom_fifo_dp5.port3
|
152 |
|
|
d_o[26] <= custom_fifo_dp:custom_fifo_dp5.port3
|
153 |
|
|
d_o[27] <= custom_fifo_dp:custom_fifo_dp5.port3
|
154 |
|
|
d_o[28] <= custom_fifo_dp:custom_fifo_dp5.port3
|
155 |
|
|
d_o[29] <= custom_fifo_dp:custom_fifo_dp5.port3
|
156 |
|
|
d_o[30] <= custom_fifo_dp:custom_fifo_dp5.port3
|
157 |
|
|
d_o[31] <= custom_fifo_dp:custom_fifo_dp5.port3
|
158 |
|
|
rst => rst.IN4
|
159 |
|
|
wr_en => wr_en.IN4
|
160 |
|
|
rd_en => rd_en.IN4
|
161 |
|
|
full <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
|
162 |
|
|
empty <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
|
163 |
|
|
|
164 |
|
|
|
165 |
|
|
|wiegand_tx_top|fifo_wieg:datafifowrite|custom_fifo_dp:custom_fifo_dp5
|
166 |
|
|
clk_rd => addr_rd[0].CLK
|
167 |
|
|
clk_rd => addr_rd[1].CLK
|
168 |
|
|
clk_rd => addr_rd[2].CLK
|
169 |
|
|
clk_rd => fifo_out[0].CLK
|
170 |
|
|
clk_rd => fifo_out[1].CLK
|
171 |
|
|
clk_rd => fifo_out[2].CLK
|
172 |
|
|
clk_rd => fifo_out[3].CLK
|
173 |
|
|
clk_rd => fifo_out[4].CLK
|
174 |
|
|
clk_rd => fifo_out[5].CLK
|
175 |
|
|
clk_rd => fifo_out[6].CLK
|
176 |
|
|
clk_rd => fifo_out[7].CLK
|
177 |
|
|
clk_wr => clk_wr.IN3
|
178 |
|
|
d_i[0] => d_i[0].IN3
|
179 |
|
|
d_i[1] => d_i[1].IN3
|
180 |
|
|
d_i[2] => d_i[2].IN3
|
181 |
|
|
d_i[3] => d_i[3].IN3
|
182 |
|
|
d_i[4] => d_i[4].IN3
|
183 |
|
|
d_i[5] => d_i[5].IN3
|
184 |
|
|
d_i[6] => d_i[6].IN3
|
185 |
|
|
d_i[7] => d_i[7].IN3
|
186 |
|
|
d_o[0] <= fifo_out[0].DB_MAX_OUTPUT_PORT_TYPE
|
187 |
|
|
d_o[1] <= fifo_out[1].DB_MAX_OUTPUT_PORT_TYPE
|
188 |
|
|
d_o[2] <= fifo_out[2].DB_MAX_OUTPUT_PORT_TYPE
|
189 |
|
|
d_o[3] <= fifo_out[3].DB_MAX_OUTPUT_PORT_TYPE
|
190 |
|
|
d_o[4] <= fifo_out[4].DB_MAX_OUTPUT_PORT_TYPE
|
191 |
|
|
d_o[5] <= fifo_out[5].DB_MAX_OUTPUT_PORT_TYPE
|
192 |
|
|
d_o[6] <= fifo_out[6].DB_MAX_OUTPUT_PORT_TYPE
|
193 |
|
|
d_o[7] <= fifo_out[7].DB_MAX_OUTPUT_PORT_TYPE
|
194 |
|
|
rst => rst.IN3
|
195 |
|
|
wr_en => always1.IN1
|
196 |
|
|
rd_en => always2.IN1
|
197 |
|
|
full <= full.DB_MAX_OUTPUT_PORT_TYPE
|
198 |
|
|
empty <= Equal0.DB_MAX_OUTPUT_PORT_TYPE
|
199 |
|
|
|
200 |
|
|
|
201 |
|
|
|wiegand_tx_top|fifo_wieg:datafifowrite|custom_fifo_dp:custom_fifo_dp5|mem_byte:mem[0].mem_byte
|
202 |
|
|
rst => byte_reg[0].ACLR
|
203 |
|
|
rst => byte_reg[1].ACLR
|
204 |
|
|
rst => byte_reg[2].ACLR
|
205 |
|
|
rst => byte_reg[3].ACLR
|
206 |
|
|
rst => byte_reg[4].ACLR
|
207 |
|
|
rst => byte_reg[5].ACLR
|
208 |
|
|
rst => byte_reg[6].ACLR
|
209 |
|
|
rst => byte_reg[7].ACLR
|
210 |
|
|
clk => byte_reg[0].CLK
|
211 |
|
|
clk => byte_reg[1].CLK
|
212 |
|
|
clk => byte_reg[2].CLK
|
213 |
|
|
clk => byte_reg[3].CLK
|
214 |
|
|
clk => byte_reg[4].CLK
|
215 |
|
|
clk => byte_reg[5].CLK
|
216 |
|
|
clk => byte_reg[6].CLK
|
217 |
|
|
clk => byte_reg[7].CLK
|
218 |
|
|
din[0] => byte_reg[0].DATAIN
|
219 |
|
|
din[1] => byte_reg[1].DATAIN
|
220 |
|
|
din[2] => byte_reg[2].DATAIN
|
221 |
|
|
din[3] => byte_reg[3].DATAIN
|
222 |
|
|
din[4] => byte_reg[4].DATAIN
|
223 |
|
|
din[5] => byte_reg[5].DATAIN
|
224 |
|
|
din[6] => byte_reg[6].DATAIN
|
225 |
|
|
din[7] => byte_reg[7].DATAIN
|
226 |
|
|
dout[0] <= dout[0].DB_MAX_OUTPUT_PORT_TYPE
|
227 |
|
|
dout[1] <= dout[1].DB_MAX_OUTPUT_PORT_TYPE
|
228 |
|
|
dout[2] <= dout[2].DB_MAX_OUTPUT_PORT_TYPE
|
229 |
|
|
dout[3] <= dout[3].DB_MAX_OUTPUT_PORT_TYPE
|
230 |
|
|
dout[4] <= dout[4].DB_MAX_OUTPUT_PORT_TYPE
|
231 |
|
|
dout[5] <= dout[5].DB_MAX_OUTPUT_PORT_TYPE
|
232 |
|
|
dout[6] <= dout[6].DB_MAX_OUTPUT_PORT_TYPE
|
233 |
|
|
dout[7] <= dout[7].DB_MAX_OUTPUT_PORT_TYPE
|
234 |
|
|
wen => byte_reg[7].ENA
|
235 |
|
|
wen => byte_reg[6].ENA
|
236 |
|
|
wen => byte_reg[5].ENA
|
237 |
|
|
wen => byte_reg[4].ENA
|
238 |
|
|
wen => byte_reg[3].ENA
|
239 |
|
|
wen => byte_reg[2].ENA
|
240 |
|
|
wen => byte_reg[1].ENA
|
241 |
|
|
wen => byte_reg[0].ENA
|
242 |
|
|
ren => dout[0].OE
|
243 |
|
|
ren => dout[1].OE
|
244 |
|
|
ren => dout[2].OE
|
245 |
|
|
ren => dout[3].OE
|
246 |
|
|
ren => dout[4].OE
|
247 |
|
|
ren => dout[5].OE
|
248 |
|
|
ren => dout[6].OE
|
249 |
|
|
ren => dout[7].OE
|
250 |
|
|
|
251 |
|
|
|
252 |
|
|
|wiegand_tx_top|fifo_wieg:datafifowrite|custom_fifo_dp:custom_fifo_dp5|mem_byte:mem[1].mem_byte
|
253 |
|
|
rst => byte_reg[0].ACLR
|
254 |
|
|
rst => byte_reg[1].ACLR
|
255 |
|
|
rst => byte_reg[2].ACLR
|
256 |
|
|
rst => byte_reg[3].ACLR
|
257 |
|
|
rst => byte_reg[4].ACLR
|
258 |
|
|
rst => byte_reg[5].ACLR
|
259 |
|
|
rst => byte_reg[6].ACLR
|
260 |
|
|
rst => byte_reg[7].ACLR
|
261 |
|
|
clk => byte_reg[0].CLK
|
262 |
|
|
clk => byte_reg[1].CLK
|
263 |
|
|
clk => byte_reg[2].CLK
|
264 |
|
|
clk => byte_reg[3].CLK
|
265 |
|
|
clk => byte_reg[4].CLK
|
266 |
|
|
clk => byte_reg[5].CLK
|
267 |
|
|
clk => byte_reg[6].CLK
|
268 |
|
|
clk => byte_reg[7].CLK
|
269 |
|
|
din[0] => byte_reg[0].DATAIN
|
270 |
|
|
din[1] => byte_reg[1].DATAIN
|
271 |
|
|
din[2] => byte_reg[2].DATAIN
|
272 |
|
|
din[3] => byte_reg[3].DATAIN
|
273 |
|
|
din[4] => byte_reg[4].DATAIN
|
274 |
|
|
din[5] => byte_reg[5].DATAIN
|
275 |
|
|
din[6] => byte_reg[6].DATAIN
|
276 |
|
|
din[7] => byte_reg[7].DATAIN
|
277 |
|
|
dout[0] <= dout[0].DB_MAX_OUTPUT_PORT_TYPE
|
278 |
|
|
dout[1] <= dout[1].DB_MAX_OUTPUT_PORT_TYPE
|
279 |
|
|
dout[2] <= dout[2].DB_MAX_OUTPUT_PORT_TYPE
|
280 |
|
|
dout[3] <= dout[3].DB_MAX_OUTPUT_PORT_TYPE
|
281 |
|
|
dout[4] <= dout[4].DB_MAX_OUTPUT_PORT_TYPE
|
282 |
|
|
dout[5] <= dout[5].DB_MAX_OUTPUT_PORT_TYPE
|
283 |
|
|
dout[6] <= dout[6].DB_MAX_OUTPUT_PORT_TYPE
|
284 |
|
|
dout[7] <= dout[7].DB_MAX_OUTPUT_PORT_TYPE
|
285 |
|
|
wen => byte_reg[7].ENA
|
286 |
|
|
wen => byte_reg[6].ENA
|
287 |
|
|
wen => byte_reg[5].ENA
|
288 |
|
|
wen => byte_reg[4].ENA
|
289 |
|
|
wen => byte_reg[3].ENA
|
290 |
|
|
wen => byte_reg[2].ENA
|
291 |
|
|
wen => byte_reg[1].ENA
|
292 |
|
|
wen => byte_reg[0].ENA
|
293 |
|
|
ren => dout[0].OE
|
294 |
|
|
ren => dout[1].OE
|
295 |
|
|
ren => dout[2].OE
|
296 |
|
|
ren => dout[3].OE
|
297 |
|
|
ren => dout[4].OE
|
298 |
|
|
ren => dout[5].OE
|
299 |
|
|
ren => dout[6].OE
|
300 |
|
|
ren => dout[7].OE
|
301 |
|
|
|
302 |
|
|
|
303 |
|
|
|wiegand_tx_top|fifo_wieg:datafifowrite|custom_fifo_dp:custom_fifo_dp5|mem_byte:mem[2].mem_byte
|
304 |
|
|
rst => byte_reg[0].ACLR
|
305 |
|
|
rst => byte_reg[1].ACLR
|
306 |
|
|
rst => byte_reg[2].ACLR
|
307 |
|
|
rst => byte_reg[3].ACLR
|
308 |
|
|
rst => byte_reg[4].ACLR
|
309 |
|
|
rst => byte_reg[5].ACLR
|
310 |
|
|
rst => byte_reg[6].ACLR
|
311 |
|
|
rst => byte_reg[7].ACLR
|
312 |
|
|
clk => byte_reg[0].CLK
|
313 |
|
|
clk => byte_reg[1].CLK
|
314 |
|
|
clk => byte_reg[2].CLK
|
315 |
|
|
clk => byte_reg[3].CLK
|
316 |
|
|
clk => byte_reg[4].CLK
|
317 |
|
|
clk => byte_reg[5].CLK
|
318 |
|
|
clk => byte_reg[6].CLK
|
319 |
|
|
clk => byte_reg[7].CLK
|
320 |
|
|
din[0] => byte_reg[0].DATAIN
|
321 |
|
|
din[1] => byte_reg[1].DATAIN
|
322 |
|
|
din[2] => byte_reg[2].DATAIN
|
323 |
|
|
din[3] => byte_reg[3].DATAIN
|
324 |
|
|
din[4] => byte_reg[4].DATAIN
|
325 |
|
|
din[5] => byte_reg[5].DATAIN
|
326 |
|
|
din[6] => byte_reg[6].DATAIN
|
327 |
|
|
din[7] => byte_reg[7].DATAIN
|
328 |
|
|
dout[0] <= dout[0].DB_MAX_OUTPUT_PORT_TYPE
|
329 |
|
|
dout[1] <= dout[1].DB_MAX_OUTPUT_PORT_TYPE
|
330 |
|
|
dout[2] <= dout[2].DB_MAX_OUTPUT_PORT_TYPE
|
331 |
|
|
dout[3] <= dout[3].DB_MAX_OUTPUT_PORT_TYPE
|
332 |
|
|
dout[4] <= dout[4].DB_MAX_OUTPUT_PORT_TYPE
|
333 |
|
|
dout[5] <= dout[5].DB_MAX_OUTPUT_PORT_TYPE
|
334 |
|
|
dout[6] <= dout[6].DB_MAX_OUTPUT_PORT_TYPE
|
335 |
|
|
dout[7] <= dout[7].DB_MAX_OUTPUT_PORT_TYPE
|
336 |
|
|
wen => byte_reg[7].ENA
|
337 |
|
|
wen => byte_reg[6].ENA
|
338 |
|
|
wen => byte_reg[5].ENA
|
339 |
|
|
wen => byte_reg[4].ENA
|
340 |
|
|
wen => byte_reg[3].ENA
|
341 |
|
|
wen => byte_reg[2].ENA
|
342 |
|
|
wen => byte_reg[1].ENA
|
343 |
|
|
wen => byte_reg[0].ENA
|
344 |
|
|
ren => dout[0].OE
|
345 |
|
|
ren => dout[1].OE
|
346 |
|
|
ren => dout[2].OE
|
347 |
|
|
ren => dout[3].OE
|
348 |
|
|
ren => dout[4].OE
|
349 |
|
|
ren => dout[5].OE
|
350 |
|
|
ren => dout[6].OE
|
351 |
|
|
ren => dout[7].OE
|
352 |
|
|
|
353 |
|
|
|
354 |
|
|
|wiegand_tx_top|fifo_wieg:datafifowrite|custom_fifo_dp:custom_fifo_dp6
|
355 |
|
|
clk_rd => addr_rd[0].CLK
|
356 |
|
|
clk_rd => addr_rd[1].CLK
|
357 |
|
|
clk_rd => addr_rd[2].CLK
|
358 |
|
|
clk_rd => fifo_out[0].CLK
|
359 |
|
|
clk_rd => fifo_out[1].CLK
|
360 |
|
|
clk_rd => fifo_out[2].CLK
|
361 |
|
|
clk_rd => fifo_out[3].CLK
|
362 |
|
|
clk_rd => fifo_out[4].CLK
|
363 |
|
|
clk_rd => fifo_out[5].CLK
|
364 |
|
|
clk_rd => fifo_out[6].CLK
|
365 |
|
|
clk_rd => fifo_out[7].CLK
|
366 |
|
|
clk_wr => clk_wr.IN3
|
367 |
|
|
d_i[0] => d_i[0].IN3
|
368 |
|
|
d_i[1] => d_i[1].IN3
|
369 |
|
|
d_i[2] => d_i[2].IN3
|
370 |
|
|
d_i[3] => d_i[3].IN3
|
371 |
|
|
d_i[4] => d_i[4].IN3
|
372 |
|
|
d_i[5] => d_i[5].IN3
|
373 |
|
|
d_i[6] => d_i[6].IN3
|
374 |
|
|
d_i[7] => d_i[7].IN3
|
375 |
|
|
d_o[0] <= fifo_out[0].DB_MAX_OUTPUT_PORT_TYPE
|
376 |
|
|
d_o[1] <= fifo_out[1].DB_MAX_OUTPUT_PORT_TYPE
|
377 |
|
|
d_o[2] <= fifo_out[2].DB_MAX_OUTPUT_PORT_TYPE
|
378 |
|
|
d_o[3] <= fifo_out[3].DB_MAX_OUTPUT_PORT_TYPE
|
379 |
|
|
d_o[4] <= fifo_out[4].DB_MAX_OUTPUT_PORT_TYPE
|
380 |
|
|
d_o[5] <= fifo_out[5].DB_MAX_OUTPUT_PORT_TYPE
|
381 |
|
|
d_o[6] <= fifo_out[6].DB_MAX_OUTPUT_PORT_TYPE
|
382 |
|
|
d_o[7] <= fifo_out[7].DB_MAX_OUTPUT_PORT_TYPE
|
383 |
|
|
rst => rst.IN3
|
384 |
|
|
wr_en => always1.IN1
|
385 |
|
|
rd_en => always2.IN1
|
386 |
|
|
full <= full.DB_MAX_OUTPUT_PORT_TYPE
|
387 |
|
|
empty <= Equal0.DB_MAX_OUTPUT_PORT_TYPE
|
388 |
|
|
|
389 |
|
|
|
390 |
|
|
|wiegand_tx_top|fifo_wieg:datafifowrite|custom_fifo_dp:custom_fifo_dp6|mem_byte:mem[0].mem_byte
|
391 |
|
|
rst => byte_reg[0].ACLR
|
392 |
|
|
rst => byte_reg[1].ACLR
|
393 |
|
|
rst => byte_reg[2].ACLR
|
394 |
|
|
rst => byte_reg[3].ACLR
|
395 |
|
|
rst => byte_reg[4].ACLR
|
396 |
|
|
rst => byte_reg[5].ACLR
|
397 |
|
|
rst => byte_reg[6].ACLR
|
398 |
|
|
rst => byte_reg[7].ACLR
|
399 |
|
|
clk => byte_reg[0].CLK
|
400 |
|
|
clk => byte_reg[1].CLK
|
401 |
|
|
clk => byte_reg[2].CLK
|
402 |
|
|
clk => byte_reg[3].CLK
|
403 |
|
|
clk => byte_reg[4].CLK
|
404 |
|
|
clk => byte_reg[5].CLK
|
405 |
|
|
clk => byte_reg[6].CLK
|
406 |
|
|
clk => byte_reg[7].CLK
|
407 |
|
|
din[0] => byte_reg[0].DATAIN
|
408 |
|
|
din[1] => byte_reg[1].DATAIN
|
409 |
|
|
din[2] => byte_reg[2].DATAIN
|
410 |
|
|
din[3] => byte_reg[3].DATAIN
|
411 |
|
|
din[4] => byte_reg[4].DATAIN
|
412 |
|
|
din[5] => byte_reg[5].DATAIN
|
413 |
|
|
din[6] => byte_reg[6].DATAIN
|
414 |
|
|
din[7] => byte_reg[7].DATAIN
|
415 |
|
|
dout[0] <= dout[0].DB_MAX_OUTPUT_PORT_TYPE
|
416 |
|
|
dout[1] <= dout[1].DB_MAX_OUTPUT_PORT_TYPE
|
417 |
|
|
dout[2] <= dout[2].DB_MAX_OUTPUT_PORT_TYPE
|
418 |
|
|
dout[3] <= dout[3].DB_MAX_OUTPUT_PORT_TYPE
|
419 |
|
|
dout[4] <= dout[4].DB_MAX_OUTPUT_PORT_TYPE
|
420 |
|
|
dout[5] <= dout[5].DB_MAX_OUTPUT_PORT_TYPE
|
421 |
|
|
dout[6] <= dout[6].DB_MAX_OUTPUT_PORT_TYPE
|
422 |
|
|
dout[7] <= dout[7].DB_MAX_OUTPUT_PORT_TYPE
|
423 |
|
|
wen => byte_reg[7].ENA
|
424 |
|
|
wen => byte_reg[6].ENA
|
425 |
|
|
wen => byte_reg[5].ENA
|
426 |
|
|
wen => byte_reg[4].ENA
|
427 |
|
|
wen => byte_reg[3].ENA
|
428 |
|
|
wen => byte_reg[2].ENA
|
429 |
|
|
wen => byte_reg[1].ENA
|
430 |
|
|
wen => byte_reg[0].ENA
|
431 |
|
|
ren => dout[0].OE
|
432 |
|
|
ren => dout[1].OE
|
433 |
|
|
ren => dout[2].OE
|
434 |
|
|
ren => dout[3].OE
|
435 |
|
|
ren => dout[4].OE
|
436 |
|
|
ren => dout[5].OE
|
437 |
|
|
ren => dout[6].OE
|
438 |
|
|
ren => dout[7].OE
|
439 |
|
|
|
440 |
|
|
|
441 |
|
|
|wiegand_tx_top|fifo_wieg:datafifowrite|custom_fifo_dp:custom_fifo_dp6|mem_byte:mem[1].mem_byte
|
442 |
|
|
rst => byte_reg[0].ACLR
|
443 |
|
|
rst => byte_reg[1].ACLR
|
444 |
|
|
rst => byte_reg[2].ACLR
|
445 |
|
|
rst => byte_reg[3].ACLR
|
446 |
|
|
rst => byte_reg[4].ACLR
|
447 |
|
|
rst => byte_reg[5].ACLR
|
448 |
|
|
rst => byte_reg[6].ACLR
|
449 |
|
|
rst => byte_reg[7].ACLR
|
450 |
|
|
clk => byte_reg[0].CLK
|
451 |
|
|
clk => byte_reg[1].CLK
|
452 |
|
|
clk => byte_reg[2].CLK
|
453 |
|
|
clk => byte_reg[3].CLK
|
454 |
|
|
clk => byte_reg[4].CLK
|
455 |
|
|
clk => byte_reg[5].CLK
|
456 |
|
|
clk => byte_reg[6].CLK
|
457 |
|
|
clk => byte_reg[7].CLK
|
458 |
|
|
din[0] => byte_reg[0].DATAIN
|
459 |
|
|
din[1] => byte_reg[1].DATAIN
|
460 |
|
|
din[2] => byte_reg[2].DATAIN
|
461 |
|
|
din[3] => byte_reg[3].DATAIN
|
462 |
|
|
din[4] => byte_reg[4].DATAIN
|
463 |
|
|
din[5] => byte_reg[5].DATAIN
|
464 |
|
|
din[6] => byte_reg[6].DATAIN
|
465 |
|
|
din[7] => byte_reg[7].DATAIN
|
466 |
|
|
dout[0] <= dout[0].DB_MAX_OUTPUT_PORT_TYPE
|
467 |
|
|
dout[1] <= dout[1].DB_MAX_OUTPUT_PORT_TYPE
|
468 |
|
|
dout[2] <= dout[2].DB_MAX_OUTPUT_PORT_TYPE
|
469 |
|
|
dout[3] <= dout[3].DB_MAX_OUTPUT_PORT_TYPE
|
470 |
|
|
dout[4] <= dout[4].DB_MAX_OUTPUT_PORT_TYPE
|
471 |
|
|
dout[5] <= dout[5].DB_MAX_OUTPUT_PORT_TYPE
|
472 |
|
|
dout[6] <= dout[6].DB_MAX_OUTPUT_PORT_TYPE
|
473 |
|
|
dout[7] <= dout[7].DB_MAX_OUTPUT_PORT_TYPE
|
474 |
|
|
wen => byte_reg[7].ENA
|
475 |
|
|
wen => byte_reg[6].ENA
|
476 |
|
|
wen => byte_reg[5].ENA
|
477 |
|
|
wen => byte_reg[4].ENA
|
478 |
|
|
wen => byte_reg[3].ENA
|
479 |
|
|
wen => byte_reg[2].ENA
|
480 |
|
|
wen => byte_reg[1].ENA
|
481 |
|
|
wen => byte_reg[0].ENA
|
482 |
|
|
ren => dout[0].OE
|
483 |
|
|
ren => dout[1].OE
|
484 |
|
|
ren => dout[2].OE
|
485 |
|
|
ren => dout[3].OE
|
486 |
|
|
ren => dout[4].OE
|
487 |
|
|
ren => dout[5].OE
|
488 |
|
|
ren => dout[6].OE
|
489 |
|
|
ren => dout[7].OE
|
490 |
|
|
|
491 |
|
|
|
492 |
|
|
|wiegand_tx_top|fifo_wieg:datafifowrite|custom_fifo_dp:custom_fifo_dp6|mem_byte:mem[2].mem_byte
|
493 |
|
|
rst => byte_reg[0].ACLR
|
494 |
|
|
rst => byte_reg[1].ACLR
|
495 |
|
|
rst => byte_reg[2].ACLR
|
496 |
|
|
rst => byte_reg[3].ACLR
|
497 |
|
|
rst => byte_reg[4].ACLR
|
498 |
|
|
rst => byte_reg[5].ACLR
|
499 |
|
|
rst => byte_reg[6].ACLR
|
500 |
|
|
rst => byte_reg[7].ACLR
|
501 |
|
|
clk => byte_reg[0].CLK
|
502 |
|
|
clk => byte_reg[1].CLK
|
503 |
|
|
clk => byte_reg[2].CLK
|
504 |
|
|
clk => byte_reg[3].CLK
|
505 |
|
|
clk => byte_reg[4].CLK
|
506 |
|
|
clk => byte_reg[5].CLK
|
507 |
|
|
clk => byte_reg[6].CLK
|
508 |
|
|
clk => byte_reg[7].CLK
|
509 |
|
|
din[0] => byte_reg[0].DATAIN
|
510 |
|
|
din[1] => byte_reg[1].DATAIN
|
511 |
|
|
din[2] => byte_reg[2].DATAIN
|
512 |
|
|
din[3] => byte_reg[3].DATAIN
|
513 |
|
|
din[4] => byte_reg[4].DATAIN
|
514 |
|
|
din[5] => byte_reg[5].DATAIN
|
515 |
|
|
din[6] => byte_reg[6].DATAIN
|
516 |
|
|
din[7] => byte_reg[7].DATAIN
|
517 |
|
|
dout[0] <= dout[0].DB_MAX_OUTPUT_PORT_TYPE
|
518 |
|
|
dout[1] <= dout[1].DB_MAX_OUTPUT_PORT_TYPE
|
519 |
|
|
dout[2] <= dout[2].DB_MAX_OUTPUT_PORT_TYPE
|
520 |
|
|
dout[3] <= dout[3].DB_MAX_OUTPUT_PORT_TYPE
|
521 |
|
|
dout[4] <= dout[4].DB_MAX_OUTPUT_PORT_TYPE
|
522 |
|
|
dout[5] <= dout[5].DB_MAX_OUTPUT_PORT_TYPE
|
523 |
|
|
dout[6] <= dout[6].DB_MAX_OUTPUT_PORT_TYPE
|
524 |
|
|
dout[7] <= dout[7].DB_MAX_OUTPUT_PORT_TYPE
|
525 |
|
|
wen => byte_reg[7].ENA
|
526 |
|
|
wen => byte_reg[6].ENA
|
527 |
|
|
wen => byte_reg[5].ENA
|
528 |
|
|
wen => byte_reg[4].ENA
|
529 |
|
|
wen => byte_reg[3].ENA
|
530 |
|
|
wen => byte_reg[2].ENA
|
531 |
|
|
wen => byte_reg[1].ENA
|
532 |
|
|
wen => byte_reg[0].ENA
|
533 |
|
|
ren => dout[0].OE
|
534 |
|
|
ren => dout[1].OE
|
535 |
|
|
ren => dout[2].OE
|
536 |
|
|
ren => dout[3].OE
|
537 |
|
|
ren => dout[4].OE
|
538 |
|
|
ren => dout[5].OE
|
539 |
|
|
ren => dout[6].OE
|
540 |
|
|
ren => dout[7].OE
|
541 |
|
|
|
542 |
|
|
|
543 |
|
|
|wiegand_tx_top|fifo_wieg:datafifowrite|custom_fifo_dp:custom_fifo_dp7
|
544 |
|
|
clk_rd => addr_rd[0].CLK
|
545 |
|
|
clk_rd => addr_rd[1].CLK
|
546 |
|
|
clk_rd => addr_rd[2].CLK
|
547 |
|
|
clk_rd => fifo_out[0].CLK
|
548 |
|
|
clk_rd => fifo_out[1].CLK
|
549 |
|
|
clk_rd => fifo_out[2].CLK
|
550 |
|
|
clk_rd => fifo_out[3].CLK
|
551 |
|
|
clk_rd => fifo_out[4].CLK
|
552 |
|
|
clk_rd => fifo_out[5].CLK
|
553 |
|
|
clk_rd => fifo_out[6].CLK
|
554 |
|
|
clk_rd => fifo_out[7].CLK
|
555 |
|
|
clk_wr => clk_wr.IN3
|
556 |
|
|
d_i[0] => d_i[0].IN3
|
557 |
|
|
d_i[1] => d_i[1].IN3
|
558 |
|
|
d_i[2] => d_i[2].IN3
|
559 |
|
|
d_i[3] => d_i[3].IN3
|
560 |
|
|
d_i[4] => d_i[4].IN3
|
561 |
|
|
d_i[5] => d_i[5].IN3
|
562 |
|
|
d_i[6] => d_i[6].IN3
|
563 |
|
|
d_i[7] => d_i[7].IN3
|
564 |
|
|
d_o[0] <= fifo_out[0].DB_MAX_OUTPUT_PORT_TYPE
|
565 |
|
|
d_o[1] <= fifo_out[1].DB_MAX_OUTPUT_PORT_TYPE
|
566 |
|
|
d_o[2] <= fifo_out[2].DB_MAX_OUTPUT_PORT_TYPE
|
567 |
|
|
d_o[3] <= fifo_out[3].DB_MAX_OUTPUT_PORT_TYPE
|
568 |
|
|
d_o[4] <= fifo_out[4].DB_MAX_OUTPUT_PORT_TYPE
|
569 |
|
|
d_o[5] <= fifo_out[5].DB_MAX_OUTPUT_PORT_TYPE
|
570 |
|
|
d_o[6] <= fifo_out[6].DB_MAX_OUTPUT_PORT_TYPE
|
571 |
|
|
d_o[7] <= fifo_out[7].DB_MAX_OUTPUT_PORT_TYPE
|
572 |
|
|
rst => rst.IN3
|
573 |
|
|
wr_en => always1.IN1
|
574 |
|
|
rd_en => always2.IN1
|
575 |
|
|
full <= full.DB_MAX_OUTPUT_PORT_TYPE
|
576 |
|
|
empty <= Equal0.DB_MAX_OUTPUT_PORT_TYPE
|
577 |
|
|
|
578 |
|
|
|
579 |
|
|
|wiegand_tx_top|fifo_wieg:datafifowrite|custom_fifo_dp:custom_fifo_dp7|mem_byte:mem[0].mem_byte
|
580 |
|
|
rst => byte_reg[0].ACLR
|
581 |
|
|
rst => byte_reg[1].ACLR
|
582 |
|
|
rst => byte_reg[2].ACLR
|
583 |
|
|
rst => byte_reg[3].ACLR
|
584 |
|
|
rst => byte_reg[4].ACLR
|
585 |
|
|
rst => byte_reg[5].ACLR
|
586 |
|
|
rst => byte_reg[6].ACLR
|
587 |
|
|
rst => byte_reg[7].ACLR
|
588 |
|
|
clk => byte_reg[0].CLK
|
589 |
|
|
clk => byte_reg[1].CLK
|
590 |
|
|
clk => byte_reg[2].CLK
|
591 |
|
|
clk => byte_reg[3].CLK
|
592 |
|
|
clk => byte_reg[4].CLK
|
593 |
|
|
clk => byte_reg[5].CLK
|
594 |
|
|
clk => byte_reg[6].CLK
|
595 |
|
|
clk => byte_reg[7].CLK
|
596 |
|
|
din[0] => byte_reg[0].DATAIN
|
597 |
|
|
din[1] => byte_reg[1].DATAIN
|
598 |
|
|
din[2] => byte_reg[2].DATAIN
|
599 |
|
|
din[3] => byte_reg[3].DATAIN
|
600 |
|
|
din[4] => byte_reg[4].DATAIN
|
601 |
|
|
din[5] => byte_reg[5].DATAIN
|
602 |
|
|
din[6] => byte_reg[6].DATAIN
|
603 |
|
|
din[7] => byte_reg[7].DATAIN
|
604 |
|
|
dout[0] <= dout[0].DB_MAX_OUTPUT_PORT_TYPE
|
605 |
|
|
dout[1] <= dout[1].DB_MAX_OUTPUT_PORT_TYPE
|
606 |
|
|
dout[2] <= dout[2].DB_MAX_OUTPUT_PORT_TYPE
|
607 |
|
|
dout[3] <= dout[3].DB_MAX_OUTPUT_PORT_TYPE
|
608 |
|
|
dout[4] <= dout[4].DB_MAX_OUTPUT_PORT_TYPE
|
609 |
|
|
dout[5] <= dout[5].DB_MAX_OUTPUT_PORT_TYPE
|
610 |
|
|
dout[6] <= dout[6].DB_MAX_OUTPUT_PORT_TYPE
|
611 |
|
|
dout[7] <= dout[7].DB_MAX_OUTPUT_PORT_TYPE
|
612 |
|
|
wen => byte_reg[7].ENA
|
613 |
|
|
wen => byte_reg[6].ENA
|
614 |
|
|
wen => byte_reg[5].ENA
|
615 |
|
|
wen => byte_reg[4].ENA
|
616 |
|
|
wen => byte_reg[3].ENA
|
617 |
|
|
wen => byte_reg[2].ENA
|
618 |
|
|
wen => byte_reg[1].ENA
|
619 |
|
|
wen => byte_reg[0].ENA
|
620 |
|
|
ren => dout[0].OE
|
621 |
|
|
ren => dout[1].OE
|
622 |
|
|
ren => dout[2].OE
|
623 |
|
|
ren => dout[3].OE
|
624 |
|
|
ren => dout[4].OE
|
625 |
|
|
ren => dout[5].OE
|
626 |
|
|
ren => dout[6].OE
|
627 |
|
|
ren => dout[7].OE
|
628 |
|
|
|
629 |
|
|
|
630 |
|
|
|wiegand_tx_top|fifo_wieg:datafifowrite|custom_fifo_dp:custom_fifo_dp7|mem_byte:mem[1].mem_byte
|
631 |
|
|
rst => byte_reg[0].ACLR
|
632 |
|
|
rst => byte_reg[1].ACLR
|
633 |
|
|
rst => byte_reg[2].ACLR
|
634 |
|
|
rst => byte_reg[3].ACLR
|
635 |
|
|
rst => byte_reg[4].ACLR
|
636 |
|
|
rst => byte_reg[5].ACLR
|
637 |
|
|
rst => byte_reg[6].ACLR
|
638 |
|
|
rst => byte_reg[7].ACLR
|
639 |
|
|
clk => byte_reg[0].CLK
|
640 |
|
|
clk => byte_reg[1].CLK
|
641 |
|
|
clk => byte_reg[2].CLK
|
642 |
|
|
clk => byte_reg[3].CLK
|
643 |
|
|
clk => byte_reg[4].CLK
|
644 |
|
|
clk => byte_reg[5].CLK
|
645 |
|
|
clk => byte_reg[6].CLK
|
646 |
|
|
clk => byte_reg[7].CLK
|
647 |
|
|
din[0] => byte_reg[0].DATAIN
|
648 |
|
|
din[1] => byte_reg[1].DATAIN
|
649 |
|
|
din[2] => byte_reg[2].DATAIN
|
650 |
|
|
din[3] => byte_reg[3].DATAIN
|
651 |
|
|
din[4] => byte_reg[4].DATAIN
|
652 |
|
|
din[5] => byte_reg[5].DATAIN
|
653 |
|
|
din[6] => byte_reg[6].DATAIN
|
654 |
|
|
din[7] => byte_reg[7].DATAIN
|
655 |
|
|
dout[0] <= dout[0].DB_MAX_OUTPUT_PORT_TYPE
|
656 |
|
|
dout[1] <= dout[1].DB_MAX_OUTPUT_PORT_TYPE
|
657 |
|
|
dout[2] <= dout[2].DB_MAX_OUTPUT_PORT_TYPE
|
658 |
|
|
dout[3] <= dout[3].DB_MAX_OUTPUT_PORT_TYPE
|
659 |
|
|
dout[4] <= dout[4].DB_MAX_OUTPUT_PORT_TYPE
|
660 |
|
|
dout[5] <= dout[5].DB_MAX_OUTPUT_PORT_TYPE
|
661 |
|
|
dout[6] <= dout[6].DB_MAX_OUTPUT_PORT_TYPE
|
662 |
|
|
dout[7] <= dout[7].DB_MAX_OUTPUT_PORT_TYPE
|
663 |
|
|
wen => byte_reg[7].ENA
|
664 |
|
|
wen => byte_reg[6].ENA
|
665 |
|
|
wen => byte_reg[5].ENA
|
666 |
|
|
wen => byte_reg[4].ENA
|
667 |
|
|
wen => byte_reg[3].ENA
|
668 |
|
|
wen => byte_reg[2].ENA
|
669 |
|
|
wen => byte_reg[1].ENA
|
670 |
|
|
wen => byte_reg[0].ENA
|
671 |
|
|
ren => dout[0].OE
|
672 |
|
|
ren => dout[1].OE
|
673 |
|
|
ren => dout[2].OE
|
674 |
|
|
ren => dout[3].OE
|
675 |
|
|
ren => dout[4].OE
|
676 |
|
|
ren => dout[5].OE
|
677 |
|
|
ren => dout[6].OE
|
678 |
|
|
ren => dout[7].OE
|
679 |
|
|
|
680 |
|
|
|
681 |
|
|
|wiegand_tx_top|fifo_wieg:datafifowrite|custom_fifo_dp:custom_fifo_dp7|mem_byte:mem[2].mem_byte
|
682 |
|
|
rst => byte_reg[0].ACLR
|
683 |
|
|
rst => byte_reg[1].ACLR
|
684 |
|
|
rst => byte_reg[2].ACLR
|
685 |
|
|
rst => byte_reg[3].ACLR
|
686 |
|
|
rst => byte_reg[4].ACLR
|
687 |
|
|
rst => byte_reg[5].ACLR
|
688 |
|
|
rst => byte_reg[6].ACLR
|
689 |
|
|
rst => byte_reg[7].ACLR
|
690 |
|
|
clk => byte_reg[0].CLK
|
691 |
|
|
clk => byte_reg[1].CLK
|
692 |
|
|
clk => byte_reg[2].CLK
|
693 |
|
|
clk => byte_reg[3].CLK
|
694 |
|
|
clk => byte_reg[4].CLK
|
695 |
|
|
clk => byte_reg[5].CLK
|
696 |
|
|
clk => byte_reg[6].CLK
|
697 |
|
|
clk => byte_reg[7].CLK
|
698 |
|
|
din[0] => byte_reg[0].DATAIN
|
699 |
|
|
din[1] => byte_reg[1].DATAIN
|
700 |
|
|
din[2] => byte_reg[2].DATAIN
|
701 |
|
|
din[3] => byte_reg[3].DATAIN
|
702 |
|
|
din[4] => byte_reg[4].DATAIN
|
703 |
|
|
din[5] => byte_reg[5].DATAIN
|
704 |
|
|
din[6] => byte_reg[6].DATAIN
|
705 |
|
|
din[7] => byte_reg[7].DATAIN
|
706 |
|
|
dout[0] <= dout[0].DB_MAX_OUTPUT_PORT_TYPE
|
707 |
|
|
dout[1] <= dout[1].DB_MAX_OUTPUT_PORT_TYPE
|
708 |
|
|
dout[2] <= dout[2].DB_MAX_OUTPUT_PORT_TYPE
|
709 |
|
|
dout[3] <= dout[3].DB_MAX_OUTPUT_PORT_TYPE
|
710 |
|
|
dout[4] <= dout[4].DB_MAX_OUTPUT_PORT_TYPE
|
711 |
|
|
dout[5] <= dout[5].DB_MAX_OUTPUT_PORT_TYPE
|
712 |
|
|
dout[6] <= dout[6].DB_MAX_OUTPUT_PORT_TYPE
|
713 |
|
|
dout[7] <= dout[7].DB_MAX_OUTPUT_PORT_TYPE
|
714 |
|
|
wen => byte_reg[7].ENA
|
715 |
|
|
wen => byte_reg[6].ENA
|
716 |
|
|
wen => byte_reg[5].ENA
|
717 |
|
|
wen => byte_reg[4].ENA
|
718 |
|
|
wen => byte_reg[3].ENA
|
719 |
|
|
wen => byte_reg[2].ENA
|
720 |
|
|
wen => byte_reg[1].ENA
|
721 |
|
|
wen => byte_reg[0].ENA
|
722 |
|
|
ren => dout[0].OE
|
723 |
|
|
ren => dout[1].OE
|
724 |
|
|
ren => dout[2].OE
|
725 |
|
|
ren => dout[3].OE
|
726 |
|
|
ren => dout[4].OE
|
727 |
|
|
ren => dout[5].OE
|
728 |
|
|
ren => dout[6].OE
|
729 |
|
|
ren => dout[7].OE
|
730 |
|
|
|
731 |
|
|
|
732 |
|
|
|wiegand_tx_top|fifo_wieg:datafifowrite|custom_fifo_dp:custom_fifo_dp8
|
733 |
|
|
clk_rd => addr_rd[0].CLK
|
734 |
|
|
clk_rd => addr_rd[1].CLK
|
735 |
|
|
clk_rd => addr_rd[2].CLK
|
736 |
|
|
clk_rd => fifo_out[0].CLK
|
737 |
|
|
clk_rd => fifo_out[1].CLK
|
738 |
|
|
clk_rd => fifo_out[2].CLK
|
739 |
|
|
clk_rd => fifo_out[3].CLK
|
740 |
|
|
clk_rd => fifo_out[4].CLK
|
741 |
|
|
clk_rd => fifo_out[5].CLK
|
742 |
|
|
clk_rd => fifo_out[6].CLK
|
743 |
|
|
clk_rd => fifo_out[7].CLK
|
744 |
|
|
clk_wr => clk_wr.IN3
|
745 |
|
|
d_i[0] => d_i[0].IN3
|
746 |
|
|
d_i[1] => d_i[1].IN3
|
747 |
|
|
d_i[2] => d_i[2].IN3
|
748 |
|
|
d_i[3] => d_i[3].IN3
|
749 |
|
|
d_i[4] => d_i[4].IN3
|
750 |
|
|
d_i[5] => d_i[5].IN3
|
751 |
|
|
d_i[6] => d_i[6].IN3
|
752 |
|
|
d_i[7] => d_i[7].IN3
|
753 |
|
|
d_o[0] <= fifo_out[0].DB_MAX_OUTPUT_PORT_TYPE
|
754 |
|
|
d_o[1] <= fifo_out[1].DB_MAX_OUTPUT_PORT_TYPE
|
755 |
|
|
d_o[2] <= fifo_out[2].DB_MAX_OUTPUT_PORT_TYPE
|
756 |
|
|
d_o[3] <= fifo_out[3].DB_MAX_OUTPUT_PORT_TYPE
|
757 |
|
|
d_o[4] <= fifo_out[4].DB_MAX_OUTPUT_PORT_TYPE
|
758 |
|
|
d_o[5] <= fifo_out[5].DB_MAX_OUTPUT_PORT_TYPE
|
759 |
|
|
d_o[6] <= fifo_out[6].DB_MAX_OUTPUT_PORT_TYPE
|
760 |
|
|
d_o[7] <= fifo_out[7].DB_MAX_OUTPUT_PORT_TYPE
|
761 |
|
|
rst => rst.IN3
|
762 |
|
|
wr_en => always1.IN1
|
763 |
|
|
rd_en => always2.IN1
|
764 |
|
|
full <= full.DB_MAX_OUTPUT_PORT_TYPE
|
765 |
|
|
empty <= Equal0.DB_MAX_OUTPUT_PORT_TYPE
|
766 |
|
|
|
767 |
|
|
|
768 |
|
|
|wiegand_tx_top|fifo_wieg:datafifowrite|custom_fifo_dp:custom_fifo_dp8|mem_byte:mem[0].mem_byte
|
769 |
|
|
rst => byte_reg[0].ACLR
|
770 |
|
|
rst => byte_reg[1].ACLR
|
771 |
|
|
rst => byte_reg[2].ACLR
|
772 |
|
|
rst => byte_reg[3].ACLR
|
773 |
|
|
rst => byte_reg[4].ACLR
|
774 |
|
|
rst => byte_reg[5].ACLR
|
775 |
|
|
rst => byte_reg[6].ACLR
|
776 |
|
|
rst => byte_reg[7].ACLR
|
777 |
|
|
clk => byte_reg[0].CLK
|
778 |
|
|
clk => byte_reg[1].CLK
|
779 |
|
|
clk => byte_reg[2].CLK
|
780 |
|
|
clk => byte_reg[3].CLK
|
781 |
|
|
clk => byte_reg[4].CLK
|
782 |
|
|
clk => byte_reg[5].CLK
|
783 |
|
|
clk => byte_reg[6].CLK
|
784 |
|
|
clk => byte_reg[7].CLK
|
785 |
|
|
din[0] => byte_reg[0].DATAIN
|
786 |
|
|
din[1] => byte_reg[1].DATAIN
|
787 |
|
|
din[2] => byte_reg[2].DATAIN
|
788 |
|
|
din[3] => byte_reg[3].DATAIN
|
789 |
|
|
din[4] => byte_reg[4].DATAIN
|
790 |
|
|
din[5] => byte_reg[5].DATAIN
|
791 |
|
|
din[6] => byte_reg[6].DATAIN
|
792 |
|
|
din[7] => byte_reg[7].DATAIN
|
793 |
|
|
dout[0] <= dout[0].DB_MAX_OUTPUT_PORT_TYPE
|
794 |
|
|
dout[1] <= dout[1].DB_MAX_OUTPUT_PORT_TYPE
|
795 |
|
|
dout[2] <= dout[2].DB_MAX_OUTPUT_PORT_TYPE
|
796 |
|
|
dout[3] <= dout[3].DB_MAX_OUTPUT_PORT_TYPE
|
797 |
|
|
dout[4] <= dout[4].DB_MAX_OUTPUT_PORT_TYPE
|
798 |
|
|
dout[5] <= dout[5].DB_MAX_OUTPUT_PORT_TYPE
|
799 |
|
|
dout[6] <= dout[6].DB_MAX_OUTPUT_PORT_TYPE
|
800 |
|
|
dout[7] <= dout[7].DB_MAX_OUTPUT_PORT_TYPE
|
801 |
|
|
wen => byte_reg[7].ENA
|
802 |
|
|
wen => byte_reg[6].ENA
|
803 |
|
|
wen => byte_reg[5].ENA
|
804 |
|
|
wen => byte_reg[4].ENA
|
805 |
|
|
wen => byte_reg[3].ENA
|
806 |
|
|
wen => byte_reg[2].ENA
|
807 |
|
|
wen => byte_reg[1].ENA
|
808 |
|
|
wen => byte_reg[0].ENA
|
809 |
|
|
ren => dout[0].OE
|
810 |
|
|
ren => dout[1].OE
|
811 |
|
|
ren => dout[2].OE
|
812 |
|
|
ren => dout[3].OE
|
813 |
|
|
ren => dout[4].OE
|
814 |
|
|
ren => dout[5].OE
|
815 |
|
|
ren => dout[6].OE
|
816 |
|
|
ren => dout[7].OE
|
817 |
|
|
|
818 |
|
|
|
819 |
|
|
|wiegand_tx_top|fifo_wieg:datafifowrite|custom_fifo_dp:custom_fifo_dp8|mem_byte:mem[1].mem_byte
|
820 |
|
|
rst => byte_reg[0].ACLR
|
821 |
|
|
rst => byte_reg[1].ACLR
|
822 |
|
|
rst => byte_reg[2].ACLR
|
823 |
|
|
rst => byte_reg[3].ACLR
|
824 |
|
|
rst => byte_reg[4].ACLR
|
825 |
|
|
rst => byte_reg[5].ACLR
|
826 |
|
|
rst => byte_reg[6].ACLR
|
827 |
|
|
rst => byte_reg[7].ACLR
|
828 |
|
|
clk => byte_reg[0].CLK
|
829 |
|
|
clk => byte_reg[1].CLK
|
830 |
|
|
clk => byte_reg[2].CLK
|
831 |
|
|
clk => byte_reg[3].CLK
|
832 |
|
|
clk => byte_reg[4].CLK
|
833 |
|
|
clk => byte_reg[5].CLK
|
834 |
|
|
clk => byte_reg[6].CLK
|
835 |
|
|
clk => byte_reg[7].CLK
|
836 |
|
|
din[0] => byte_reg[0].DATAIN
|
837 |
|
|
din[1] => byte_reg[1].DATAIN
|
838 |
|
|
din[2] => byte_reg[2].DATAIN
|
839 |
|
|
din[3] => byte_reg[3].DATAIN
|
840 |
|
|
din[4] => byte_reg[4].DATAIN
|
841 |
|
|
din[5] => byte_reg[5].DATAIN
|
842 |
|
|
din[6] => byte_reg[6].DATAIN
|
843 |
|
|
din[7] => byte_reg[7].DATAIN
|
844 |
|
|
dout[0] <= dout[0].DB_MAX_OUTPUT_PORT_TYPE
|
845 |
|
|
dout[1] <= dout[1].DB_MAX_OUTPUT_PORT_TYPE
|
846 |
|
|
dout[2] <= dout[2].DB_MAX_OUTPUT_PORT_TYPE
|
847 |
|
|
dout[3] <= dout[3].DB_MAX_OUTPUT_PORT_TYPE
|
848 |
|
|
dout[4] <= dout[4].DB_MAX_OUTPUT_PORT_TYPE
|
849 |
|
|
dout[5] <= dout[5].DB_MAX_OUTPUT_PORT_TYPE
|
850 |
|
|
dout[6] <= dout[6].DB_MAX_OUTPUT_PORT_TYPE
|
851 |
|
|
dout[7] <= dout[7].DB_MAX_OUTPUT_PORT_TYPE
|
852 |
|
|
wen => byte_reg[7].ENA
|
853 |
|
|
wen => byte_reg[6].ENA
|
854 |
|
|
wen => byte_reg[5].ENA
|
855 |
|
|
wen => byte_reg[4].ENA
|
856 |
|
|
wen => byte_reg[3].ENA
|
857 |
|
|
wen => byte_reg[2].ENA
|
858 |
|
|
wen => byte_reg[1].ENA
|
859 |
|
|
wen => byte_reg[0].ENA
|
860 |
|
|
ren => dout[0].OE
|
861 |
|
|
ren => dout[1].OE
|
862 |
|
|
ren => dout[2].OE
|
863 |
|
|
ren => dout[3].OE
|
864 |
|
|
ren => dout[4].OE
|
865 |
|
|
ren => dout[5].OE
|
866 |
|
|
ren => dout[6].OE
|
867 |
|
|
ren => dout[7].OE
|
868 |
|
|
|
869 |
|
|
|
870 |
|
|
|wiegand_tx_top|fifo_wieg:datafifowrite|custom_fifo_dp:custom_fifo_dp8|mem_byte:mem[2].mem_byte
|
871 |
|
|
rst => byte_reg[0].ACLR
|
872 |
|
|
rst => byte_reg[1].ACLR
|
873 |
|
|
rst => byte_reg[2].ACLR
|
874 |
|
|
rst => byte_reg[3].ACLR
|
875 |
|
|
rst => byte_reg[4].ACLR
|
876 |
|
|
rst => byte_reg[5].ACLR
|
877 |
|
|
rst => byte_reg[6].ACLR
|
878 |
|
|
rst => byte_reg[7].ACLR
|
879 |
|
|
clk => byte_reg[0].CLK
|
880 |
|
|
clk => byte_reg[1].CLK
|
881 |
|
|
clk => byte_reg[2].CLK
|
882 |
|
|
clk => byte_reg[3].CLK
|
883 |
|
|
clk => byte_reg[4].CLK
|
884 |
|
|
clk => byte_reg[5].CLK
|
885 |
|
|
clk => byte_reg[6].CLK
|
886 |
|
|
clk => byte_reg[7].CLK
|
887 |
|
|
din[0] => byte_reg[0].DATAIN
|
888 |
|
|
din[1] => byte_reg[1].DATAIN
|
889 |
|
|
din[2] => byte_reg[2].DATAIN
|
890 |
|
|
din[3] => byte_reg[3].DATAIN
|
891 |
|
|
din[4] => byte_reg[4].DATAIN
|
892 |
|
|
din[5] => byte_reg[5].DATAIN
|
893 |
|
|
din[6] => byte_reg[6].DATAIN
|
894 |
|
|
din[7] => byte_reg[7].DATAIN
|
895 |
|
|
dout[0] <= dout[0].DB_MAX_OUTPUT_PORT_TYPE
|
896 |
|
|
dout[1] <= dout[1].DB_MAX_OUTPUT_PORT_TYPE
|
897 |
|
|
dout[2] <= dout[2].DB_MAX_OUTPUT_PORT_TYPE
|
898 |
|
|
dout[3] <= dout[3].DB_MAX_OUTPUT_PORT_TYPE
|
899 |
|
|
dout[4] <= dout[4].DB_MAX_OUTPUT_PORT_TYPE
|
900 |
|
|
dout[5] <= dout[5].DB_MAX_OUTPUT_PORT_TYPE
|
901 |
|
|
dout[6] <= dout[6].DB_MAX_OUTPUT_PORT_TYPE
|
902 |
|
|
dout[7] <= dout[7].DB_MAX_OUTPUT_PORT_TYPE
|
903 |
|
|
wen => byte_reg[7].ENA
|
904 |
|
|
wen => byte_reg[6].ENA
|
905 |
|
|
wen => byte_reg[5].ENA
|
906 |
|
|
wen => byte_reg[4].ENA
|
907 |
|
|
wen => byte_reg[3].ENA
|
908 |
|
|
wen => byte_reg[2].ENA
|
909 |
|
|
wen => byte_reg[1].ENA
|
910 |
|
|
wen => byte_reg[0].ENA
|
911 |
|
|
ren => dout[0].OE
|
912 |
|
|
ren => dout[1].OE
|
913 |
|
|
ren => dout[2].OE
|
914 |
|
|
ren => dout[3].OE
|
915 |
|
|
ren => dout[4].OE
|
916 |
|
|
ren => dout[5].OE
|
917 |
|
|
ren => dout[6].OE
|
918 |
|
|
ren => dout[7].OE
|
919 |
|
|
|
920 |
|
|
|
921 |
|
|
|wiegand_tx_top|wb_interface_wieg:wb_interface
|
922 |
|
|
wb_rst_i => size[0].ACLR
|
923 |
|
|
wb_rst_i => size[1].ACLR
|
924 |
|
|
wb_rst_i => size[2].ACLR
|
925 |
|
|
wb_rst_i => size[3].ACLR
|
926 |
|
|
wb_rst_i => size[4].ACLR
|
927 |
|
|
wb_rst_i => size[5].ACLR
|
928 |
|
|
wb_rst_i => size[6].ACLR
|
929 |
|
|
wb_rst_i => size[7].ACLR
|
930 |
|
|
wb_rst_i => size[8].ACLR
|
931 |
|
|
wb_rst_i => p2p[0]~reg0.ACLR
|
932 |
|
|
wb_rst_i => p2p[1]~reg0.ACLR
|
933 |
|
|
wb_rst_i => p2p[2]~reg0.ACLR
|
934 |
|
|
wb_rst_i => p2p[3]~reg0.ACLR
|
935 |
|
|
wb_rst_i => p2p[4]~reg0.ACLR
|
936 |
|
|
wb_rst_i => p2p[5]~reg0.ACLR
|
937 |
|
|
wb_rst_i => p2p[6]~reg0.ACLR
|
938 |
|
|
wb_rst_i => p2p[7]~reg0.ACLR
|
939 |
|
|
wb_rst_i => p2p[8]~reg0.ACLR
|
940 |
|
|
wb_rst_i => p2p[9]~reg0.ACLR
|
941 |
|
|
wb_rst_i => p2p[10]~reg0.ACLR
|
942 |
|
|
wb_rst_i => p2p[11]~reg0.ACLR
|
943 |
|
|
wb_rst_i => p2p[12]~reg0.ACLR
|
944 |
|
|
wb_rst_i => p2p[13]~reg0.ACLR
|
945 |
|
|
wb_rst_i => p2p[14]~reg0.ACLR
|
946 |
|
|
wb_rst_i => p2p[15]~reg0.ACLR
|
947 |
|
|
wb_rst_i => p2p[16]~reg0.ACLR
|
948 |
|
|
wb_rst_i => p2p[17]~reg0.ACLR
|
949 |
|
|
wb_rst_i => p2p[18]~reg0.ACLR
|
950 |
|
|
wb_rst_i => p2p[19]~reg0.ACLR
|
951 |
|
|
wb_rst_i => p2p[20]~reg0.ACLR
|
952 |
|
|
wb_rst_i => p2p[21]~reg0.ACLR
|
953 |
|
|
wb_rst_i => p2p[22]~reg0.ACLR
|
954 |
|
|
wb_rst_i => p2p[23]~reg0.ACLR
|
955 |
|
|
wb_rst_i => p2p[24]~reg0.ACLR
|
956 |
|
|
wb_rst_i => p2p[25]~reg0.ACLR
|
957 |
|
|
wb_rst_i => p2p[26]~reg0.ACLR
|
958 |
|
|
wb_rst_i => p2p[27]~reg0.ACLR
|
959 |
|
|
wb_rst_i => p2p[28]~reg0.ACLR
|
960 |
|
|
wb_rst_i => p2p[29]~reg0.ACLR
|
961 |
|
|
wb_rst_i => p2p[30]~reg0.ACLR
|
962 |
|
|
wb_rst_i => p2p[31]~reg0.ACLR
|
963 |
|
|
wb_rst_i => pulsewidth[0]~reg0.ACLR
|
964 |
|
|
wb_rst_i => pulsewidth[1]~reg0.PRESET
|
965 |
|
|
wb_rst_i => pulsewidth[2]~reg0.ACLR
|
966 |
|
|
wb_rst_i => pulsewidth[3]~reg0.PRESET
|
967 |
|
|
wb_rst_i => pulsewidth[4]~reg0.ACLR
|
968 |
|
|
wb_rst_i => pulsewidth[5]~reg0.ACLR
|
969 |
|
|
wb_rst_i => pulsewidth[6]~reg0.ACLR
|
970 |
|
|
wb_rst_i => pulsewidth[7]~reg0.ACLR
|
971 |
|
|
wb_rst_i => pulsewidth[8]~reg0.ACLR
|
972 |
|
|
wb_rst_i => pulsewidth[9]~reg0.ACLR
|
973 |
|
|
wb_rst_i => pulsewidth[10]~reg0.ACLR
|
974 |
|
|
wb_rst_i => pulsewidth[11]~reg0.ACLR
|
975 |
|
|
wb_rst_i => pulsewidth[12]~reg0.ACLR
|
976 |
|
|
wb_rst_i => pulsewidth[13]~reg0.ACLR
|
977 |
|
|
wb_rst_i => pulsewidth[14]~reg0.ACLR
|
978 |
|
|
wb_rst_i => pulsewidth[15]~reg0.ACLR
|
979 |
|
|
wb_rst_i => pulsewidth[16]~reg0.ACLR
|
980 |
|
|
wb_rst_i => pulsewidth[17]~reg0.ACLR
|
981 |
|
|
wb_rst_i => pulsewidth[18]~reg0.ACLR
|
982 |
|
|
wb_rst_i => pulsewidth[19]~reg0.ACLR
|
983 |
|
|
wb_rst_i => pulsewidth[20]~reg0.ACLR
|
984 |
|
|
wb_rst_i => pulsewidth[21]~reg0.ACLR
|
985 |
|
|
wb_rst_i => pulsewidth[22]~reg0.ACLR
|
986 |
|
|
wb_rst_i => pulsewidth[23]~reg0.ACLR
|
987 |
|
|
wb_rst_i => pulsewidth[24]~reg0.ACLR
|
988 |
|
|
wb_rst_i => pulsewidth[25]~reg0.ACLR
|
989 |
|
|
wb_rst_i => pulsewidth[26]~reg0.ACLR
|
990 |
|
|
wb_rst_i => pulsewidth[27]~reg0.ACLR
|
991 |
|
|
wb_rst_i => pulsewidth[28]~reg0.ACLR
|
992 |
|
|
wb_rst_i => pulsewidth[29]~reg0.ACLR
|
993 |
|
|
wb_rst_i => pulsewidth[30]~reg0.ACLR
|
994 |
|
|
wb_rst_i => pulsewidth[31]~reg0.ACLR
|
995 |
|
|
wb_rst_i => rty.ACLR
|
996 |
|
|
wb_rst_i => err.ACLR
|
997 |
|
|
wb_rst_i => ack.ACLR
|
998 |
|
|
wb_rst_i => rst_o.DATAIN
|
999 |
|
|
wb_clk_i => rty.CLK
|
1000 |
|
|
wb_clk_i => err.CLK
|
1001 |
|
|
wb_clk_i => ack.CLK
|
1002 |
|
|
wb_clk_i => clk_o.DATAIN
|
1003 |
|
|
wb_clk_i => p2p[0]~reg0.CLK
|
1004 |
|
|
wb_clk_i => p2p[1]~reg0.CLK
|
1005 |
|
|
wb_clk_i => p2p[2]~reg0.CLK
|
1006 |
|
|
wb_clk_i => p2p[3]~reg0.CLK
|
1007 |
|
|
wb_clk_i => p2p[4]~reg0.CLK
|
1008 |
|
|
wb_clk_i => p2p[5]~reg0.CLK
|
1009 |
|
|
wb_clk_i => p2p[6]~reg0.CLK
|
1010 |
|
|
wb_clk_i => p2p[7]~reg0.CLK
|
1011 |
|
|
wb_clk_i => p2p[8]~reg0.CLK
|
1012 |
|
|
wb_clk_i => p2p[9]~reg0.CLK
|
1013 |
|
|
wb_clk_i => p2p[10]~reg0.CLK
|
1014 |
|
|
wb_clk_i => p2p[11]~reg0.CLK
|
1015 |
|
|
wb_clk_i => p2p[12]~reg0.CLK
|
1016 |
|
|
wb_clk_i => p2p[13]~reg0.CLK
|
1017 |
|
|
wb_clk_i => p2p[14]~reg0.CLK
|
1018 |
|
|
wb_clk_i => p2p[15]~reg0.CLK
|
1019 |
|
|
wb_clk_i => p2p[16]~reg0.CLK
|
1020 |
|
|
wb_clk_i => p2p[17]~reg0.CLK
|
1021 |
|
|
wb_clk_i => p2p[18]~reg0.CLK
|
1022 |
|
|
wb_clk_i => p2p[19]~reg0.CLK
|
1023 |
|
|
wb_clk_i => p2p[20]~reg0.CLK
|
1024 |
|
|
wb_clk_i => p2p[21]~reg0.CLK
|
1025 |
|
|
wb_clk_i => p2p[22]~reg0.CLK
|
1026 |
|
|
wb_clk_i => p2p[23]~reg0.CLK
|
1027 |
|
|
wb_clk_i => p2p[24]~reg0.CLK
|
1028 |
|
|
wb_clk_i => p2p[25]~reg0.CLK
|
1029 |
|
|
wb_clk_i => p2p[26]~reg0.CLK
|
1030 |
|
|
wb_clk_i => p2p[27]~reg0.CLK
|
1031 |
|
|
wb_clk_i => p2p[28]~reg0.CLK
|
1032 |
|
|
wb_clk_i => p2p[29]~reg0.CLK
|
1033 |
|
|
wb_clk_i => p2p[30]~reg0.CLK
|
1034 |
|
|
wb_clk_i => p2p[31]~reg0.CLK
|
1035 |
|
|
wb_clk_i => size[0].CLK
|
1036 |
|
|
wb_clk_i => size[1].CLK
|
1037 |
|
|
wb_clk_i => size[2].CLK
|
1038 |
|
|
wb_clk_i => size[3].CLK
|
1039 |
|
|
wb_clk_i => size[4].CLK
|
1040 |
|
|
wb_clk_i => size[5].CLK
|
1041 |
|
|
wb_clk_i => size[6].CLK
|
1042 |
|
|
wb_clk_i => size[7].CLK
|
1043 |
|
|
wb_clk_i => size[8].CLK
|
1044 |
|
|
wb_clk_i => pulsewidth[0]~reg0.CLK
|
1045 |
|
|
wb_clk_i => pulsewidth[1]~reg0.CLK
|
1046 |
|
|
wb_clk_i => pulsewidth[2]~reg0.CLK
|
1047 |
|
|
wb_clk_i => pulsewidth[3]~reg0.CLK
|
1048 |
|
|
wb_clk_i => pulsewidth[4]~reg0.CLK
|
1049 |
|
|
wb_clk_i => pulsewidth[5]~reg0.CLK
|
1050 |
|
|
wb_clk_i => pulsewidth[6]~reg0.CLK
|
1051 |
|
|
wb_clk_i => pulsewidth[7]~reg0.CLK
|
1052 |
|
|
wb_clk_i => pulsewidth[8]~reg0.CLK
|
1053 |
|
|
wb_clk_i => pulsewidth[9]~reg0.CLK
|
1054 |
|
|
wb_clk_i => pulsewidth[10]~reg0.CLK
|
1055 |
|
|
wb_clk_i => pulsewidth[11]~reg0.CLK
|
1056 |
|
|
wb_clk_i => pulsewidth[12]~reg0.CLK
|
1057 |
|
|
wb_clk_i => pulsewidth[13]~reg0.CLK
|
1058 |
|
|
wb_clk_i => pulsewidth[14]~reg0.CLK
|
1059 |
|
|
wb_clk_i => pulsewidth[15]~reg0.CLK
|
1060 |
|
|
wb_clk_i => pulsewidth[16]~reg0.CLK
|
1061 |
|
|
wb_clk_i => pulsewidth[17]~reg0.CLK
|
1062 |
|
|
wb_clk_i => pulsewidth[18]~reg0.CLK
|
1063 |
|
|
wb_clk_i => pulsewidth[19]~reg0.CLK
|
1064 |
|
|
wb_clk_i => pulsewidth[20]~reg0.CLK
|
1065 |
|
|
wb_clk_i => pulsewidth[21]~reg0.CLK
|
1066 |
|
|
wb_clk_i => pulsewidth[22]~reg0.CLK
|
1067 |
|
|
wb_clk_i => pulsewidth[23]~reg0.CLK
|
1068 |
|
|
wb_clk_i => pulsewidth[24]~reg0.CLK
|
1069 |
|
|
wb_clk_i => pulsewidth[25]~reg0.CLK
|
1070 |
|
|
wb_clk_i => pulsewidth[26]~reg0.CLK
|
1071 |
|
|
wb_clk_i => pulsewidth[27]~reg0.CLK
|
1072 |
|
|
wb_clk_i => pulsewidth[28]~reg0.CLK
|
1073 |
|
|
wb_clk_i => pulsewidth[29]~reg0.CLK
|
1074 |
|
|
wb_clk_i => pulsewidth[30]~reg0.CLK
|
1075 |
|
|
wb_clk_i => pulsewidth[31]~reg0.CLK
|
1076 |
|
|
wb_stb_i => err_int.IN0
|
1077 |
|
|
wb_stb_i => rty_int.IN1
|
1078 |
|
|
wb_stb_i => wb_dat_o.IN0
|
1079 |
|
|
wb_ack_o <= ack.DB_MAX_OUTPUT_PORT_TYPE
|
1080 |
|
|
wb_addr_i[0] => err_int.IN1
|
1081 |
|
|
wb_addr_i[0] => Equal0.IN0
|
1082 |
|
|
wb_addr_i[0] => Equal1.IN1
|
1083 |
|
|
wb_addr_i[0] => Equal2.IN31
|
1084 |
|
|
wb_addr_i[0] => Equal3.IN5
|
1085 |
|
|
wb_addr_i[1] => Equal0.IN31
|
1086 |
|
|
wb_addr_i[1] => Equal1.IN0
|
1087 |
|
|
wb_addr_i[1] => Equal2.IN0
|
1088 |
|
|
wb_addr_i[1] => Equal3.IN4
|
1089 |
|
|
wb_addr_i[2] => WideNor0.IN0
|
1090 |
|
|
wb_addr_i[2] => Equal0.IN30
|
1091 |
|
|
wb_addr_i[2] => Equal1.IN31
|
1092 |
|
|
wb_addr_i[2] => Equal2.IN30
|
1093 |
|
|
wb_addr_i[2] => Equal3.IN3
|
1094 |
|
|
wb_addr_i[3] => WideNor0.IN1
|
1095 |
|
|
wb_addr_i[3] => Equal0.IN29
|
1096 |
|
|
wb_addr_i[3] => Equal1.IN30
|
1097 |
|
|
wb_addr_i[3] => Equal2.IN29
|
1098 |
|
|
wb_addr_i[3] => Equal3.IN2
|
1099 |
|
|
wb_addr_i[4] => WideNor0.IN2
|
1100 |
|
|
wb_addr_i[4] => Equal0.IN28
|
1101 |
|
|
wb_addr_i[4] => Equal1.IN29
|
1102 |
|
|
wb_addr_i[4] => Equal2.IN28
|
1103 |
|
|
wb_addr_i[4] => Equal3.IN1
|
1104 |
|
|
wb_addr_i[5] => WideNor0.IN3
|
1105 |
|
|
wb_addr_i[5] => Equal0.IN27
|
1106 |
|
|
wb_addr_i[5] => Equal1.IN28
|
1107 |
|
|
wb_addr_i[5] => Equal2.IN27
|
1108 |
|
|
wb_addr_i[5] => Equal3.IN0
|
1109 |
|
|
wb_we_i => err_int.IN1
|
1110 |
|
|
wb_we_i => rty_int.IN1
|
1111 |
|
|
wb_we_i => always5.IN1
|
1112 |
|
|
wb_we_i => wb_dat_o.IN1
|
1113 |
|
|
wb_dat_i[0] => dat_o[0].DATAIN
|
1114 |
|
|
wb_dat_i[0] => pulsewidth[0]~reg0.DATAIN
|
1115 |
|
|
wb_dat_i[0] => p2p[0]~reg0.DATAIN
|
1116 |
|
|
wb_dat_i[0] => size[0].DATAIN
|
1117 |
|
|
wb_dat_i[1] => dat_o[1].DATAIN
|
1118 |
|
|
wb_dat_i[1] => pulsewidth[1]~reg0.DATAIN
|
1119 |
|
|
wb_dat_i[1] => p2p[1]~reg0.DATAIN
|
1120 |
|
|
wb_dat_i[1] => size[1].DATAIN
|
1121 |
|
|
wb_dat_i[2] => dat_o[2].DATAIN
|
1122 |
|
|
wb_dat_i[2] => pulsewidth[2]~reg0.DATAIN
|
1123 |
|
|
wb_dat_i[2] => p2p[2]~reg0.DATAIN
|
1124 |
|
|
wb_dat_i[2] => size[2].DATAIN
|
1125 |
|
|
wb_dat_i[3] => dat_o[3].DATAIN
|
1126 |
|
|
wb_dat_i[3] => pulsewidth[3]~reg0.DATAIN
|
1127 |
|
|
wb_dat_i[3] => p2p[3]~reg0.DATAIN
|
1128 |
|
|
wb_dat_i[3] => size[3].DATAIN
|
1129 |
|
|
wb_dat_i[4] => dat_o[4].DATAIN
|
1130 |
|
|
wb_dat_i[4] => pulsewidth[4]~reg0.DATAIN
|
1131 |
|
|
wb_dat_i[4] => p2p[4]~reg0.DATAIN
|
1132 |
|
|
wb_dat_i[4] => size[4].DATAIN
|
1133 |
|
|
wb_dat_i[5] => dat_o[5].DATAIN
|
1134 |
|
|
wb_dat_i[5] => pulsewidth[5]~reg0.DATAIN
|
1135 |
|
|
wb_dat_i[5] => p2p[5]~reg0.DATAIN
|
1136 |
|
|
wb_dat_i[5] => size[5].DATAIN
|
1137 |
|
|
wb_dat_i[6] => dat_o[6].DATAIN
|
1138 |
|
|
wb_dat_i[6] => pulsewidth[6]~reg0.DATAIN
|
1139 |
|
|
wb_dat_i[6] => p2p[6]~reg0.DATAIN
|
1140 |
|
|
wb_dat_i[6] => size[6].DATAIN
|
1141 |
|
|
wb_dat_i[7] => size.DATAB
|
1142 |
|
|
wb_dat_i[7] => dat_o[7].DATAIN
|
1143 |
|
|
wb_dat_i[7] => pulsewidth[7]~reg0.DATAIN
|
1144 |
|
|
wb_dat_i[7] => p2p[7]~reg0.DATAIN
|
1145 |
|
|
wb_dat_i[8] => size.DATAB
|
1146 |
|
|
wb_dat_i[8] => dat_o[8].DATAIN
|
1147 |
|
|
wb_dat_i[8] => pulsewidth[8]~reg0.DATAIN
|
1148 |
|
|
wb_dat_i[8] => p2p[8]~reg0.DATAIN
|
1149 |
|
|
wb_dat_i[9] => dat_o[9].DATAIN
|
1150 |
|
|
wb_dat_i[9] => pulsewidth[9]~reg0.DATAIN
|
1151 |
|
|
wb_dat_i[9] => p2p[9]~reg0.DATAIN
|
1152 |
|
|
wb_dat_i[10] => dat_o[10].DATAIN
|
1153 |
|
|
wb_dat_i[10] => pulsewidth[10]~reg0.DATAIN
|
1154 |
|
|
wb_dat_i[10] => p2p[10]~reg0.DATAIN
|
1155 |
|
|
wb_dat_i[11] => dat_o[11].DATAIN
|
1156 |
|
|
wb_dat_i[11] => pulsewidth[11]~reg0.DATAIN
|
1157 |
|
|
wb_dat_i[11] => p2p[11]~reg0.DATAIN
|
1158 |
|
|
wb_dat_i[12] => dat_o[12].DATAIN
|
1159 |
|
|
wb_dat_i[12] => pulsewidth[12]~reg0.DATAIN
|
1160 |
|
|
wb_dat_i[12] => p2p[12]~reg0.DATAIN
|
1161 |
|
|
wb_dat_i[13] => dat_o[13].DATAIN
|
1162 |
|
|
wb_dat_i[13] => pulsewidth[13]~reg0.DATAIN
|
1163 |
|
|
wb_dat_i[13] => p2p[13]~reg0.DATAIN
|
1164 |
|
|
wb_dat_i[14] => dat_o[14].DATAIN
|
1165 |
|
|
wb_dat_i[14] => pulsewidth[14]~reg0.DATAIN
|
1166 |
|
|
wb_dat_i[14] => p2p[14]~reg0.DATAIN
|
1167 |
|
|
wb_dat_i[15] => dat_o[15].DATAIN
|
1168 |
|
|
wb_dat_i[15] => pulsewidth[15]~reg0.DATAIN
|
1169 |
|
|
wb_dat_i[15] => p2p[15]~reg0.DATAIN
|
1170 |
|
|
wb_dat_i[16] => dat_o[16].DATAIN
|
1171 |
|
|
wb_dat_i[16] => pulsewidth[16]~reg0.DATAIN
|
1172 |
|
|
wb_dat_i[16] => p2p[16]~reg0.DATAIN
|
1173 |
|
|
wb_dat_i[17] => dat_o[17].DATAIN
|
1174 |
|
|
wb_dat_i[17] => pulsewidth[17]~reg0.DATAIN
|
1175 |
|
|
wb_dat_i[17] => p2p[17]~reg0.DATAIN
|
1176 |
|
|
wb_dat_i[18] => dat_o[18].DATAIN
|
1177 |
|
|
wb_dat_i[18] => pulsewidth[18]~reg0.DATAIN
|
1178 |
|
|
wb_dat_i[18] => p2p[18]~reg0.DATAIN
|
1179 |
|
|
wb_dat_i[19] => dat_o[19].DATAIN
|
1180 |
|
|
wb_dat_i[19] => pulsewidth[19]~reg0.DATAIN
|
1181 |
|
|
wb_dat_i[19] => p2p[19]~reg0.DATAIN
|
1182 |
|
|
wb_dat_i[20] => dat_o[20].DATAIN
|
1183 |
|
|
wb_dat_i[20] => pulsewidth[20]~reg0.DATAIN
|
1184 |
|
|
wb_dat_i[20] => p2p[20]~reg0.DATAIN
|
1185 |
|
|
wb_dat_i[21] => dat_o[21].DATAIN
|
1186 |
|
|
wb_dat_i[21] => pulsewidth[21]~reg0.DATAIN
|
1187 |
|
|
wb_dat_i[21] => p2p[21]~reg0.DATAIN
|
1188 |
|
|
wb_dat_i[22] => dat_o[22].DATAIN
|
1189 |
|
|
wb_dat_i[22] => pulsewidth[22]~reg0.DATAIN
|
1190 |
|
|
wb_dat_i[22] => p2p[22]~reg0.DATAIN
|
1191 |
|
|
wb_dat_i[23] => dat_o[23].DATAIN
|
1192 |
|
|
wb_dat_i[23] => pulsewidth[23]~reg0.DATAIN
|
1193 |
|
|
wb_dat_i[23] => p2p[23]~reg0.DATAIN
|
1194 |
|
|
wb_dat_i[24] => dat_o[24].DATAIN
|
1195 |
|
|
wb_dat_i[24] => pulsewidth[24]~reg0.DATAIN
|
1196 |
|
|
wb_dat_i[24] => p2p[24]~reg0.DATAIN
|
1197 |
|
|
wb_dat_i[25] => dat_o[25].DATAIN
|
1198 |
|
|
wb_dat_i[25] => pulsewidth[25]~reg0.DATAIN
|
1199 |
|
|
wb_dat_i[25] => p2p[25]~reg0.DATAIN
|
1200 |
|
|
wb_dat_i[26] => dat_o[26].DATAIN
|
1201 |
|
|
wb_dat_i[26] => pulsewidth[26]~reg0.DATAIN
|
1202 |
|
|
wb_dat_i[26] => p2p[26]~reg0.DATAIN
|
1203 |
|
|
wb_dat_i[27] => dat_o[27].DATAIN
|
1204 |
|
|
wb_dat_i[27] => pulsewidth[27]~reg0.DATAIN
|
1205 |
|
|
wb_dat_i[27] => p2p[27]~reg0.DATAIN
|
1206 |
|
|
wb_dat_i[28] => dat_o[28].DATAIN
|
1207 |
|
|
wb_dat_i[28] => pulsewidth[28]~reg0.DATAIN
|
1208 |
|
|
wb_dat_i[28] => p2p[28]~reg0.DATAIN
|
1209 |
|
|
wb_dat_i[29] => dat_o[29].DATAIN
|
1210 |
|
|
wb_dat_i[29] => pulsewidth[29]~reg0.DATAIN
|
1211 |
|
|
wb_dat_i[29] => p2p[29]~reg0.DATAIN
|
1212 |
|
|
wb_dat_i[30] => dat_o[30].DATAIN
|
1213 |
|
|
wb_dat_i[30] => pulsewidth[30]~reg0.DATAIN
|
1214 |
|
|
wb_dat_i[30] => p2p[30]~reg0.DATAIN
|
1215 |
|
|
wb_dat_i[31] => dat_o[31].DATAIN
|
1216 |
|
|
wb_dat_i[31] => pulsewidth[31]~reg0.DATAIN
|
1217 |
|
|
wb_dat_i[31] => p2p[31]~reg0.DATAIN
|
1218 |
|
|
wb_sel_i[0] => ~NO_FANOUT~
|
1219 |
|
|
wb_sel_i[1] => ~NO_FANOUT~
|
1220 |
|
|
wb_sel_i[2] => ~NO_FANOUT~
|
1221 |
|
|
wb_sel_i[3] => ~NO_FANOUT~
|
1222 |
|
|
wb_dat_o[0] <= wb_dat_o[0].DB_MAX_OUTPUT_PORT_TYPE
|
1223 |
|
|
wb_dat_o[1] <= wb_dat_o[1].DB_MAX_OUTPUT_PORT_TYPE
|
1224 |
|
|
wb_dat_o[2] <= wb_dat_o[2].DB_MAX_OUTPUT_PORT_TYPE
|
1225 |
|
|
wb_dat_o[3] <= wb_dat_o[3].DB_MAX_OUTPUT_PORT_TYPE
|
1226 |
|
|
wb_dat_o[4] <= wb_dat_o[4].DB_MAX_OUTPUT_PORT_TYPE
|
1227 |
|
|
wb_dat_o[5] <= wb_dat_o[5].DB_MAX_OUTPUT_PORT_TYPE
|
1228 |
|
|
wb_dat_o[6] <= wb_dat_o[6].DB_MAX_OUTPUT_PORT_TYPE
|
1229 |
|
|
wb_dat_o[7] <= wb_dat_o[7].DB_MAX_OUTPUT_PORT_TYPE
|
1230 |
|
|
wb_dat_o[8] <= wb_dat_o[8].DB_MAX_OUTPUT_PORT_TYPE
|
1231 |
|
|
wb_dat_o[9] <= wb_dat_o[9].DB_MAX_OUTPUT_PORT_TYPE
|
1232 |
|
|
wb_dat_o[10] <= wb_dat_o[10].DB_MAX_OUTPUT_PORT_TYPE
|
1233 |
|
|
wb_dat_o[11] <= wb_dat_o[11].DB_MAX_OUTPUT_PORT_TYPE
|
1234 |
|
|
wb_dat_o[12] <= wb_dat_o[12].DB_MAX_OUTPUT_PORT_TYPE
|
1235 |
|
|
wb_dat_o[13] <= wb_dat_o[13].DB_MAX_OUTPUT_PORT_TYPE
|
1236 |
|
|
wb_dat_o[14] <= wb_dat_o[14].DB_MAX_OUTPUT_PORT_TYPE
|
1237 |
|
|
wb_dat_o[15] <= wb_dat_o[15].DB_MAX_OUTPUT_PORT_TYPE
|
1238 |
|
|
wb_dat_o[16] <= wb_dat_o[16].DB_MAX_OUTPUT_PORT_TYPE
|
1239 |
|
|
wb_dat_o[17] <= wb_dat_o[17].DB_MAX_OUTPUT_PORT_TYPE
|
1240 |
|
|
wb_dat_o[18] <= wb_dat_o[18].DB_MAX_OUTPUT_PORT_TYPE
|
1241 |
|
|
wb_dat_o[19] <= wb_dat_o[19].DB_MAX_OUTPUT_PORT_TYPE
|
1242 |
|
|
wb_dat_o[20] <= wb_dat_o[20].DB_MAX_OUTPUT_PORT_TYPE
|
1243 |
|
|
wb_dat_o[21] <= wb_dat_o[21].DB_MAX_OUTPUT_PORT_TYPE
|
1244 |
|
|
wb_dat_o[22] <= wb_dat_o[22].DB_MAX_OUTPUT_PORT_TYPE
|
1245 |
|
|
wb_dat_o[23] <= wb_dat_o[23].DB_MAX_OUTPUT_PORT_TYPE
|
1246 |
|
|
wb_dat_o[24] <= wb_dat_o[24].DB_MAX_OUTPUT_PORT_TYPE
|
1247 |
|
|
wb_dat_o[25] <= wb_dat_o[25].DB_MAX_OUTPUT_PORT_TYPE
|
1248 |
|
|
wb_dat_o[26] <= wb_dat_o[26].DB_MAX_OUTPUT_PORT_TYPE
|
1249 |
|
|
wb_dat_o[27] <= wb_dat_o[27].DB_MAX_OUTPUT_PORT_TYPE
|
1250 |
|
|
wb_dat_o[28] <= wb_dat_o[28].DB_MAX_OUTPUT_PORT_TYPE
|
1251 |
|
|
wb_dat_o[29] <= wb_dat_o[29].DB_MAX_OUTPUT_PORT_TYPE
|
1252 |
|
|
wb_dat_o[30] <= wb_dat_o[30].DB_MAX_OUTPUT_PORT_TYPE
|
1253 |
|
|
wb_dat_o[31] <= wb_dat_o[31].DB_MAX_OUTPUT_PORT_TYPE
|
1254 |
|
|
wb_cyc_i => err_int.IN1
|
1255 |
|
|
wb_cyc_i => rty_int.IN1
|
1256 |
|
|
wb_cyc_i => wb_dat_o.IN1
|
1257 |
|
|
wb_cti_i[0] => ~NO_FANOUT~
|
1258 |
|
|
wb_cti_i[1] => ~NO_FANOUT~
|
1259 |
|
|
wb_cti_i[2] => ~NO_FANOUT~
|
1260 |
|
|
wb_err_o <= err.DB_MAX_OUTPUT_PORT_TYPE
|
1261 |
|
|
wb_rty_o <= rty.DB_MAX_OUTPUT_PORT_TYPE
|
1262 |
|
|
rst_o <= wb_rst_i.DB_MAX_OUTPUT_PORT_TYPE
|
1263 |
|
|
dat_o[0] <= wb_dat_i[0].DB_MAX_OUTPUT_PORT_TYPE
|
1264 |
|
|
dat_o[1] <= wb_dat_i[1].DB_MAX_OUTPUT_PORT_TYPE
|
1265 |
|
|
dat_o[2] <= wb_dat_i[2].DB_MAX_OUTPUT_PORT_TYPE
|
1266 |
|
|
dat_o[3] <= wb_dat_i[3].DB_MAX_OUTPUT_PORT_TYPE
|
1267 |
|
|
dat_o[4] <= wb_dat_i[4].DB_MAX_OUTPUT_PORT_TYPE
|
1268 |
|
|
dat_o[5] <= wb_dat_i[5].DB_MAX_OUTPUT_PORT_TYPE
|
1269 |
|
|
dat_o[6] <= wb_dat_i[6].DB_MAX_OUTPUT_PORT_TYPE
|
1270 |
|
|
dat_o[7] <= wb_dat_i[7].DB_MAX_OUTPUT_PORT_TYPE
|
1271 |
|
|
dat_o[8] <= wb_dat_i[8].DB_MAX_OUTPUT_PORT_TYPE
|
1272 |
|
|
dat_o[9] <= wb_dat_i[9].DB_MAX_OUTPUT_PORT_TYPE
|
1273 |
|
|
dat_o[10] <= wb_dat_i[10].DB_MAX_OUTPUT_PORT_TYPE
|
1274 |
|
|
dat_o[11] <= wb_dat_i[11].DB_MAX_OUTPUT_PORT_TYPE
|
1275 |
|
|
dat_o[12] <= wb_dat_i[12].DB_MAX_OUTPUT_PORT_TYPE
|
1276 |
|
|
dat_o[13] <= wb_dat_i[13].DB_MAX_OUTPUT_PORT_TYPE
|
1277 |
|
|
dat_o[14] <= wb_dat_i[14].DB_MAX_OUTPUT_PORT_TYPE
|
1278 |
|
|
dat_o[15] <= wb_dat_i[15].DB_MAX_OUTPUT_PORT_TYPE
|
1279 |
|
|
dat_o[16] <= wb_dat_i[16].DB_MAX_OUTPUT_PORT_TYPE
|
1280 |
|
|
dat_o[17] <= wb_dat_i[17].DB_MAX_OUTPUT_PORT_TYPE
|
1281 |
|
|
dat_o[18] <= wb_dat_i[18].DB_MAX_OUTPUT_PORT_TYPE
|
1282 |
|
|
dat_o[19] <= wb_dat_i[19].DB_MAX_OUTPUT_PORT_TYPE
|
1283 |
|
|
dat_o[20] <= wb_dat_i[20].DB_MAX_OUTPUT_PORT_TYPE
|
1284 |
|
|
dat_o[21] <= wb_dat_i[21].DB_MAX_OUTPUT_PORT_TYPE
|
1285 |
|
|
dat_o[22] <= wb_dat_i[22].DB_MAX_OUTPUT_PORT_TYPE
|
1286 |
|
|
dat_o[23] <= wb_dat_i[23].DB_MAX_OUTPUT_PORT_TYPE
|
1287 |
|
|
dat_o[24] <= wb_dat_i[24].DB_MAX_OUTPUT_PORT_TYPE
|
1288 |
|
|
dat_o[25] <= wb_dat_i[25].DB_MAX_OUTPUT_PORT_TYPE
|
1289 |
|
|
dat_o[26] <= wb_dat_i[26].DB_MAX_OUTPUT_PORT_TYPE
|
1290 |
|
|
dat_o[27] <= wb_dat_i[27].DB_MAX_OUTPUT_PORT_TYPE
|
1291 |
|
|
dat_o[28] <= wb_dat_i[28].DB_MAX_OUTPUT_PORT_TYPE
|
1292 |
|
|
dat_o[29] <= wb_dat_i[29].DB_MAX_OUTPUT_PORT_TYPE
|
1293 |
|
|
dat_o[30] <= wb_dat_i[30].DB_MAX_OUTPUT_PORT_TYPE
|
1294 |
|
|
dat_o[31] <= wb_dat_i[31].DB_MAX_OUTPUT_PORT_TYPE
|
1295 |
|
|
dat_i[0] => ~NO_FANOUT~
|
1296 |
|
|
dat_i[1] => ~NO_FANOUT~
|
1297 |
|
|
dat_i[2] => ~NO_FANOUT~
|
1298 |
|
|
dat_i[3] => ~NO_FANOUT~
|
1299 |
|
|
dat_i[4] => ~NO_FANOUT~
|
1300 |
|
|
dat_i[5] => ~NO_FANOUT~
|
1301 |
|
|
dat_i[6] => ~NO_FANOUT~
|
1302 |
|
|
dat_i[7] => ~NO_FANOUT~
|
1303 |
|
|
dat_i[8] => ~NO_FANOUT~
|
1304 |
|
|
dat_i[9] => ~NO_FANOUT~
|
1305 |
|
|
dat_i[10] => ~NO_FANOUT~
|
1306 |
|
|
dat_i[11] => ~NO_FANOUT~
|
1307 |
|
|
dat_i[12] => ~NO_FANOUT~
|
1308 |
|
|
dat_i[13] => ~NO_FANOUT~
|
1309 |
|
|
dat_i[14] => ~NO_FANOUT~
|
1310 |
|
|
dat_i[15] => ~NO_FANOUT~
|
1311 |
|
|
dat_i[16] => ~NO_FANOUT~
|
1312 |
|
|
dat_i[17] => ~NO_FANOUT~
|
1313 |
|
|
dat_i[18] => ~NO_FANOUT~
|
1314 |
|
|
dat_i[19] => ~NO_FANOUT~
|
1315 |
|
|
dat_i[20] => ~NO_FANOUT~
|
1316 |
|
|
dat_i[21] => ~NO_FANOUT~
|
1317 |
|
|
dat_i[22] => ~NO_FANOUT~
|
1318 |
|
|
dat_i[23] => ~NO_FANOUT~
|
1319 |
|
|
dat_i[24] => ~NO_FANOUT~
|
1320 |
|
|
dat_i[25] => ~NO_FANOUT~
|
1321 |
|
|
dat_i[26] => ~NO_FANOUT~
|
1322 |
|
|
dat_i[27] => ~NO_FANOUT~
|
1323 |
|
|
dat_i[28] => ~NO_FANOUT~
|
1324 |
|
|
dat_i[29] => ~NO_FANOUT~
|
1325 |
|
|
dat_i[30] => ~NO_FANOUT~
|
1326 |
|
|
dat_i[31] => ~NO_FANOUT~
|
1327 |
|
|
msgLength[0] <= size[0].DB_MAX_OUTPUT_PORT_TYPE
|
1328 |
|
|
msgLength[1] <= size[1].DB_MAX_OUTPUT_PORT_TYPE
|
1329 |
|
|
msgLength[2] <= size[2].DB_MAX_OUTPUT_PORT_TYPE
|
1330 |
|
|
msgLength[3] <= size[3].DB_MAX_OUTPUT_PORT_TYPE
|
1331 |
|
|
msgLength[4] <= size[4].DB_MAX_OUTPUT_PORT_TYPE
|
1332 |
|
|
msgLength[5] <= size[5].DB_MAX_OUTPUT_PORT_TYPE
|
1333 |
|
|
msgLength[6] <= size[6].DB_MAX_OUTPUT_PORT_TYPE
|
1334 |
|
|
start_tx <= size[7].DB_MAX_OUTPUT_PORT_TYPE
|
1335 |
|
|
p2p[0] <= p2p[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
1336 |
|
|
p2p[1] <= p2p[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
1337 |
|
|
p2p[2] <= p2p[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
1338 |
|
|
p2p[3] <= p2p[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
1339 |
|
|
p2p[4] <= p2p[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
1340 |
|
|
p2p[5] <= p2p[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
1341 |
|
|
p2p[6] <= p2p[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
1342 |
|
|
p2p[7] <= p2p[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
1343 |
|
|
p2p[8] <= p2p[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
1344 |
|
|
p2p[9] <= p2p[9]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
1345 |
|
|
p2p[10] <= p2p[10]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
1346 |
|
|
p2p[11] <= p2p[11]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
1347 |
|
|
p2p[12] <= p2p[12]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
1348 |
|
|
p2p[13] <= p2p[13]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
1349 |
|
|
p2p[14] <= p2p[14]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
1350 |
|
|
p2p[15] <= p2p[15]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
1351 |
|
|
p2p[16] <= p2p[16]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
1352 |
|
|
p2p[17] <= p2p[17]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
1353 |
|
|
p2p[18] <= p2p[18]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
1354 |
|
|
p2p[19] <= p2p[19]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
1355 |
|
|
p2p[20] <= p2p[20]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
1356 |
|
|
p2p[21] <= p2p[21]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
1357 |
|
|
p2p[22] <= p2p[22]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
1358 |
|
|
p2p[23] <= p2p[23]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
1359 |
|
|
p2p[24] <= p2p[24]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
1360 |
|
|
p2p[25] <= p2p[25]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
1361 |
|
|
p2p[26] <= p2p[26]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
1362 |
|
|
p2p[27] <= p2p[27]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
1363 |
|
|
p2p[28] <= p2p[28]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
1364 |
|
|
p2p[29] <= p2p[29]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
1365 |
|
|
p2p[30] <= p2p[30]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
1366 |
|
|
p2p[31] <= p2p[31]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
1367 |
|
|
pulsewidth[0] <= pulsewidth[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
1368 |
|
|
pulsewidth[1] <= pulsewidth[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
1369 |
|
|
pulsewidth[2] <= pulsewidth[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
1370 |
|
|
pulsewidth[3] <= pulsewidth[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
1371 |
|
|
pulsewidth[4] <= pulsewidth[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
1372 |
|
|
pulsewidth[5] <= pulsewidth[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
1373 |
|
|
pulsewidth[6] <= pulsewidth[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
1374 |
|
|
pulsewidth[7] <= pulsewidth[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
1375 |
|
|
pulsewidth[8] <= pulsewidth[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
1376 |
|
|
pulsewidth[9] <= pulsewidth[9]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
1377 |
|
|
pulsewidth[10] <= pulsewidth[10]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
1378 |
|
|
pulsewidth[11] <= pulsewidth[11]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
1379 |
|
|
pulsewidth[12] <= pulsewidth[12]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
1380 |
|
|
pulsewidth[13] <= pulsewidth[13]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
1381 |
|
|
pulsewidth[14] <= pulsewidth[14]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
1382 |
|
|
pulsewidth[15] <= pulsewidth[15]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
1383 |
|
|
pulsewidth[16] <= pulsewidth[16]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
1384 |
|
|
pulsewidth[17] <= pulsewidth[17]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
1385 |
|
|
pulsewidth[18] <= pulsewidth[18]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
1386 |
|
|
pulsewidth[19] <= pulsewidth[19]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
1387 |
|
|
pulsewidth[20] <= pulsewidth[20]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
1388 |
|
|
pulsewidth[21] <= pulsewidth[21]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
1389 |
|
|
pulsewidth[22] <= pulsewidth[22]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
1390 |
|
|
pulsewidth[23] <= pulsewidth[23]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
1391 |
|
|
pulsewidth[24] <= pulsewidth[24]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
1392 |
|
|
pulsewidth[25] <= pulsewidth[25]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
1393 |
|
|
pulsewidth[26] <= pulsewidth[26]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
1394 |
|
|
pulsewidth[27] <= pulsewidth[27]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
1395 |
|
|
pulsewidth[28] <= pulsewidth[28]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
1396 |
|
|
pulsewidth[29] <= pulsewidth[29]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
1397 |
|
|
pulsewidth[30] <= pulsewidth[30]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
1398 |
|
|
pulsewidth[31] <= pulsewidth[31]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
1399 |
|
|
clk_o <= wb_clk_i.DB_MAX_OUTPUT_PORT_TYPE
|
1400 |
|
|
full => err_int.IN1
|
1401 |
|
|
full => wb_wr_en.IN1
|
1402 |
|
|
lock_cfg_i => rty_int.IN1
|
1403 |
|
|
lock_cfg_i => ack.IN1
|
1404 |
|
|
lock_cfg_i => always5.IN1
|
1405 |
|
|
wb_wr_en <= wb_wr_en.DB_MAX_OUTPUT_PORT_TYPE
|
1406 |
|
|
rst_FIFO <= size[8].DB_MAX_OUTPUT_PORT_TYPE
|
1407 |
|
|
|
1408 |
|
|
|