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[/] [wiegand_ctl/] [trunk/] [syn/] [xilinx/] [wiegand_tx/] [vivado/] [wiegand_tx_top/] [wiegand_tx_top.srcs/] [constrs_1/] [new/] [wiegand_tx_top.xdc] - Blame information for rev 17

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#only true IO are zero_o and one_o pins; rest stay on-chip through WB bus
set_property IOSTANDARD LVCMOS18 [get_ports {one_o zero_o}]
#set_property PACKAGE_PIN  [get_ports one_o]
#set_property PACKAGE_PIN  [get_ports zero_o]
 
#timing constraints
#only one clock, and it's the WB clock.
create_clock �period 10 [get_ports wb_clk_i]

Line No.	Rev	Author	Line
1	17	jeaander	`#only true IO are zero_o and one_o pins; rest stay on-chip through WB bus`
2			`set_property IOSTANDARD LVCMOS18 [get_ports {one_o zero_o}]`
3			`#set_property PACKAGE_PIN [get_ports one_o]`
4			`#set_property PACKAGE_PIN [get_ports zero_o]`
5
6			`#timing constraints`
7			`#only one clock, and it's the WB clock.`
8			`create_clock �period 10 [get_ports wb_clk_i]`

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Subversion Repositories wiegand_ctl

[/] [wiegand_ctl/] [trunk/] [syn/] [xilinx/] [wiegand_tx/] [vivado/] [wiegand_tx_top/] [wiegand_tx_top.srcs/] [constrs_1/] [new/] [wiegand_tx_top.xdc] - Blame information for rev 17