Subversion Repositories wishbone_spi_flash_interface

--------------------------------------------------------------------------

-- Package of bit sync and DPLL components

--

--

--

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.NUMERIC_STD.ALL;

use IEEE.MATH_REAL.ALL;

library work;

use work.convert_pack.all;

package spi_pack is

  component spi_flash_interface

    generic(

      NUM_CS        : natural;  -- Number of SPI device selects

      DEF_R_0       : unsigned(31 downto 0); -- SPI Chip Selects

      DEF_R_1       : unsigned(31 downto 0); -- SPI Command byte

      DEF_R_2       : unsigned(31 downto 0)  -- SPI Address (24 bits)

    );

    port (

      -- System Clock and Clock Enable

      sys_rst_n  : in  std_logic;

      sys_clk    : in  std_logic;

      sys_clk_en : in  std_logic;

      -- Bus interface

      adr_i      : in  unsigned(3 downto 0);

      sel_i      : in  std_logic;

      we_i       : in  std_logic;

      dat_i      : in  unsigned(31 downto 0);

      dat_o      : out unsigned(31 downto 0);

      ack_o      : out std_logic;

      -- SPI interface

      -- "hold" and "WP" are not implemented.

      spi_cs_o   : out unsigned(NUM_CS-1 downto 0);

      spi_sck_o  : out std_logic;

      spi_so_o   : out std_logic;

      spi_si_i   : in  std_logic

    );

  end component;

  component spi_flash_sys_init

    generic(

      SYS_CLK_RATE : real;

      FLASH_IDLE   : natural;  -- Number of ms idle before RAM-mapped FLASH operation closeout

      DECODE_BITS  : natural;  -- Number of init address upper-bits decoded to select individual SPI devices.

      DEF_R_0      : unsigned(31 downto 0) := str2u("00000001",32); -- low-level SPI Chip Select control

      DEF_R_1      : unsigned(31 downto 0) := str2u("00000003",32); -- low-level SPI Command byte

      DEF_R_2      : unsigned(31 downto 0) := str2u("007F0000",32); -- low-level SPI Address

      DEF_R_3      : unsigned(31 downto 0) := str2u("007F0000",32); -- Init Address

      DEF_R_4      : unsigned(31 downto 0) := str2u("00000100",32); -- Init Bytes

      DEF_R_5      : unsigned(31 downto 0) := str2u("00000001",32)  -- Init Settings

    );

    port (

      -- System Clock and Clock Enable

      sys_rst_n  : in  std_logic;

      sys_clk    : in  std_logic;

      sys_clk_en : in  std_logic;

      -- Bus interface

      adr_i      : in  unsigned(3 downto 0);

      sel_i      : in  std_logic;

      we_i       : in  std_logic;

      dat_i      : in  unsigned(31 downto 0);

      dat_o      : out unsigned(31 downto 0);

      ack_o      : out std_logic;

      -- RAM mapped SPI FLASH access port

      -- (fl_ack_o may take ~5ms during page program)

      fl_adr_i   : in  unsigned(31 downto 0);

      fl_sel_i   : in  std_logic;

      fl_we_i    : in  std_logic;

      fl_dat_i   : in  unsigned(7 downto 0);

      fl_dat_o   : out unsigned(7 downto 0);

      fl_ack_o   : out std_logic;

      -- Init data output port

      init_adr_o : out unsigned(31 downto 0);

      init_dat_o : out unsigned(7 downto 0);

      init_cyc_o : out std_logic;

      init_ack_i : in  std_logic;

      init_fin_o : out std_logic; -- Stays high when init is finished

      -- SPI interface

      -- "hold" and "WP" are not implemented.

      spi_adr_o  : out unsigned(DECODE_BITS-1 downto 0);

      spi_cs_o   : out std_logic;

      spi_sck_o  : out std_logic;

      spi_so_o   : out std_logic;

      spi_si_i   : in  std_logic

    );

  end component;

  component spi_flash_simulator

    generic(

      SYS_CLK_RATE   : real;

      FLASH_ADR_BITS : natural; -- Flash memory size is based on this

      FLASH_INIT     : string   -- Default RX packet digestion settings

    );

    port (

      -- System Clock and Clock Enable

      sys_rst_n  : in  std_logic;

      sys_clk    : in  std_logic;

      sys_clk_en : in  std_logic;

      -- SPI interface

      -- "hold" and "WP" are not implemented.

      spi_cs_i   : in  std_logic;

      spi_sck_i  : in  std_logic;

      spi_si_i   : in  std_logic;

      spi_so_o   : out std_logic

    );

  end component;

end spi_pack;

-------------------------------------------------------------------------------

-- SPI Flash Interface

-------------------------------------------------------------------------------

--

-- Author: John Clayton

-- Date  : July 26, 2013 Created this module starting with code copied from

--                       another module.

--         July 31, 2013 Modified this module in simulation, until it looked

--                       correct.  Tested in hardware.  It works!

--         Aug. 10, 2013 Refined the design so that it enforces a minimum

--                       spi_cs_o high time between assertions, thus allowing

--                       the design to actually program SPI FLASH chips using

--                       a 50 MHz clock, instead of just at 25 MHz.

--

-- Description

-------------------------------------------------------------------------------

-- This module is an interface to a SPI serial FLASH memory.  The code was

-- written in order to keep it as generic as possible, but without many

-- extra frills.  The module was written by reading the Adesto Technologies

-- AT25DF641 and ST Micro M25P64 datasheets.

--

-- There are three registers involved in its use.  There is one for the

-- SPI command byte, one for the 24-bit SPI address, and one for data to

-- be read from, or written to, the SPI serial FLASH device.

--

-- The SPI serial FLASH interface is implemented using four signals:

--   spi_cs_o  = SPI chip select outputs

--   spi_sck_o = Serial Clock output

--   spi_si_i  = Serial Data input

--   spi_so_o  = Serial Data output

--

-- For multiple SPI devices, the spi_cs_o output is implemented as a bus

-- of register driven outputs.  The size of the bus is controlled by generics,

-- allowing any number of SPI devices to be selected.  Because these outputs

-- are not decoded as a 1-active-of-N type signal, it is possible to select

-- multiple devices simultaneously, which may work well for writing and

-- erasing, but not for reading.  You have been warned!

--

-- The spi_sck_o output is generated at half the sys_clk rate, and it is

-- not adjustable.  To obtain operation at lower clock rates without

-- using a lower sys_clk frequency, consider slowing down the operation

-- of this module by the use of the sys_clk_en signal.

--

-- This module takes the approach that the serial communication with the 

-- SPI device is not continuous.  Instead, the command is completed in

-- segments or phases.  To begin a command, a bus write to the SPI chip

-- select register asserts '0' on the desired chip select bits.  Then, a write

-- to the command register causes the command to be sent out, generating a

-- burst of eight clock pulses.  Another separate bus cycle is then required

-- in order to send out the address.  After that, bus cycles can be used to

-- either read or write data bytes.  At the conclusion of those activities,

-- the command can be terminated or executed by simply writing to the SPI

-- chip select register to raise the chip select bit back to a '1'.

--

-- This approach works because the spi_sck_o output is under control of

-- this module.

--

-- There are no provisions for use of the "hold" or "WP" (write protect)

-- signals.  If desired, it might be possible to use sys_clk_en as a hold

-- signal, although this has not been tested or investigated in any detail.

--

-- The registers are summarized as follows:

--

-- Address      Structure   Function

-- -------      ---------   -----------------------------------------------------

--   0x0           (N:0)    SPI chip Selects, where N=NUM_CS-1.

--   0x1           (7:0)    SPI Command Byte

--   0x2          (23:0)    SPI Address Bytes

--   0x3+          (7:0)    SPI Data

--

--   Notes on Registers:

--

--   (0x0) SPI Chip Selects

--

--     Writing to this register selects which associated spi_cs_o outputs are

--     active.  The spi_cs_o outputs are driven directly from the register,

--     and can be changed at any time.  SPI chip selects are low asserted,

--     so the bits in this register are loaded with all ones initially.

--     To initiate a command, the appropriate spi_cs_o bit must be cleared

--     to zero.  To conclude and execute a command, the spi_cs_o bit must

--     be set back to one.

--     Reading this register returns the contents, but does not affect the

--     SPI interface.

--     Care should be exercised when using this register with multiple SPI

--     devices, as it is possible to activate more than one device.  This

--     may work well for writing to the devices, but will result in data bit

--     collisions if multiple devices are read simultaneously.

--

--   (0x1) SPI Command Byte

--

--     Writing to this register causes the contents to be updated, and also

--     sends out the new contents in serial form, most significant bit first.

--     Reading this register returns the contents, but does not affect the

--     SPI interface.

--

--   (0x2) SPI Address Bytes

--

--     Writing to this register causes the contents to be updated, and also

--     sends out the new contents in serial form, most significant bit first.

--     Reading this register returns the contents, but does not affect the

--     SPI interface.

--

--   (0x3+) SPI Data Byte (Addresses in the range [0x3..0xF] access this.)

--

--     There is no local storage register inside the module for this address.

--     Writing to this address causes the data to be sent out in serial form,

--     most significant bit first.

--     Reading this address causes a burst of eight clock pulses to be issued

--     from the SPI interface, effectively reading in eight bits and returning

--     them in parallel over the bus interface.

--     Successive reads or writes therefore program or read successive locations

--     in the SPI device.

--     It should be noted that the SPI serial FLASH devices may allow continuous

--     reads which go on indefinitely, cycling through the entire contents of

--     the FLASH array.  On the other hand, writes are buffered inside the

--     FLASH device, so that a "Byte/Page Program" instruction may allow from

--     1 to 256 sequential bytes to be programmed.  If more bytes are sent to

--     the FLASH device, it may simply cause the FIFO buffer inside the FLASH

--     device to hold the last 256 bytes for programming, discarding the bytes

--     which were written at first.

--

-- The sys_rst_n input is an asynchronous reset.

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.NUMERIC_STD.ALL;

use IEEE.MATH_REAL.ALL;

library work;

use work.convert_pack.all;

  entity spi_flash_interface is

    generic(

      NUM_CS        : natural := 1;  -- Number of SPI device selects

      DEF_R_0       : unsigned(31 downto 0) := str2u("00000001",32); -- SPI Chip Selects

      DEF_R_1       : unsigned(31 downto 0) := str2u("00000003",32); -- SPI Command byte

      DEF_R_2       : unsigned(31 downto 0) := str2u("007F0000",32)  -- SPI Address (24 bits)

    );

    port (

      -- System Clock and Clock Enable

      sys_rst_n  : in  std_logic;

      sys_clk    : in  std_logic;

      sys_clk_en : in  std_logic;

      -- Bus interface

      adr_i      : in  unsigned(3 downto 0);

      sel_i      : in  std_logic;

      we_i       : in  std_logic;

      dat_i      : in  unsigned(31 downto 0);

      dat_o      : out unsigned(31 downto 0);

      ack_o      : out std_logic;

      -- SPI interface

      -- "hold" and "WP" are not implemented.

      spi_cs_o   : out unsigned(NUM_CS-1 downto 0);

      spi_sck_o  : out std_logic;

      spi_so_o   : out std_logic;

      spi_si_i   : in  std_logic

    );

end spi_flash_interface;

architecture beh of spi_flash_interface is

-- Constants

constant DAT_SIZE     : natural := 32;

-- Internal signal declarations

signal reg_cs    : unsigned(NUM_CS-1 downto 0);

signal reg_cmd   : unsigned(7 downto 0);

signal reg_adr   : unsigned(23 downto 0);

signal sr        : unsigned(7 downto 0);

signal clk_count : unsigned(4 downto 0);

signal ack       : std_logic;

  -- For the state machine

type FSM_STATE_TYPE is (IDLE, SEND_CMD, SEND_ADR, SHIFT_A2, SHIFT_A1, SHIFT_A0, GET_BYTE, GIVE_ACK);

signal fsm_state      : FSM_STATE_TYPE;

-----------------------------------------------------------------------------

begin

  -- Register read mux

  with (adr_i) select

  dat_o <=

    u_resize(reg_cs,DAT_SIZE)   when "0000",

    u_resize(reg_cmd,DAT_SIZE)  when "0001",

    u_resize(reg_adr,DAT_SIZE)  when "0010",

    u_resize(sr,DAT_SIZE)       when others;

  -- Create acknowledge signal

  ack   <= '1' when sel_i='1' and fsm_state=GIVE_ACK else '0';

  ack_o <= ack;

  -- Create SPI signals

  spi_cs_o  <= reg_cs;

  spi_so_o  <= sr(7);

  spi_sck_o <= clk_count(0);

  -- The main process

  main_proc: process(sys_clk, sys_rst_n)

  begin

    if (sys_rst_n='0') then

      reg_cs    <= DEF_R_0(NUM_CS-1 downto 0);

      reg_cmd   <= DEF_R_1(reg_cmd'length-1 downto 0);

      reg_adr   <= DEF_R_2(reg_adr'length-1 downto 0);

      sr        <= (others=>'0');

      clk_count <= to_unsigned(0,clk_count'length);

      fsm_state   <= IDLE;

    elsif (sys_clk'event and sys_clk='1') then

      if (sys_clk_en='1') then

        -- Decrement the clock counter

        if (clk_count>0) then

          clk_count <= clk_count-1;

          -- Handle the shift register

          if (fsm_state=GET_BYTE and clk_count(0)='0') or (fsm_state/=GET_BYTE and clk_count(0)='1') then

            sr <= sr(6 downto 0) & spi_si_i;

          end if;

        end if;

        -- Handle state transitions

        case (fsm_state) is

          when IDLE =>

            null;

          when SEND_CMD =>

            sr <= reg_cmd;

            clk_count <= to_unsigned(16,clk_count'length);

            fsm_state <= SHIFT_A0;

          when SEND_ADR =>

            sr <= reg_adr(23 downto 16);

            clk_count <= to_unsigned(16,clk_count'length);

            fsm_state <= SHIFT_A2;

          when SHIFT_A2 =>

            if (clk_count=0) then

              sr <= reg_adr(15 downto 8);

              clk_count <= to_unsigned(16,clk_count'length);

              fsm_state <= SHIFT_A1;

            end if;

          when SHIFT_A1 =>

            if (clk_count=0) then

              sr <= reg_adr(7 downto 0);

              clk_count <= to_unsigned(16,clk_count'length);

              fsm_state <= SHIFT_A0;

            end if;

          when SHIFT_A0 =>

            if (clk_count=0) then

              fsm_state <= GIVE_ACK;

            end if;

          when GET_BYTE =>

            if (clk_count=0) then

              fsm_state <= GIVE_ACK;

            end if;

          when GIVE_ACK =>

            fsm_state <= IDLE;

          --when others => 

          --  fsm_state <= IDLE;

        end case;

        -- Handle bus writes to registers

        if (fsm_state=IDLE and sel_i='1' and we_i='1') then

          case (adr_i) is

            when "0000" =>

              reg_cs <= dat_i(NUM_CS-1 downto 0);

              fsm_state <= GIVE_ACK;

            when "0001" =>

              reg_cmd <= dat_i(reg_cmd'length-1 downto 0);

              fsm_state <= SEND_CMD;

            when "0010" =>

              reg_adr <= dat_i(reg_adr'length-1 downto 0);

              fsm_state <= SEND_ADR;

            when others => null;

              sr <= dat_i(sr'length-1 downto 0);

              clk_count <= to_unsigned(16,clk_count'length);

              fsm_state <= SHIFT_A0;

          end case;

        end if;

        -- Handle SPI read cycle

        if (fsm_state=IDLE and sel_i='1' and we_i='0') then

          case (adr_i) is

            when "0000" =>

              fsm_state <= GIVE_ACK;

            when "0001" =>

              fsm_state <= GIVE_ACK;

            when "0010" =>

              fsm_state <= GIVE_ACK;

            when others =>

              clk_count <= to_unsigned(16,clk_count'length);

              fsm_state <= GET_BYTE;

          end case;

        end if;

      end if; -- sys_clk_en

    end if; -- sys_clk

  end process;

end beh;

-------------------------------------------------------------------------------

-- SPI Flash System Initializer

-------------------------------------------------------------------------------

--

-- Author: John Clayton

-- Date  : July 31, 2013 Created this module starting with code copied from

--                       another module.  Began writing description.

--         Aug.  5, 2013 Simulated the design.  Revamped the register

--                       structure, added init_chain feature.  Combined

--                       states in fl_state FSM.

--         Aug.  7, 2013 Added explicit reset bit.

--

-- Description

-------------------------------------------------------------------------------

-- This module uses an interface to SPI serial FLASH memory devices to allow

-- reading/writing/erasing of the FLASH.  It includes a state machine that

-- coordinates many of the required commands automatically, to make the

-- process of reading and writing SPI FLASH appear as though a simple RAM

-- is being used.  Moreover, the state machine has an initialization mode

-- which can read bytes out of the selected SPI FLASH device and present

-- them on an 8-bit parallel output port.

--

-- The actual rate of outputting "initialization bytes" is determined by

-- the init_ack_i input, up to the maximum available rate Fmax of approx.

-- 2.7 MBytes/second.  This maximum byte transfer rate is calculated

-- according to the following formula:

--

--   Fmax = (Fsys_clk / N)

--

-- Where N=18 sys_clks required per byte obtained, and Fsys_clk is

-- currently 50 MHz.  Other sys_clk rates would also work.

--

-- The init_adr_o output allows the outgoing bytes to be treated in

-- different ways, or stored into different places, depending on the address

-- setting being used.  Note that the init_adr_o output is taken directly

-- from the init address register, which refers to the addresses within

-- the SPI devices themselves.  This signal therefore not required to be

-- used as-is during initialization.  Feel free to substitute any addresses

-- you want, or re-map the initialization addresses as needed.

--

-- The idea is that the parallel output bytes can be used to send commands

-- on a system bus.  One way to do this is to attach a UART, which would

-- inject ASCII characters into an ASCII command interpreter, such as

-- "async_syscon" or "udp_ip_syscon".

--

-- Another way would be to send the bytes into a binary command interpreter.

--

-- Another way would be to attach the init port as a requester on the arbiter

-- for the target bus.

--

-- In addition to creating initialization commands at power on, the output

-- bytes can also be treated as DSP samples of a waveform.  Thus, the output

-- could be used to generate audio "sound bytes" [pun intended] at a set

-- sample rate and bits per sample.

--

-- In fact, it is conceivable that through the use of a command interpreter,

-- a final initialization command could reprogram the initialization address

-- and quantity, in order to begin a whole new initialization sequence!  Oh,

-- the sheer joy of it!  If there is no command interpreter being used, there

-- is an alternative method of achieving this serial-init-sequencing joy.

-- A chain enable bit is provided in the initialization settings register

-- which causes the initialization sequencer to "re-up" by using the last

-- eight bytes of the current initialization sequence as a new address and

-- quantity for the next one.  Isn't that simply grand?

--

-- Think of what you could do...  You could set up registers in the first

-- initialization sequence, and then invoke another sequence which would

-- play some kind of audio greeting.  It could be music, or perhaps a voice.

-- Like the audio might say "System is now fully functional, and ready!"

-- Like that.  You know, it isn't bad to have a healthy imagination.

-- At least, that's what I imagine.

--

-- As a corollary benefit of implementing the initialization function, an

-- additional SPI FLASH memory mapping "feature" is provided.  This means

-- that the entire contents of the SPI FLASH device is memory mapped, with a

-- separate address for each byte within the device.  Sequential reads and

-- writes are allowed within this address space, and the needed WREN and

-- other commands to perform the reads/writes are performed automatically.

-- This also means that the bus cycle acknowledge signal when using the

-- memory mapped region can take quite a long time to appear, on the order

-- of 5 ms.  Also note that the key word when using the memory mapped

-- region is "sequential."  This is so important that this module actually

-- enforces sequential accesses, by keeping a copy of the initial address

-- and incrementing that during the session.  The "session" begins when

-- an access is requested within the memory mapped region, and ends when

-- an "access idle" timeout is reached.  Therefore, temporally-sequential

-- accesses which attempt to decrement the address, or jump around in

-- other ways, will actually result in sequential bytes being read/written

-- during the session.

--

-- The system initializer is an extension of a much simpler register-based

-- "low-level" SPI Flash interface module.  The "low-level" features are

-- preserved in this module.

--

-- The original interface was written in order to be as generic as possible,

-- without many extra frills.  The module was written by and tested using

-- the Adesto Technologies AT25DF641 and ST Micro M25P64 datasheets.  Also,

-- hardware testing was initially done on the M25P64 mounted on a Lattice

-- Semiconductor "Versa" FPGA development board.  Nevertheless, this design

-- should work quite easily with other SPI FLASH devices and other FPGAs.

--

-- For the basic SPI interface, there are three registers involved.

-- There is one for the SPI command byte, one for the 24-bit SPI address, 

-- and one for data to be read from, or written to, the SPI serial FLASH 

-- device.  The basic interface was preserved in order to allow for any

-- desired command to be explicitly executed via register accesses.

--

-- The SPI serial FLASH interface is implemented using four signals:

--   spi_cs_o  = SPI chip select outputs

--   spi_sck_o = Serial Clock output

--   spi_si_i  = Serial Data input

--   spi_so_o  = Serial Data output

--

-- For multiple SPI devices, the spi_cs_o output is implemented as a bus

-- of register driven outputs.  The size of the bus is controlled by generics,

-- allowing any number of SPI devices to be selected.  Because these outputs

-- are not decoded as a 1-active-of-N type signal, it is possible to select

-- multiple devices simultaneously, which may work well for writing and

-- erasing, but not for reading.  You have been warned!

--

-- The spi_sck_o output is generated at half the sys_clk rate, and it is

-- not adjustable.  To obtain operation at lower clock rates without

-- using a lower sys_clk frequency, consider slowing down the operation

-- of this module by the use of the sys_clk_en signal.

--

-- This module takes the approach that the serial communication with the 

-- SPI device is not continuous.  Instead, the command is completed in

-- segments or phases.  To begin a command, a bus write to the SPI chip

-- select register asserts '0' on the desired chip select bits.  Then, a write

-- to the command register causes the command to be sent out, generating a

-- burst of eight clock pulses.  Another separate bus cycle is then required

-- in order to send out the address.  After that, bus cycles can be used to

-- either read or write data bytes.  At the conclusion of those activities,

-- the command can be terminated or executed by simply writing to the SPI

-- chip select register to raise the chip select bit back to a '1'.

--

-- This approach works because the spi_sck_o output is under control of

-- this module.

--

-- There are no provisions for use of the "hold" or "WP" (write protect)

-- signals.  If desired, it might be possible to use sys_clk_en as a hold

-- signal, although this has not been tested or investigated in any detail.

--

-- The registers are summarized as follows:

--

-- Address   Structure        Function

-- -------   --------------   -----------------------------------------------------

--   0x0     (N+16:16,N:0)    SPI chip Selects, where N=NUM_CS-1.

--   0x1             (7:0)    SPI Command Byte

--   0x2            (23:0)    SPI Address Bytes

--   0x3            (31:0)    Init Address

--   0x4            (31:0)    Init Quantity (bytes)

--   0x5             (3:0)    Init Settings

--   0x6+            (7:0)    SPI Data

--

--   Notes on Registers:

--

--   (0x0) low-level SPI Chip Select control

--

--     This register contains a single bit, which is directly mapped to the

--     spi_cs_o output during low-level SPI operations.  During ram mapped

--     operations and initialization sequences, the spi_cs_o output is

--     controlled automatically by a state machine so that during those

--     operations, this bit has no effect.

--

--   (0x1) low-level SPI Command Byte

--

--     This is part of the low-level SPI interface, and is not involved in

--     initialization or RAM mapping of the SPI devices.

--

--     Writing to this register causes the contents to be updated, and also

--     sends out the new contents in serial form, most significant bit first.

--     Reading this register returns the contents, but does not affect the

--     SPI interface.

--

--   (0x2) low-level SPI Address

--

--     This is part of the low-level SPI interface, and is not involved in

--     initialization or RAM mapping of the SPI devices.

--

--     Writing to this register causes the contents to be updated, and also

--     sends out the new contents in serial form, most significant bits first.

--     Reading this register returns the contents, but does not affect the

--     SPI interface.

--

--     The number of bytes used for SPI addresses is set by the constant

--     SPI_ADR_BYTES.

--

--   (0x3) Init Address

--

--     Bits (31:0) contain the initialization address, which consists of

--       four bytes: [decode][sector][page][byte]

--       This grouping of fields is actually based on the size of the

--       SPI FLASH devices being tested.  If larger devices are used,

--       for example, then the [decode] field may use fewer bits, and

--       the [sector] field may grow.  Similarly, the [page] field might

--       change if the devices being used have pages larger than 256

--       bytes.  So, it's a matter of interpretation.  The main idea is

--       for form a flat address space which maps all the attached SPI

--       devices.

--

--   (0x4) Initialization Quantity (Bytes)

--     This register contains the number of bytes to read from the SPI

--     FLASH device during an initialization operation.

--     The number can be quite large, up to 0x800000 (8 Mbytes) for the

--     AT25DF641 and M25P64.  In anticipation of larger future devices,

--     this field was made a full 32-bits, allowing up to 4 gigabytes.

--     Operation of the initialization cycle begins immediately once

--     this field is set to anything greater than zero.  Also, the

--     quantity is "live" and it decrements during initialization.

--

--   (0x5) Init Settings

--

--     Bit  (0) is the R/W Access Enable bit.  Set this bit in order to

--       freely read and write to the SPI FLASH via the memory mapped

--       interface.  When it is cleared, the memory mapped interface does

--       not respond with a bus cycle acknowledge, since it is not

--       operating.

--     Bit  (1) is the Initialization chain enable bit.  Setting this bit

--       causes the last eight bytes of the initialization to be withheld.

--       Instead of being sent out as bus cycles on the parallel init bus,

--       the bytes are used to reset the initializer for another run

--       using a new address and a new quantity.  Since the init_ack_i

--       input is used to throttle initialization cycles when delays are

--       required, no delay is provided within the eight "re-up" bytes.

--       The re-up bytes are composed of four address bytes, followed by

--       four quantity bytes.  The fields are stored least significant

--       byte first.

--     Bit  (2) is the Erase bit.  Set this bit to erase the sector

--       currently selected by the [sector] field in the address register.

--       Note that sector erase times can be on the order of seconds.

--       (Typically 1s, but up to 3s for M25P64.  Typically 400ms, but

--       up to 950ms for AT25DF641.)  Since the erase operation is

--       self-timed inside the device, this module polls the device status

--       register to see when the erase operation is completed.  When it

--       is, the erase bit is then cleared.  No other operations are

--       possible while this is occurring.  Because the sector erase can

--       take so long, there is a way to break out by using the explicit

--       reset bit.  Also, there is no automatic timeout from the sector

--       erase operation.

--     Bit  (3) is an explicit reset bit.  Setting it resets both state

--       machines.  It is a write only bit, and returns a '0' when read.

--       It can be used to "break out" of an operation, such as a long

--       sector erase.

--

--   (0x6+) SPI Data Byte (System cycles in the range [0x6..0xF] access this.)

--

--     This is part of the low-level SPI interface, and is not involved in

--     initialization or RAM mapping of the SPI devices.

--

--     There is no local storage register inside the module for this address.

--     Writing to this address causes the data to be sent out in serial form,

--     most significant bit first.

--     Reading this address causes a burst of eight clock pulses to be issued

--     from the SPI interface, effectively reading in eight bits and returning

--     them in parallel over the bus interface.

--     Successive reads or writes therefore program or read successive locations

--     in the SPI device.

--     It should be noted that the SPI serial FLASH devices may allow continuous

--     reads which go on indefinitely, cycling through the entire contents of

--     the FLASH array.  On the other hand, writes are buffered inside the

--     FLASH device, so that a "Byte/Page Program" instruction may allow from

--     1 to 256 sequential bytes to be programmed.  If more bytes are sent to

--     the FLASH device, it may simply cause the FIFO buffer inside the FLASH

--     device to hold the last 256 bytes for programming, discarding the bytes

--     which were written at first.

--

-- The sys_rst_n input is an asynchronous reset.

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.NUMERIC_STD.ALL;

use IEEE.MATH_REAL.ALL;

library work;

use work.dds_pack.all;

use work.convert_pack.all;

  entity spi_flash_sys_init is

    generic(

      SYS_CLK_RATE : real    := 50000000.0;

      FLASH_IDLE   : natural := 2;  -- Number of ms idle before RAM-mapped FLASH operation closeout

      DECODE_BITS  : natural := 8;  -- Number of init address upper-bits decoded to select individual SPI devices.

      DEF_R_0      : unsigned(31 downto 0) := str2u("00000001",32); -- low-level SPI Chip Select control

      DEF_R_1      : unsigned(31 downto 0) := str2u("00000003",32); -- low-level SPI Command byte