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[/] [xge_mac/] [trunk/] [rtl/] [verilog/] [stats_sm.v] - Blame information for rev 27

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1 24 antanguay
//////////////////////////////////////////////////////////////////////
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////                                                              ////
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////  File name "wishbone.v"                                      ////
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////                                                              ////
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////  This file is part of the "10GE MAC" project                 ////
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////  http://www.opencores.org/cores/xge_mac/                     ////
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////                                                              ////
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////  Author(s):                                                  ////
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////      - A. Tanguay (antanguay@opencores.org)                  ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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////                                                              ////
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//// Copyright (C) 2008 AUTHORS. All rights reserved.             ////
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////                                                              ////
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//// This source file may be used and distributed without         ////
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//// restriction provided that this copyright statement is not    ////
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//// removed from the file and that any derivative work contains  ////
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//// the original copyright notice and the associated disclaimer. ////
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////                                                              ////
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//// This source file is free software; you can redistribute it   ////
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//// and/or modify it under the terms of the GNU Lesser General   ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any   ////
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//// later version.                                               ////
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////                                                              ////
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//// This source is distributed in the hope that it will be       ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
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//// PURPOSE.  See the GNU Lesser General Public License for more ////
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//// details.                                                     ////
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////                                                              ////
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//// You should have received a copy of the GNU Lesser General    ////
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//// Public License along with this source; if not, download it   ////
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//// from http://www.opencores.org/lgpl.shtml                     ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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`include "defines.v"
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module stats_sm(/*AUTOARG*/
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  // Outputs
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  stats_tx_octets, stats_tx_pkts, stats_rx_octets, stats_rx_pkts,
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  // Inputs
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  wb_clk_i, wb_rst_i, txsfifo_rdata, txsfifo_rempty, rxsfifo_rdata,
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  rxsfifo_rempty, clear_stats_tx_octets, clear_stats_tx_pkts,
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  clear_stats_rx_octets, clear_stats_rx_pkts
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  );
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input         wb_clk_i;
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input         wb_rst_i;
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input  [13:0] txsfifo_rdata;
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input         txsfifo_rempty;
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input  [13:0] rxsfifo_rdata;
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input         rxsfifo_rempty;
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output [31:0] stats_tx_octets;
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output [31:0] stats_tx_pkts;
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output [31:0] stats_rx_octets;
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output [31:0] stats_rx_pkts;
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input         clear_stats_tx_octets;
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input         clear_stats_tx_pkts;
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input         clear_stats_rx_octets;
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input         clear_stats_rx_pkts;
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/*AUTOREG*/
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// Beginning of automatic regs (for this module's undeclared outputs)
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reg [31:0]              stats_rx_octets;
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reg [31:0]              stats_rx_pkts;
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reg [31:0]              stats_tx_octets;
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reg [31:0]              stats_tx_pkts;
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// End of automatics
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/*AUTOWIRE*/
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reg           txsfifo_rempty_d1;
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reg           rxsfifo_rempty_d1;
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reg [31:0]    next_stats_tx_octets;
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reg [31:0]    next_stats_tx_pkts;
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reg [31:0]    next_stats_rx_octets;
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reg [31:0]    next_stats_rx_pkts;
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always @(posedge wb_clk_i or posedge wb_rst_i) begin
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    if (wb_rst_i == 1'b1) begin
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        txsfifo_rempty_d1 <= 1'b1;
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        rxsfifo_rempty_d1 <= 1'b1;
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        stats_tx_octets <= 32'b0;
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        stats_tx_pkts <= 32'b0;
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        stats_rx_octets <= 32'b0;
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        stats_rx_pkts <= 32'b0;
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    end
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    else begin
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        txsfifo_rempty_d1 <= txsfifo_rempty;
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        rxsfifo_rempty_d1 <= rxsfifo_rempty;
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        stats_tx_octets <= next_stats_tx_octets;
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        stats_tx_pkts <= next_stats_tx_pkts;
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        stats_rx_octets <= next_stats_rx_octets;
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        stats_rx_pkts <= next_stats_rx_pkts;
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    end
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end
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always @(/*AS*/clear_stats_rx_octets or clear_stats_rx_pkts
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         or clear_stats_tx_octets or clear_stats_tx_pkts
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         or rxsfifo_rdata or rxsfifo_rempty_d1 or stats_rx_octets
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         or stats_rx_pkts or stats_tx_octets or stats_tx_pkts
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         or txsfifo_rdata or txsfifo_rempty_d1) begin
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    next_stats_tx_octets = {32{~clear_stats_tx_octets}} & stats_tx_octets;
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    next_stats_tx_pkts = {32{~clear_stats_tx_pkts}} & stats_tx_pkts;
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    next_stats_rx_octets = {32{~clear_stats_rx_octets}} & stats_rx_octets;
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    next_stats_rx_pkts = {32{~clear_stats_rx_pkts}} & stats_rx_pkts;
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    if (!txsfifo_rempty_d1) begin
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        next_stats_tx_octets = next_stats_tx_octets + {18'b0, txsfifo_rdata};
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        next_stats_tx_pkts = next_stats_tx_pkts + 32'b1;
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    end
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    if (!rxsfifo_rempty_d1) begin
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        next_stats_rx_octets = next_stats_rx_octets + {18'b0, rxsfifo_rdata};
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        next_stats_rx_pkts = next_stats_rx_pkts + 32'b1;
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    end
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end
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endmodule

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