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[/] [xge_mac/] [trunk/] [rtl/] [verilog/] [sync_clk_wb.v] - Blame information for rev 12

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//////////////////////////////////////////////////////////////////////
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////                                                              ////
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////  File name "sync_clk_wb.v"                                   ////
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////                                                              ////
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////  This file is part of the "10GE MAC" project                 ////
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////  http://www.opencores.org/cores/xge_mac/                     ////
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////                                                              ////
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////  Author(s):                                                  ////
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////      - A. Tanguay (antanguay@opencores.org)                  ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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////                                                              ////
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//// Copyright (C) 2008 AUTHORS. All rights reserved.             ////
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////                                                              ////
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//// This source file may be used and distributed without         ////
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//// restriction provided that this copyright statement is not    ////
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//// removed from the file and that any derivative work contains  ////
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//// the original copyright notice and the associated disclaimer. ////
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////                                                              ////
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//// This source file is free software; you can redistribute it   ////
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//// and/or modify it under the terms of the GNU Lesser General   ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any   ////
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//// later version.                                               ////
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////                                                              ////
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//// This source is distributed in the hope that it will be       ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
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//// PURPOSE.  See the GNU Lesser General Public License for more ////
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//// details.                                                     ////
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////                                                              ////
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//// You should have received a copy of the GNU Lesser General    ////
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//// Public License along with this source; if not, download it   ////
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//// from http://www.opencores.org/lgpl.shtml                     ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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`include "defines.v"
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module sync_clk_wb(/*AUTOARG*/
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  // Outputs
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  status_crc_error, status_fragment_error, status_txdfifo_ovflow,
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  status_txdfifo_udflow, status_rxdfifo_ovflow, status_rxdfifo_udflow,
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  status_pause_frame_rx, status_local_fault, status_remote_fault,
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  // Inputs
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  wb_clk_i, wb_rst_i, status_crc_error_tog, status_fragment_error_tog,
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  status_txdfifo_ovflow_tog, status_txdfifo_udflow_tog,
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  status_rxdfifo_ovflow_tog, status_rxdfifo_udflow_tog,
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  status_pause_frame_rx_tog, status_local_fault_crx,
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  status_remote_fault_crx
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  );
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input         wb_clk_i;
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input         wb_rst_i;
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input         status_crc_error_tog;
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input         status_fragment_error_tog;
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input         status_txdfifo_ovflow_tog;
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input         status_txdfifo_udflow_tog;
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input         status_rxdfifo_ovflow_tog;
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input         status_rxdfifo_udflow_tog;
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input         status_pause_frame_rx_tog;
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input         status_local_fault_crx;
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input         status_remote_fault_crx;
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output        status_crc_error;
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output        status_fragment_error;
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output        status_txdfifo_ovflow;
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output        status_txdfifo_udflow;
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output        status_rxdfifo_ovflow;
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output        status_rxdfifo_udflow;
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output        status_pause_frame_rx;
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output        status_local_fault;
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output        status_remote_fault;
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/*AUTOREG*/
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/*AUTOWIRE*/
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wire  [6:0]             sig_out1;
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wire  [1:0]             sig_out2;
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assign status_crc_error = sig_out1[6];
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assign status_fragment_error = sig_out1[5];
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assign status_txdfifo_ovflow = sig_out1[4];
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assign status_txdfifo_udflow = sig_out1[3];
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assign status_rxdfifo_ovflow = sig_out1[2];
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assign status_rxdfifo_udflow = sig_out1[1];
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assign status_pause_frame_rx = sig_out1[0];
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assign status_local_fault = sig_out2[1];
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assign status_remote_fault = sig_out2[0];
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meta_sync #(.DWIDTH (7), .EDGE_DETECT (1)) meta_sync0 (
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                      // Outputs
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                      .out              (sig_out1),
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                      // Inputs
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                      .clk              (wb_clk_i),
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                      .reset_n          (~wb_rst_i),
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                      .in               ({
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                                          status_crc_error_tog,
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                                          status_fragment_error_tog,
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                                          status_txdfifo_ovflow_tog,
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                                          status_txdfifo_udflow_tog,
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                                          status_rxdfifo_ovflow_tog,
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                                          status_rxdfifo_udflow_tog,
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                                          status_pause_frame_rx_tog
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                                         }));
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meta_sync #(.DWIDTH (2), .EDGE_DETECT (0)) meta_sync1 (
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                      // Outputs
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                      .out              (sig_out2),
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                      // Inputs
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                      .clk              (wb_clk_i),
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                      .reset_n          (~wb_rst_i),
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                      .in               ({
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                                          status_local_fault_crx,
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                                          status_remote_fault_crx
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                                         }));
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endmodule

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