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[/] [xge_mac/] [trunk/] [tbench/] [systemc/] [sc_testbench.h] - Blame information for rev 19

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//////////////////////////////////////////////////////////////////////
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////                                                              ////
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////  File name "sc_testbench.h"                                  ////
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////                                                              ////
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////  This file is part of the "10GE MAC" project                 ////
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////  http://www.opencores.org/cores/xge_mac/                     ////
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////                                                              ////
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////  Author(s):                                                  ////
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////      - A. Tanguay (antanguay@opencores.org)                  ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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////                                                              ////
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//// Copyright (C) 2008 AUTHORS. All rights reserved.             ////
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////                                                              ////
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//// This source file may be used and distributed without         ////
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//// restriction provided that this copyright statement is not    ////
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//// removed from the file and that any derivative work contains  ////
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//// the original copyright notice and the associated disclaimer. ////
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////                                                              ////
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//// This source file is free software; you can redistribute it   ////
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//// and/or modify it under the terms of the GNU Lesser General   ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any   ////
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//// later version.                                               ////
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////                                                              ////
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//// This source is distributed in the hope that it will be       ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
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//// PURPOSE.  See the GNU Lesser General Public License for more ////
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//// details.                                                     ////
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////                                                              ////
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//// You should have received a copy of the GNU Lesser General    ////
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//// Public License along with this source; if not, download it   ////
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//// from http://www.opencores.org/lgpl.shtml                     ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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#ifndef TESTBENCH_H
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#define TESTBENCH_H
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#include "systemc.h"            // SystemC global header
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#include "sc_defines.h"
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#include "sc_cpu_if.h"
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#include "sc_pkt_if.h"
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#include "sc_xgmii_if.h"
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#include "sc_pkt_generator.h"
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#include "sc_scoreboard.h"
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SC_MODULE(testbench) {
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  public:
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    //---
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    // Ports
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    sc_in<bool> clk_156m25;
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    sc_in<bool> clk_xgmii;
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    sc_in<bool> wb_clk_i;
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    sc_in<bool> reset_156m25_n;
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    sc_in<bool> reset_xgmii_n;
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    sc_in<bool> wb_rst_i;
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    sc_in<bool> wb_ack_o;
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    sc_in<unsigned int> wb_dat_o;
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    sc_in<bool> wb_int_o;
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    sc_out<unsigned int> wb_adr_i;
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    sc_out<bool> wb_cyc_i;
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    sc_out<unsigned int> wb_dat_i;
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    sc_out<bool> wb_stb_i;
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    sc_out<bool> wb_we_i;
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    sc_out<unsigned int> xgmii_rxc;
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    sc_out<vluint64_t > xgmii_rxd;
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    sc_in<unsigned int> xgmii_txc;
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    sc_in<vluint64_t > xgmii_txd;
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    sc_out<vluint64_t > pkt_tx_data;
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    sc_out<bool> pkt_tx_eop;
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    sc_out<unsigned int> pkt_tx_mod;
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    sc_out<bool> pkt_tx_sop;
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    sc_out<bool> pkt_tx_val;
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    sc_in<bool> pkt_tx_full;
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    sc_in<bool> pkt_rx_avail;
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    sc_in<vluint64_t > pkt_rx_data;
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    sc_in<bool> pkt_rx_eop;
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    sc_in<unsigned int> pkt_rx_mod;
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    sc_in<bool> pkt_rx_err;
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    sc_in<bool> pkt_rx_sop;
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    sc_in<bool> pkt_rx_val;
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    sc_out<bool> pkt_rx_ren;
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    //---
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    // Instances
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    cpu_if cpu_if0;
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    pkt_if pkt_if0;
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    xgmii_if xgm_if0;
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    pkt_generator pif_gen0;
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    pkt_generator xgm_gen0;
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    scoreboard sb;
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    //---
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    // Functions
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    SC_CTOR(testbench) :
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        cpu_if0("cpu_if0"),
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        pkt_if0("pkt_if0"),
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        xgm_if0("xgm_if0"),
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        pif_gen0("pif_gen0"),
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        xgm_gen0("xgm_gen0"),
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        sb("sb") {
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        //--
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        // CPU Interface
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        cpu_if0.wb_clk_i (wb_clk_i);
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        cpu_if0.wb_rst_i (wb_rst_i);
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        cpu_if0.wb_ack_o (wb_ack_o);
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        cpu_if0.wb_dat_o (wb_dat_o);
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        cpu_if0.wb_int_o (wb_int_o);
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        cpu_if0.wb_adr_i (wb_adr_i);
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        cpu_if0.wb_cyc_i (wb_cyc_i);
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        cpu_if0.wb_dat_i (wb_dat_i);
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        cpu_if0.wb_stb_i (wb_stb_i);
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        cpu_if0.wb_we_i (wb_we_i);
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        //---
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        // Packet Interface
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        pkt_if0.clk_156m25 (clk_156m25);
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        pkt_if0.reset_156m25_n (reset_156m25_n);
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        pkt_if0.pkt_tx_data (pkt_tx_data);
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        pkt_if0.pkt_tx_eop (pkt_tx_eop);
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        pkt_if0.pkt_tx_mod (pkt_tx_mod);
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        pkt_if0.pkt_tx_sop (pkt_tx_sop);
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        pkt_if0.pkt_tx_val (pkt_tx_val);
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        pkt_if0.pkt_tx_full (pkt_tx_full);
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        pkt_if0.pkt_rx_avail (pkt_rx_avail);
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        pkt_if0.pkt_rx_data (pkt_rx_data);
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        pkt_if0.pkt_rx_eop (pkt_rx_eop);
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        pkt_if0.pkt_rx_mod (pkt_rx_mod);
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        pkt_if0.pkt_rx_err (pkt_rx_err);
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        pkt_if0.pkt_rx_sop (pkt_rx_sop);
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        pkt_if0.pkt_rx_val (pkt_rx_val);
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        pkt_if0.pkt_rx_ren (pkt_rx_ren);
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        //---
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        // XGMII Interface
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        xgm_if0.clk_xgmii (clk_xgmii);
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        xgm_if0.reset_xgmii_n (reset_xgmii_n);
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        xgm_if0.xgmii_rxc (xgmii_rxc);
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        xgm_if0.xgmii_rxd (xgmii_rxd);
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        xgm_if0.xgmii_txc (xgmii_txc);
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        xgm_if0.xgmii_txd (xgmii_txd);
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        //---
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        // Connect packet generators to physical interfaces
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        pif_gen0.connect_fifo(pkt_if0.get_tx_fifo_ptr());
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        xgm_gen0.connect_fifo(xgm_if0.get_tx_fifo_ptr());
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        //---
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        // Connector scoreboard to components
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        pkt_if0.connect_scoreboard(&sb, scoreboard::SB_PIF_ID);
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        xgm_if0.connect_scoreboard(&sb, scoreboard::SB_XGM_ID);
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        cpu_if0.connect_scoreboard(&sb, scoreboard::SB_CPU_ID);
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    }
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};
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#endif

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