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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  File name "tb_xge_mac.v"                                    ////
////                                                              ////
////  This file is part of the "10GE MAC" project                 ////
////  http://www.opencores.org/cores/xge_mac/                     ////
////                                                              ////
////  Author(s):                                                  ////
////      - A. Tanguay (antanguay@opencores.org)                  ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2008 AUTHORS. All rights reserved.             ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
 
 
`include "timescale.v"
`include "defines.v"
 
//`define GXB
//`define XIL
 
module tb;
 
 
/*AUTOREG*/
 
reg [7:0]     tx_buffer[0:10000];
integer       tx_length;
 
reg           clk_156m25;
reg           clk_312m50;
reg           clk_xgmii_rx;
reg           clk_xgmii_tx;
 
reg           reset_156m25_n;
reg           reset_xgmii_rx_n;
reg           reset_xgmii_tx_n;
 
reg           pkt_rx_ren;
 
reg  [63:0]   pkt_tx_data;
reg           pkt_tx_val;
reg           pkt_tx_sop;
reg           pkt_tx_eop;
reg  [2:0]    pkt_tx_mod;
 
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire                    pkt_rx_avail;           // From dut of xge_mac.v
wire [63:0]             pkt_rx_data;            // From dut of xge_mac.v
wire                    pkt_rx_eop;             // From dut of xge_mac.v
wire                    pkt_rx_err;             // From dut of xge_mac.v
wire [2:0]              pkt_rx_mod;             // From dut of xge_mac.v
wire                    pkt_rx_sop;             // From dut of xge_mac.v
wire                    pkt_rx_val;             // From dut of xge_mac.v
wire                    pkt_tx_full;            // From dut of xge_mac.v
wire                    wb_ack_o;               // From dut of xge_mac.v
wire [31:0]             wb_dat_o;               // From dut of xge_mac.v
wire                    wb_int_o;               // From dut of xge_mac.v
wire [7:0]              xgmii_txc;              // From dut of xge_mac.v
wire [63:0]             xgmii_txd;              // From dut of xge_mac.v
// End of automatics
 
wire  [7:0]   wb_adr_i;
wire  [31:0]  wb_dat_i;
 
wire [7:0]              xgmii_rxc;
wire [63:0]             xgmii_rxd;
 
wire [3:0]              tx_dataout;
 
wire                    xaui_tx_l0_n;
wire                    xaui_tx_l0_p;
wire                    xaui_tx_l1_n;
wire                    xaui_tx_l1_p;
wire                    xaui_tx_l2_n;
wire                    xaui_tx_l2_p;
wire                    xaui_tx_l3_n;
wire                    xaui_tx_l3_p;
 
xge_mac dut(/*AUTOINST*/
            // Outputs
            .pkt_rx_avail               (pkt_rx_avail),
            .pkt_rx_data                (pkt_rx_data[63:0]),
            .pkt_rx_eop                 (pkt_rx_eop),
            .pkt_rx_err                 (pkt_rx_err),
            .pkt_rx_mod                 (pkt_rx_mod[2:0]),
            .pkt_rx_sop                 (pkt_rx_sop),
            .pkt_rx_val                 (pkt_rx_val),
            .pkt_tx_full                (pkt_tx_full),
            .wb_ack_o                   (wb_ack_o),
            .wb_dat_o                   (wb_dat_o[31:0]),
            .wb_int_o                   (wb_int_o),
            .xgmii_txc                  (xgmii_txc[7:0]),
            .xgmii_txd                  (xgmii_txd[63:0]),
            // Inputs
            .clk_156m25                 (clk_156m25),
            .clk_xgmii_rx               (clk_xgmii_rx),
            .clk_xgmii_tx               (clk_xgmii_tx),
            .pkt_rx_ren                 (pkt_rx_ren),
            .pkt_tx_data                (pkt_tx_data[63:0]),
            .pkt_tx_eop                 (pkt_tx_eop),
            .pkt_tx_mod                 (pkt_tx_mod[2:0]),
            .pkt_tx_sop                 (pkt_tx_sop),
            .pkt_tx_val                 (pkt_tx_val),
            .reset_156m25_n             (reset_156m25_n),
            .reset_xgmii_rx_n           (reset_xgmii_rx_n),
            .reset_xgmii_tx_n           (reset_xgmii_tx_n),
            .wb_adr_i                   (wb_adr_i[7:0]),
            .wb_clk_i                   (wb_clk_i),
            .wb_cyc_i                   (wb_cyc_i),
            .wb_dat_i                   (wb_dat_i[31:0]),
            .wb_rst_i                   (wb_rst_i),
            .wb_stb_i                   (wb_stb_i),
            .wb_we_i                    (wb_we_i),
            .xgmii_rxc                  (xgmii_rxc[7:0]),
            .xgmii_rxd                  (xgmii_rxd[63:0]));
 
`ifdef GXB
// Example of transceiver instance
gxb gxb(// Outputs
        .rx_ctrldetect                  ({xgmii_rxc[7],
                                          xgmii_rxc[5],
                                          xgmii_rxc[3],
                                          xgmii_rxc[1],
                                          xgmii_rxc[6],
                                          xgmii_rxc[4],
                                          xgmii_rxc[2],
                                          xgmii_rxc[0]}),
        .rx_dataout                     ({xgmii_rxd[63:56],
                                          xgmii_rxd[47:40],
                                          xgmii_rxd[31:24],
                                          xgmii_rxd[15:8],
                                          xgmii_rxd[55:48],
                                          xgmii_rxd[39:32],
                                          xgmii_rxd[23:16],
                                          xgmii_rxd[7:0]}),
        .tx_dataout                     (tx_dataout[3:0]),
        // Inputs
        .pll_inclk                      (clk_156m25),
        .rx_analogreset                 (~reset_156m25_n),
        .rx_cruclk                      ({clk_156m25, clk_156m25, clk_156m25, clk_156m25}),
        .rx_datain                      (tx_dataout[3:0]),
        .rx_digitalreset                (~reset_156m25_n),
        .tx_ctrlenable                  ({xgmii_txc[7],
                                          xgmii_txc[5],
                                          xgmii_txc[3],
                                          xgmii_txc[1],
                                          xgmii_txc[6],
                                          xgmii_txc[4],
                                          xgmii_txc[2],
                                          xgmii_txc[0]}),
        .tx_datain                      ({xgmii_txd[63:56],
                                          xgmii_txd[47:40],
                                          xgmii_txd[31:24],
                                          xgmii_txd[15:8],
                                          xgmii_txd[55:48],
                                          xgmii_txd[39:32],
                                          xgmii_txd[23:16],
                                          xgmii_txd[7:0]}),
        .tx_digitalreset                (~reset_156m25_n));
`endif
 
`ifdef XIL
// Example of transceiver instance
xaui_block xaui(// Outputs
                .txoutclk               (),
                .xgmii_rxd              (xgmii_rxd[63:0]),
                .xgmii_rxc              (xgmii_rxc[7:0]),
                .xaui_tx_l0_p           (xaui_tx_l0_p),
                .xaui_tx_l0_n           (xaui_tx_l0_n),
                .xaui_tx_l1_p           (xaui_tx_l1_p),
                .xaui_tx_l1_n           (xaui_tx_l1_n),
                .xaui_tx_l2_p           (xaui_tx_l2_p),
                .xaui_tx_l2_n           (xaui_tx_l2_n),
                .xaui_tx_l3_p           (xaui_tx_l3_p),
                .xaui_tx_l3_n           (xaui_tx_l3_n),
                .txlock                 (),
                .align_status           (),
                .sync_status            (),
                .mgt_tx_ready           (),
                .drp_o                  (),
                .drp_rdy                (),
                .status_vector          (),
                // Inputs
                .dclk                   (clk_156m25),
                .clk156                 (clk_156m25),
                .clk312                 (clk_312m50),
                .refclk                 (clk_156m25),
                .reset                  (~reset_156m25_n),
                .reset156               (~reset_156m25_n),
                .xgmii_txd              (xgmii_txd[63:0]),
                .xgmii_txc              (xgmii_txc[7:0]),
                .xaui_rx_l0_p           (xaui_tx_l0_p),
                .xaui_rx_l0_n           (xaui_tx_l0_n),
                .xaui_rx_l1_p           (xaui_tx_l1_p),
                .xaui_rx_l1_n           (xaui_tx_l1_n),
                .xaui_rx_l2_p           (xaui_tx_l2_p),
                .xaui_rx_l2_n           (xaui_tx_l2_n),
                .xaui_rx_l3_p           (xaui_tx_l3_p),
                .xaui_rx_l3_n           (xaui_tx_l3_n),
                .signal_detect          (4'b1111),
                .drp_addr               (7'b0),
                .drp_en                 (2'b0),
                .drp_i                  (16'b0),
                .drp_we                 (2'b0),
                .configuration_vector   (7'b0));
 
glbl glbl();
`endif
 
//---
// Unused for this testbench
 
assign wb_adr_i = 8'b0;
assign wb_clk_i = 1'b0;
assign wb_cyc_i = 1'b0;
assign wb_dat_i = 32'b0;
assign wb_rst_i = 1'b1;
assign wb_stb_i = 1'b0;
assign wb_we_i = 1'b0;
 
 
//---
// XGMII Loopback
// This test is done with loopback on XGMII or using one of the tranceiver examples
 
`ifndef GXB
  `ifndef XIL
    assign xgmii_rxc = xgmii_txc;
    assign xgmii_rxd = xgmii_txd;
  `endif
`endif
 
//---
// Clock generation
 
initial begin
    clk_156m25 = 1'b0;
    clk_xgmii_rx = 1'b0;
    clk_xgmii_tx = 1'b0;
    forever begin
        WaitPS(3200);
        clk_156m25 = ~clk_156m25;
        clk_xgmii_rx = ~clk_xgmii_rx;
        clk_xgmii_tx = ~clk_xgmii_tx;
    end
end
 
initial begin
    clk_312m50 = 1'b0;
    forever begin
        WaitPS(1600);
        clk_312m50 = ~clk_312m50;
    end
end
 
//---
// Reset Generation
 
initial begin
    reset_156m25_n = 1'b0;
    reset_xgmii_rx_n = 1'b0;
    reset_xgmii_tx_n = 1'b0;
    WaitNS(20);
    reset_156m25_n = 1'b1;
    reset_xgmii_rx_n = 1'b1;
    reset_xgmii_tx_n = 1'b1;
end
 
 
//---
// Init signals
 
initial begin
 
    for (tx_length = 0; tx_length <= 1000; tx_length = tx_length + 1) begin
        tx_buffer[tx_length] = 0;
    end
 
    pkt_rx_ren = 1'b0;
 
    pkt_tx_data = 64'b0;
    pkt_tx_val = 1'b0;
    pkt_tx_sop = 1'b0;
    pkt_tx_eop = 1'b0;
    pkt_tx_mod = 3'b0;
 
end
 
task WaitNS;
  input [31:0] delay;
    begin
        #(1000*delay);
    end
endtask
 
task WaitPS;
  input [31:0] delay;
    begin
        #(delay);
    end
endtask
 
 
//---
// Task to send a single packet
 
task TxPacket;
  integer        i;
    begin
 
        $display("Transmit packet with length: %d", tx_length);
 
        @(posedge clk_156m25);
        WaitNS(1);
        pkt_tx_val = 1'b1;
 
        for (i = 0; i < tx_length; i = i + 8) begin
 
            pkt_tx_sop = 1'b0;
            pkt_tx_eop = 1'b0;
            pkt_tx_mod = 2'b0;
 
            if (i == 0) pkt_tx_sop = 1'b1;
 
            if (i + 8 >= tx_length) begin
                pkt_tx_eop = 1'b1;
                pkt_tx_mod = tx_length % 8;
            end
 
            pkt_tx_data[`LANE7] = tx_buffer[i];
            pkt_tx_data[`LANE6] = tx_buffer[i+1];
            pkt_tx_data[`LANE5] = tx_buffer[i+2];
            pkt_tx_data[`LANE4] = tx_buffer[i+3];
            pkt_tx_data[`LANE3] = tx_buffer[i+4];
            pkt_tx_data[`LANE2] = tx_buffer[i+5];
            pkt_tx_data[`LANE1] = tx_buffer[i+6];
            pkt_tx_data[`LANE0] = tx_buffer[i+7];
 
            @(posedge clk_156m25);
            WaitNS(1);
 
        end
 
        pkt_tx_val = 1'b0;
        pkt_tx_eop = 1'b0;
        pkt_tx_mod = 3'b0;
 
    end
 
endtask
 
 
//---
// Task to read a single packet from command file and transmit
 
task CmdTxPacket;
  input [31:0] file;
  integer count;
  integer data;
  integer i;
    begin
 
        count = $fscanf(file, "%2d", tx_length);
 
        if (count == 1) begin
 
            for (i = 0; i < tx_length; i = i + 1) begin
 
                count = $fscanf(file, "%2X", data);
                if (count) begin
                    tx_buffer[i] = data;
                end
 
            end
 
            TxPacket();
 
        end
    end
 
endtask
 
 
//---
// Task to read commands from file and stop when complete
 
task ProcessCmdFile;
  integer    file_cmd;
  integer  count;
  reg [8*8-1:0] str;
    begin
 
        file_cmd = $fopen("../../tbench/verilog/packets_tx.txt", "r");
        if (!file_cmd) $stop;
 
        while (!$feof(file_cmd)) begin
 
            count = $fscanf(file_cmd, "%s", str);
            if (count != 1) continue;
 
            $display("CMD %s", str);
 
            case (str)
 
              "SEND_PKT":
                begin
                    CmdTxPacket(file_cmd);
                end
 
            endcase
 
        end
 
        $fclose(file_cmd);
 
        WaitNS(50000);
        $stop;
 
    end
endtask
 
initial begin
    WaitNS(5000);
`ifdef XIL
    WaitNS(200000);
`endif
    ProcessCmdFile();
end
 
 
//---
// Task to read a single packet from receive interface and display
 
task RxPacket;
  reg done;
    begin
 
        done = 0;
 
        pkt_rx_ren <= 1'b1;
        @(posedge clk_156m25);
 
        while (!done) begin
 
            if (pkt_rx_val) begin
 
                if (pkt_rx_sop) begin
                    $display("\n\n------------------------");
                end
 
                $display("%x", pkt_rx_data);
 
                if (pkt_rx_eop) begin
                    done <= 1;
                    pkt_rx_ren <= 1'b0;
                end
 
                if (pkt_rx_eop) begin
                    $display("------------------------\n\n");
                end
 
            end
 
            @(posedge clk_156m25);
 
        end
 
    end
endtask
 
initial begin
 
    forever begin
 
        if (pkt_rx_avail) begin
            RxPacket();
        end
 
        @(posedge clk_156m25);
 
    end
 
end
 
endmodule

Line No.	Rev	Author	Line
1	2	antanguay	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// File name "tb_xge_mac.v" ////`
4			`//// ////`
5			`//// This file is part of the "10GE MAC" project ////`
6			`//// http://www.opencores.org/cores/xge_mac/ ////`
7			`//// ////`
8			`//// Author(s): ////`
9			`//// - A. Tanguay (antanguay@opencores.org) ////`
10			`//// ////`
11			`//////////////////////////////////////////////////////////////////////`
12			`//// ////`
13			`//// Copyright (C) 2008 AUTHORS. All rights reserved. ////`
14			`//// ////`
15			`//// This source file may be used and distributed without ////`
16			`//// restriction provided that this copyright statement is not ////`
17			`//// removed from the file and that any derivative work contains ////`
18			`//// the original copyright notice and the associated disclaimer. ////`
19			`//// ////`
20			`//// This source file is free software; you can redistribute it ////`
21			`//// and/or modify it under the terms of the GNU Lesser General ////`
22			`//// Public License as published by the Free Software Foundation; ////`
23			`//// either version 2.1 of the License, or (at your option) any ////`
24			`//// later version. ////`
25			`//// ////`
26			`//// This source is distributed in the hope that it will be ////`
27			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
28			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
29			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
30			`//// details. ////`
31			`//// ////`
32			`//// You should have received a copy of the GNU Lesser General ////`
33			`//// Public License along with this source; if not, download it ////`
34			`//// from http://www.opencores.org/lgpl.shtml ////`
35			`//// ////`
36			`//////////////////////////////////////////////////////////////////////`
37
38
39			`include "timescale.v"
40			`include "defines.v"
41
42	14	antanguay	//`define GXB
43			//`define XIL
44
45	2	antanguay	`module tb;`
46
47
48			`/AUTOREG/`
49
50			`reg [7:0] tx_buffer[0:10000];`
51			`integer tx_length;`
52
53			`reg clk_156m25;`
54	12	antanguay	`reg clk_312m50;`
55	2	antanguay	`reg clk_xgmii_rx;`
56			`reg clk_xgmii_tx;`
57
58			`reg reset_156m25_n;`
59			`reg reset_xgmii_rx_n;`
60			`reg reset_xgmii_tx_n;`
61
62			`reg pkt_rx_ren;`
63
64			`reg [63:0] pkt_tx_data;`
65			`reg pkt_tx_val;`
66			`reg pkt_tx_sop;`
67	6	antanguay	`reg pkt_tx_eop;`
68			`reg [2:0] pkt_tx_mod;`
69	2	antanguay
70			`/AUTOWIRE/`
71			`// Beginning of automatic wires (for undeclared instantiated-module outputs)`
72			`wire pkt_rx_avail; // From dut of xge_mac.v`
73			`wire [63:0] pkt_rx_data; // From dut of xge_mac.v`
74	6	antanguay	`wire pkt_rx_eop; // From dut of xge_mac.v`
75	2	antanguay	`wire pkt_rx_err; // From dut of xge_mac.v`
76	6	antanguay	`wire [2:0] pkt_rx_mod; // From dut of xge_mac.v`
77	2	antanguay	`wire pkt_rx_sop; // From dut of xge_mac.v`
78			`wire pkt_rx_val; // From dut of xge_mac.v`
79			`wire pkt_tx_full; // From dut of xge_mac.v`
80			`wire wb_ack_o; // From dut of xge_mac.v`
81			`wire [31:0] wb_dat_o; // From dut of xge_mac.v`
82			`wire wb_int_o; // From dut of xge_mac.v`
83			`wire [7:0] xgmii_txc; // From dut of xge_mac.v`
84			`wire [63:0] xgmii_txd; // From dut of xge_mac.v`
85			`// End of automatics`
86
87			`wire [7:0] wb_adr_i;`
88			`wire [31:0] wb_dat_i;`
89
90			`wire [7:0] xgmii_rxc;`
91			`wire [63:0] xgmii_rxd;`
92
93	12	antanguay	`wire [3:0] tx_dataout;`
94	2	antanguay
95	12	antanguay	`wire xaui_tx_l0_n;`
96			`wire xaui_tx_l0_p;`
97			`wire xaui_tx_l1_n;`
98			`wire xaui_tx_l1_p;`
99			`wire xaui_tx_l2_n;`
100			`wire xaui_tx_l2_p;`
101			`wire xaui_tx_l3_n;`
102			`wire xaui_tx_l3_p;`
103
104	2	antanguay	`xge_mac dut(/AUTOINST/`
105			`// Outputs`
106			`.pkt_rx_avail (pkt_rx_avail),`
107			`.pkt_rx_data (pkt_rx_data[63:0]),`
108	6	antanguay	`.pkt_rx_eop (pkt_rx_eop),`
109	2	antanguay	`.pkt_rx_err (pkt_rx_err),`
110	6	antanguay	`.pkt_rx_mod (pkt_rx_mod[2:0]),`
111	2	antanguay	`.pkt_rx_sop (pkt_rx_sop),`
112			`.pkt_rx_val (pkt_rx_val),`
113			`.pkt_tx_full (pkt_tx_full),`
114			`.wb_ack_o (wb_ack_o),`
115			`.wb_dat_o (wb_dat_o[31:0]),`
116			`.wb_int_o (wb_int_o),`
117			`.xgmii_txc (xgmii_txc[7:0]),`
118			`.xgmii_txd (xgmii_txd[63:0]),`
119			`// Inputs`
120			`.clk_156m25 (clk_156m25),`
121			`.clk_xgmii_rx (clk_xgmii_rx),`
122			`.clk_xgmii_tx (clk_xgmii_tx),`
123			`.pkt_rx_ren (pkt_rx_ren),`
124			`.pkt_tx_data (pkt_tx_data[63:0]),`
125	6	antanguay	`.pkt_tx_eop (pkt_tx_eop),`
126			`.pkt_tx_mod (pkt_tx_mod[2:0]),`
127	2	antanguay	`.pkt_tx_sop (pkt_tx_sop),`
128			`.pkt_tx_val (pkt_tx_val),`
129			`.reset_156m25_n (reset_156m25_n),`
130			`.reset_xgmii_rx_n (reset_xgmii_rx_n),`
131			`.reset_xgmii_tx_n (reset_xgmii_tx_n),`
132			`.wb_adr_i (wb_adr_i[7:0]),`
133			`.wb_clk_i (wb_clk_i),`
134			`.wb_cyc_i (wb_cyc_i),`
135			`.wb_dat_i (wb_dat_i[31:0]),`
136			`.wb_rst_i (wb_rst_i),`
137			`.wb_stb_i (wb_stb_i),`
138			`.wb_we_i (wb_we_i),`
139			`.xgmii_rxc (xgmii_rxc[7:0]),`
140			`.xgmii_rxd (xgmii_rxd[63:0]));`
141
142	12	antanguay	`ifdef GXB
143			`// Example of transceiver instance`
144			`gxb gxb(// Outputs`
145			`.rx_ctrldetect ({xgmii_rxc[7],`
146			`xgmii_rxc[5],`
147			`xgmii_rxc[3],`
148			`xgmii_rxc[1],`
149			`xgmii_rxc[6],`
150			`xgmii_rxc[4],`
151			`xgmii_rxc[2],`
152			`xgmii_rxc[0]}),`
153			`.rx_dataout ({xgmii_rxd[63:56],`
154			`xgmii_rxd[47:40],`
155			`xgmii_rxd[31:24],`
156			`xgmii_rxd[15:8],`
157			`xgmii_rxd[55:48],`
158			`xgmii_rxd[39:32],`
159			`xgmii_rxd[23:16],`
160			`xgmii_rxd[7:0]}),`
161			`.tx_dataout (tx_dataout[3:0]),`
162			`// Inputs`
163			`.pll_inclk (clk_156m25),`
164			`.rx_analogreset (~reset_156m25_n),`
165			`.rx_cruclk ({clk_156m25, clk_156m25, clk_156m25, clk_156m25}),`
166			`.rx_datain (tx_dataout[3:0]),`
167			`.rx_digitalreset (~reset_156m25_n),`
168			`.tx_ctrlenable ({xgmii_txc[7],`
169			`xgmii_txc[5],`
170			`xgmii_txc[3],`
171			`xgmii_txc[1],`
172			`xgmii_txc[6],`
173			`xgmii_txc[4],`
174			`xgmii_txc[2],`
175			`xgmii_txc[0]}),`
176			`.tx_datain ({xgmii_txd[63:56],`
177			`xgmii_txd[47:40],`
178			`xgmii_txd[31:24],`
179			`xgmii_txd[15:8],`
180			`xgmii_txd[55:48],`
181			`xgmii_txd[39:32],`
182			`xgmii_txd[23:16],`
183			`xgmii_txd[7:0]}),`
184			`.tx_digitalreset (~reset_156m25_n));`
185			`endif
186	2	antanguay
187	12	antanguay	`ifdef XIL
188			`// Example of transceiver instance`
189			`xaui_block xaui(// Outputs`
190			`.txoutclk (),`
191			`.xgmii_rxd (xgmii_rxd[63:0]),`
192			`.xgmii_rxc (xgmii_rxc[7:0]),`
193			`.xaui_tx_l0_p (xaui_tx_l0_p),`
194			`.xaui_tx_l0_n (xaui_tx_l0_n),`
195			`.xaui_tx_l1_p (xaui_tx_l1_p),`
196			`.xaui_tx_l1_n (xaui_tx_l1_n),`
197			`.xaui_tx_l2_p (xaui_tx_l2_p),`
198			`.xaui_tx_l2_n (xaui_tx_l2_n),`
199			`.xaui_tx_l3_p (xaui_tx_l3_p),`
200			`.xaui_tx_l3_n (xaui_tx_l3_n),`
201			`.txlock (),`
202			`.align_status (),`
203			`.sync_status (),`
204			`.mgt_tx_ready (),`
205			`.drp_o (),`
206			`.drp_rdy (),`
207			`.status_vector (),`
208			`// Inputs`
209			`.dclk (clk_156m25),`
210			`.clk156 (clk_156m25),`
211			`.clk312 (clk_312m50),`
212			`.refclk (clk_156m25),`
213			`.reset (~reset_156m25_n),`
214			`.reset156 (~reset_156m25_n),`
215			`.xgmii_txd (xgmii_txd[63:0]),`
216			`.xgmii_txc (xgmii_txc[7:0]),`
217			`.xaui_rx_l0_p (xaui_tx_l0_p),`
218			`.xaui_rx_l0_n (xaui_tx_l0_n),`
219			`.xaui_rx_l1_p (xaui_tx_l1_p),`
220			`.xaui_rx_l1_n (xaui_tx_l1_n),`
221			`.xaui_rx_l2_p (xaui_tx_l2_p),`
222			`.xaui_rx_l2_n (xaui_tx_l2_n),`
223			`.xaui_rx_l3_p (xaui_tx_l3_p),`
224			`.xaui_rx_l3_n (xaui_tx_l3_n),`
225			`.signal_detect (4'b1111),`
226			`.drp_addr (7'b0),`
227			`.drp_en (2'b0),`
228			`.drp_i (16'b0),`
229			`.drp_we (2'b0),`
230			`.configuration_vector (7'b0));`
231
232			`glbl glbl();`
233			`endif
234
235	2	antanguay	`//---`
236			`// Unused for this testbench`
237
238			`assign wb_adr_i = 8'b0;`
239			`assign wb_clk_i = 1'b0;`
240			`assign wb_cyc_i = 1'b0;`
241			`assign wb_dat_i = 32'b0;`
242			`assign wb_rst_i = 1'b1;`
243			`assign wb_stb_i = 1'b0;`
244			`assign wb_we_i = 1'b0;`
245
246
247			`//---`
248			`// XGMII Loopback`
249	12	antanguay	`// This test is done with loopback on XGMII or using one of the tranceiver examples`
250	2	antanguay
251	12	antanguay	`ifndef GXB
252			`ifndef XIL
253			`assign xgmii_rxc = xgmii_txc;`
254			`assign xgmii_rxd = xgmii_txd;`
255			`endif
256			`endif
257	2	antanguay
258			`//---`
259			`// Clock generation`
260
261			`initial begin`
262			`clk_156m25 = 1'b0;`
263			`clk_xgmii_rx = 1'b0;`
264			`clk_xgmii_tx = 1'b0;`
265			`forever begin`
266			`WaitPS(3200);`
267			`clk_156m25 = ~clk_156m25;`
268			`clk_xgmii_rx = ~clk_xgmii_rx;`
269			`clk_xgmii_tx = ~clk_xgmii_tx;`
270			`end`
271	12	antanguay	`end`
272	2	antanguay
273	12	antanguay	`initial begin`
274			`clk_312m50 = 1'b0;`
275			`forever begin`
276			`WaitPS(1600);`
277			`clk_312m50 = ~clk_312m50;`
278			`end`
279			`end`
280	2	antanguay
281			`//---`
282			`// Reset Generation`
283
284			`initial begin`
285			`reset_156m25_n = 1'b0;`
286			`reset_xgmii_rx_n = 1'b0;`
287			`reset_xgmii_tx_n = 1'b0;`
288			`WaitNS(20);`
289			`reset_156m25_n = 1'b1;`
290			`reset_xgmii_rx_n = 1'b1;`
291			`reset_xgmii_tx_n = 1'b1;`
292			`end`
293
294
295			`//---`
296			`// Init signals`
297
298			`initial begin`
299
300			`for (tx_length = 0; tx_length <= 1000; tx_length = tx_length + 1) begin`
301			`tx_buffer[tx_length] = 0;`
302			`end`
303
304			`pkt_rx_ren = 1'b0;`
305
306			`pkt_tx_data = 64'b0;`
307			`pkt_tx_val = 1'b0;`
308			`pkt_tx_sop = 1'b0;`
309	6	antanguay	`pkt_tx_eop = 1'b0;`
310			`pkt_tx_mod = 3'b0;`
311	2	antanguay
312			`end`
313
314			`task WaitNS;`
315			`input [31:0] delay;`
316			`begin`
317			`#(1000*delay);`
318			`end`
319			`endtask`
320
321			`task WaitPS;`
322			`input [31:0] delay;`
323			`begin`
324			`#(delay);`
325			`end`
326			`endtask`
327
328
329			`//---`
330			`// Task to send a single packet`
331
332			`task TxPacket;`
333			`integer i;`
334			`begin`
335
336			`$display("Transmit packet with length: %d", tx_length);`
337
338			`@(posedge clk_156m25);`
339			`WaitNS(1);`
340			`pkt_tx_val = 1'b1;`
341
342			`for (i = 0; i < tx_length; i = i + 8) begin`
343
344			`pkt_tx_sop = 1'b0;`
345	6	antanguay	`pkt_tx_eop = 1'b0;`
346			`pkt_tx_mod = 2'b0;`
347	2	antanguay
348			`if (i == 0) pkt_tx_sop = 1'b1;`
349
350	6	antanguay	`if (i + 8 >= tx_length) begin`
351			`pkt_tx_eop = 1'b1;`
352			`pkt_tx_mod = tx_length % 8;`
353			`end`
354
355	12	antanguay	pkt_tx_data[`LANE7] = tx_buffer[i];
356			pkt_tx_data[`LANE6] = tx_buffer[i+1];
357			pkt_tx_data[`LANE5] = tx_buffer[i+2];
358			pkt_tx_data[`LANE4] = tx_buffer[i+3];
359			pkt_tx_data[`LANE3] = tx_buffer[i+4];
360			pkt_tx_data[`LANE2] = tx_buffer[i+5];
361			pkt_tx_data[`LANE1] = tx_buffer[i+6];
362			pkt_tx_data[`LANE0] = tx_buffer[i+7];
363	2	antanguay
364			`@(posedge clk_156m25);`
365			`WaitNS(1);`
366
367			`end`
368
369			`pkt_tx_val = 1'b0;`
370	6	antanguay	`pkt_tx_eop = 1'b0;`
371			`pkt_tx_mod = 3'b0;`
372	2	antanguay
373			`end`
374
375			`endtask`
376
377
378			`//---`
379			`// Task to read a single packet from command file and transmit`
380
381			`task CmdTxPacket;`
382			`input [31:0] file;`
383			`integer count;`
384			`integer data;`
385			`integer i;`
386			`begin`
387
388			`count = $fscanf(file, "%2d", tx_length);`
389
390			`if (count == 1) begin`
391
392			`for (i = 0; i < tx_length; i = i + 1) begin`
393	12	antanguay
394	2	antanguay	`count = $fscanf(file, "%2X", data);`
395			`if (count) begin`
396			`tx_buffer[i] = data;`
397			`end`
398
399			`end`
400
401			`TxPacket();`
402
403			`end`
404			`end`
405
406			`endtask`
407
408
409			`//---`
410			`// Task to read commands from file and stop when complete`
411
412			`task ProcessCmdFile;`
413			`integer file_cmd;`
414			`integer count;`
415			`reg [8*8-1:0] str;`
416			`begin`
417
418			`file_cmd = $fopen("../../tbench/verilog/packets_tx.txt", "r");`
419			`if (!file_cmd) $stop;`
420
421			`while (!$feof(file_cmd)) begin`
422
423			`count = $fscanf(file_cmd, "%s", str);`
424	16	antanguay	`if (count != 1) continue;`
425	2	antanguay
426			`$display("CMD %s", str);`
427
428			`case (str)`
429
430	12	antanguay	`"SEND_PKT":`
431	2	antanguay	`begin`
432			`CmdTxPacket(file_cmd);`
433			`end`
434
435			`endcase`
436
437			`end`
438
439			`$fclose(file_cmd);`
440
441	12	antanguay	`WaitNS(50000);`
442	2	antanguay	`$stop;`
443
444			`end`
445			`endtask`
446
447			`initial begin`
448	12	antanguay	`WaitNS(5000);`
449			`ifdef XIL
450			`WaitNS(200000);`
451			`endif
452	2	antanguay	`ProcessCmdFile();`
453			`end`
454
455
456			`//---`
457			`// Task to read a single packet from receive interface and display`
458
459			`task RxPacket;`
460			`reg done;`
461			`begin`
462
463			`done = 0;`
464
465			`pkt_rx_ren <= 1'b1;`
466			`@(posedge clk_156m25);`
467
468			`while (!done) begin`
469
470			`if (pkt_rx_val) begin`
471
472			`if (pkt_rx_sop) begin`
473			`$display("\n\n------------------------");`
474			`end`
475
476			`$display("%x", pkt_rx_data);`
477
478			`if (pkt_rx_eop) begin`
479			`done <= 1;`
480			`pkt_rx_ren <= 1'b0;`
481			`end`
482
483			`if (pkt_rx_eop) begin`
484			`$display("------------------------\n\n");`
485			`end`
486
487			`end`
488
489			`@(posedge clk_156m25);`
490
491			`end`
492
493			`end`
494			`endtask`
495
496			`initial begin`
497	12	antanguay
498	2	antanguay	`forever begin`
499
500			`if (pkt_rx_avail) begin`

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