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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  File name "tb_xge_mac.v"                                    ////
////                                                              ////
////  This file is part of the "10GE MAC" project                 ////
////  http://www.opencores.org/cores/xge_mac/                     ////
////                                                              ////
////  Author(s):                                                  ////
////      - A. Tanguay (antanguay@opencores.org)                  ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2008 AUTHORS. All rights reserved.             ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
 
 
`include "timescale.v"
`include "defines.v"
 
//`define GXB
//`define XIL
 
module tb;
 
 
/*AUTOREG*/
 
reg [7:0]     tx_buffer[0:10000];
integer       tx_length;
 
reg           clk_156m25;
reg           clk_312m50;
reg           clk_xgmii_rx;
reg           clk_xgmii_tx;
 
reg           reset_156m25_n;
reg           reset_xgmii_rx_n;
reg           reset_xgmii_tx_n;
 
reg           pkt_rx_ren;
 
reg  [63:0]   pkt_tx_data;
reg           pkt_tx_val;
reg           pkt_tx_sop;
reg           pkt_tx_eop;
reg  [2:0]    pkt_tx_mod;
 
integer       tx_count;
integer       rx_count;
 
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire                    pkt_rx_avail;           // From dut of xge_mac.v
wire [63:0]             pkt_rx_data;            // From dut of xge_mac.v
wire                    pkt_rx_eop;             // From dut of xge_mac.v
wire                    pkt_rx_err;             // From dut of xge_mac.v
wire [2:0]              pkt_rx_mod;             // From dut of xge_mac.v
wire                    pkt_rx_sop;             // From dut of xge_mac.v
wire                    pkt_rx_val;             // From dut of xge_mac.v
wire                    pkt_tx_full;            // From dut of xge_mac.v
wire                    wb_ack_o;               // From dut of xge_mac.v
wire [31:0]             wb_dat_o;               // From dut of xge_mac.v
wire                    wb_int_o;               // From dut of xge_mac.v
wire [7:0]              xgmii_txc;              // From dut of xge_mac.v
wire [63:0]             xgmii_txd;              // From dut of xge_mac.v
// End of automatics
 
wire  [7:0]   wb_adr_i;
wire  [31:0]  wb_dat_i;
 
wire [7:0]              xgmii_rxc;
wire [63:0]             xgmii_rxd;
 
wire [3:0]              tx_dataout;
 
wire                    xaui_tx_l0_n;
wire                    xaui_tx_l0_p;
wire                    xaui_tx_l1_n;
wire                    xaui_tx_l1_p;
wire                    xaui_tx_l2_n;
wire                    xaui_tx_l2_p;
wire                    xaui_tx_l3_n;
wire                    xaui_tx_l3_p;
 
xge_mac dut(/*AUTOINST*/
            // Outputs
            .pkt_rx_avail               (pkt_rx_avail),
            .pkt_rx_data                (pkt_rx_data[63:0]),
            .pkt_rx_eop                 (pkt_rx_eop),
            .pkt_rx_err                 (pkt_rx_err),
            .pkt_rx_mod                 (pkt_rx_mod[2:0]),
            .pkt_rx_sop                 (pkt_rx_sop),
            .pkt_rx_val                 (pkt_rx_val),
            .pkt_tx_full                (pkt_tx_full),
            .wb_ack_o                   (wb_ack_o),
            .wb_dat_o                   (wb_dat_o[31:0]),
            .wb_int_o                   (wb_int_o),
            .xgmii_txc                  (xgmii_txc[7:0]),
            .xgmii_txd                  (xgmii_txd[63:0]),
            // Inputs
            .clk_156m25                 (clk_156m25),
            .clk_xgmii_rx               (clk_xgmii_rx),
            .clk_xgmii_tx               (clk_xgmii_tx),
            .pkt_rx_ren                 (pkt_rx_ren),
            .pkt_tx_data                (pkt_tx_data[63:0]),
            .pkt_tx_eop                 (pkt_tx_eop),
            .pkt_tx_mod                 (pkt_tx_mod[2:0]),
            .pkt_tx_sop                 (pkt_tx_sop),
            .pkt_tx_val                 (pkt_tx_val),
            .reset_156m25_n             (reset_156m25_n),
            .reset_xgmii_rx_n           (reset_xgmii_rx_n),
            .reset_xgmii_tx_n           (reset_xgmii_tx_n),
            .wb_adr_i                   (wb_adr_i[7:0]),
            .wb_clk_i                   (wb_clk_i),
            .wb_cyc_i                   (wb_cyc_i),
            .wb_dat_i                   (wb_dat_i[31:0]),
            .wb_rst_i                   (wb_rst_i),
            .wb_stb_i                   (wb_stb_i),
            .wb_we_i                    (wb_we_i),
            .xgmii_rxc                  (xgmii_rxc[7:0]),
            .xgmii_rxd                  (xgmii_rxd[63:0]));
 
`ifdef GXB
// Example of transceiver instance
gxb gxb(// Outputs
        .rx_ctrldetect                  ({xgmii_rxc[7],
                                          xgmii_rxc[5],
                                          xgmii_rxc[3],
                                          xgmii_rxc[1],
                                          xgmii_rxc[6],
                                          xgmii_rxc[4],
                                          xgmii_rxc[2],
                                          xgmii_rxc[0]}),
        .rx_dataout                     ({xgmii_rxd[63:56],
                                          xgmii_rxd[47:40],
                                          xgmii_rxd[31:24],
                                          xgmii_rxd[15:8],
                                          xgmii_rxd[55:48],
                                          xgmii_rxd[39:32],
                                          xgmii_rxd[23:16],
                                          xgmii_rxd[7:0]}),
        .tx_dataout                     (tx_dataout[3:0]),
        // Inputs
        .pll_inclk                      (clk_156m25),
        .rx_analogreset                 (~reset_156m25_n),
        .rx_cruclk                      ({clk_156m25, clk_156m25, clk_156m25, clk_156m25}),
        .rx_datain                      (tx_dataout[3:0]),
        .rx_digitalreset                (~reset_156m25_n),
        .tx_ctrlenable                  ({xgmii_txc[7],
                                          xgmii_txc[5],
                                          xgmii_txc[3],
                                          xgmii_txc[1],
                                          xgmii_txc[6],
                                          xgmii_txc[4],
                                          xgmii_txc[2],
                                          xgmii_txc[0]}),
        .tx_datain                      ({xgmii_txd[63:56],
                                          xgmii_txd[47:40],
                                          xgmii_txd[31:24],
                                          xgmii_txd[15:8],
                                          xgmii_txd[55:48],
                                          xgmii_txd[39:32],
                                          xgmii_txd[23:16],
                                          xgmii_txd[7:0]}),
        .tx_digitalreset                (~reset_156m25_n));
`endif
 
`ifdef XIL
// Example of transceiver instance
xaui_block xaui(// Outputs
                .txoutclk               (),
                .xgmii_rxd              (xgmii_rxd[63:0]),
                .xgmii_rxc              (xgmii_rxc[7:0]),
                .xaui_tx_l0_p           (xaui_tx_l0_p),
                .xaui_tx_l0_n           (xaui_tx_l0_n),
                .xaui_tx_l1_p           (xaui_tx_l1_p),
                .xaui_tx_l1_n           (xaui_tx_l1_n),
                .xaui_tx_l2_p           (xaui_tx_l2_p),
                .xaui_tx_l2_n           (xaui_tx_l2_n),
                .xaui_tx_l3_p           (xaui_tx_l3_p),
                .xaui_tx_l3_n           (xaui_tx_l3_n),
                .txlock                 (),
                .align_status           (),
                .sync_status            (),
                .mgt_tx_ready           (),
                .drp_o                  (),
                .drp_rdy                (),
                .status_vector          (),
                // Inputs
                .dclk                   (clk_156m25),
                .clk156                 (clk_156m25),
                .clk312                 (clk_312m50),
                .refclk                 (clk_156m25),
                .reset                  (~reset_156m25_n),
                .reset156               (~reset_156m25_n),
                .xgmii_txd              (xgmii_txd[63:0]),
                .xgmii_txc              (xgmii_txc[7:0]),
                .xaui_rx_l0_p           (xaui_tx_l0_p),
                .xaui_rx_l0_n           (xaui_tx_l0_n),
                .xaui_rx_l1_p           (xaui_tx_l1_p),
                .xaui_rx_l1_n           (xaui_tx_l1_n),
                .xaui_rx_l2_p           (xaui_tx_l2_p),
                .xaui_rx_l2_n           (xaui_tx_l2_n),
                .xaui_rx_l3_p           (xaui_tx_l3_p),
                .xaui_rx_l3_n           (xaui_tx_l3_n),
                .signal_detect          (4'b1111),
                .drp_addr               (7'b0),
                .drp_en                 (2'b0),
                .drp_i                  (16'b0),
                .drp_we                 (2'b0),
                .configuration_vector   (7'b0));
 
glbl glbl();
`endif
 
//---
// Unused for this testbench
 
assign wb_adr_i = 8'b0;
assign wb_clk_i = 1'b0;
assign wb_cyc_i = 1'b0;
assign wb_dat_i = 32'b0;
assign wb_rst_i = 1'b1;
assign wb_stb_i = 1'b0;
assign wb_we_i = 1'b0;
 
 
initial begin
    tx_count = 0;
    rx_count = 0;
end
 
//---
// XGMII Loopback
// This test is done with loopback on XGMII or using one of the tranceiver examples
 
`ifndef GXB
  `ifndef XIL
    assign xgmii_rxc = xgmii_txc;
    assign xgmii_rxd = xgmii_txd;
  `endif
`endif
 
//---
// Clock generation
 
initial begin
    clk_156m25 = 1'b0;
    clk_xgmii_rx = 1'b0;
    clk_xgmii_tx = 1'b0;
    forever begin
        WaitPS(3200);
        clk_156m25 = ~clk_156m25;
        clk_xgmii_rx = ~clk_xgmii_rx;
        clk_xgmii_tx = ~clk_xgmii_tx;
    end
end
 
initial begin
    clk_312m50 = 1'b0;
    forever begin
        WaitPS(1600);
        clk_312m50 = ~clk_312m50;
    end
end
 
//---
// Reset Generation
 
initial begin
    reset_156m25_n = 1'b0;
    reset_xgmii_rx_n = 1'b0;
    reset_xgmii_tx_n = 1'b0;
    WaitNS(20);
    reset_156m25_n = 1'b1;
    reset_xgmii_rx_n = 1'b1;
    reset_xgmii_tx_n = 1'b1;
end
 
 
//---
// Init signals
 
initial begin
 
    for (tx_length = 0; tx_length <= 1000; tx_length = tx_length + 1) begin
        tx_buffer[tx_length] = 0;
    end
 
    pkt_rx_ren = 1'b0;
 
    pkt_tx_data = 64'b0;
    pkt_tx_val = 1'b0;
    pkt_tx_sop = 1'b0;
    pkt_tx_eop = 1'b0;
    pkt_tx_mod = 3'b0;
 
end
 
task WaitNS;
  input [31:0] delay;
    begin
        #(1000*delay);
    end
endtask
 
task WaitPS;
  input [31:0] delay;
    begin
        #(delay);
    end
endtask
 
 
//---
// Task to send a single packet
 
task TxPacket;
  integer        i;
    begin
 
        $display("Transmit packet with length: %d", tx_length);
 
        @(posedge clk_156m25);
        WaitNS(1);
        pkt_tx_val = 1'b1;
 
        for (i = 0; i < tx_length; i = i + 8) begin
 
            pkt_tx_sop = 1'b0;
            pkt_tx_eop = 1'b0;
            pkt_tx_mod = 2'b0;
 
            if (i == 0) pkt_tx_sop = 1'b1;
 
            if (i + 8 >= tx_length) begin
                pkt_tx_eop = 1'b1;
                pkt_tx_mod = tx_length % 8;
            end
 
            pkt_tx_data[`LANE7] = tx_buffer[i];
            pkt_tx_data[`LANE6] = tx_buffer[i+1];
            pkt_tx_data[`LANE5] = tx_buffer[i+2];
            pkt_tx_data[`LANE4] = tx_buffer[i+3];
            pkt_tx_data[`LANE3] = tx_buffer[i+4];
            pkt_tx_data[`LANE2] = tx_buffer[i+5];
            pkt_tx_data[`LANE1] = tx_buffer[i+6];
            pkt_tx_data[`LANE0] = tx_buffer[i+7];
 
            @(posedge clk_156m25);
            WaitNS(1);
 
        end
 
        pkt_tx_val = 1'b0;
        pkt_tx_eop = 1'b0;
        pkt_tx_mod = 3'b0;
 
        tx_count = tx_count + 1;
 
    end
 
endtask
 
 
//---
// Task to read a single packet from command file and transmit
 
task CmdTxPacket;
  input [31:0] file;
  integer count;
  integer data;
  integer i;
    begin
 
        count = $fscanf(file, "%2d", tx_length);
 
        if (count == 1) begin
 
            for (i = 0; i < tx_length; i = i + 1) begin
 
                count = $fscanf(file, "%2X", data);
                if (count) begin
                    tx_buffer[i] = data;
                end
 
            end
 
            TxPacket();
 
        end
    end
 
endtask
 
 
//---
// Task to read commands from file and stop when complete
 
task ProcessCmdFile;
  integer    file_cmd;
  integer  count;
  reg [8*8-1:0] str;
    begin
 
        file_cmd = $fopen("../../tbench/verilog/packets_tx.txt", "r");
        if (!file_cmd) $stop;
 
        while (!$feof(file_cmd)) begin
 
            count = $fscanf(file_cmd, "%s", str);
            if (count != 1) continue;
 
            $display("CMD %s", str);
 
            case (str)
 
              "SEND_PKT":
                begin
                    CmdTxPacket(file_cmd);
                end
 
            endcase
 
        end
 
        $fclose(file_cmd);
 
        WaitNS(50000);
        $stop;
 
    end
endtask
 
initial begin
    WaitNS(5000);
`ifdef XIL
    WaitNS(200000);
`endif
    ProcessCmdFile();
end
 
 
//---
// Task to read a single packet from receive interface and display
 
task RxPacket;
  reg done;
    begin
 
        done = 0;
 
        pkt_rx_ren <= 1'b1;
        @(posedge clk_156m25);
 
        while (!done) begin
 
            if (pkt_rx_val) begin
 
                if (pkt_rx_sop) begin
                    $display("\n\n------------------------");
                    $display("Received Packet");
                    $display("------------------------");
                end
 
                $display("%x", pkt_rx_data);
 
                if (pkt_rx_eop) begin
                    done <= 1;
                    pkt_rx_ren <= 1'b0;
                end
 
                if (pkt_rx_eop) begin
                    $display("------------------------\n\n");
                end
 
            end
 
            @(posedge clk_156m25);
 
        end
 
        rx_count = rx_count + 1;
 
    end
endtask
 
initial begin
 
    forever begin
 
        if (pkt_rx_avail) begin
 
            RxPacket();
 
            if (rx_count == tx_count) begin
                $display("All packets received. Sumulation done!!!\n");
            end
 
        end
 
        @(posedge clk_156m25);
 
    end
 
end
 
endmodule

Line No.	Rev	Author	Line
1	2	antanguay	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// File name "tb_xge_mac.v" ////`
4			`//// ////`
5			`//// This file is part of the "10GE MAC" project ////`
6			`//// http://www.opencores.org/cores/xge_mac/ ////`
7			`//// ////`
8			`//// Author(s): ////`
9			`//// - A. Tanguay (antanguay@opencores.org) ////`
10			`//// ////`
11			`//////////////////////////////////////////////////////////////////////`
12			`//// ////`
13			`//// Copyright (C) 2008 AUTHORS. All rights reserved. ////`
14			`//// ////`
15			`//// This source file may be used and distributed without ////`
16			`//// restriction provided that this copyright statement is not ////`
17			`//// removed from the file and that any derivative work contains ////`
18			`//// the original copyright notice and the associated disclaimer. ////`
19			`//// ////`
20			`//// This source file is free software; you can redistribute it ////`
21			`//// and/or modify it under the terms of the GNU Lesser General ////`
22			`//// Public License as published by the Free Software Foundation; ////`
23			`//// either version 2.1 of the License, or (at your option) any ////`
24			`//// later version. ////`
25			`//// ////`
26			`//// This source is distributed in the hope that it will be ////`
27			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
28			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
29			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
30			`//// details. ////`
31			`//// ////`
32			`//// You should have received a copy of the GNU Lesser General ////`
33			`//// Public License along with this source; if not, download it ////`
34			`//// from http://www.opencores.org/lgpl.shtml ////`
35			`//// ////`
36			`//////////////////////////////////////////////////////////////////////`
37
38
39			`include "timescale.v"
40			`include "defines.v"
41
42	14	antanguay	//`define GXB
43			//`define XIL
44
45	2	antanguay	`module tb;`
46
47
48			`/AUTOREG/`
49
50			`reg [7:0] tx_buffer[0:10000];`
51			`integer tx_length;`
52
53			`reg clk_156m25;`
54	12	antanguay	`reg clk_312m50;`
55	2	antanguay	`reg clk_xgmii_rx;`
56			`reg clk_xgmii_tx;`
57
58			`reg reset_156m25_n;`
59			`reg reset_xgmii_rx_n;`
60			`reg reset_xgmii_tx_n;`
61
62			`reg pkt_rx_ren;`
63
64			`reg [63:0] pkt_tx_data;`
65			`reg pkt_tx_val;`
66			`reg pkt_tx_sop;`
67	6	antanguay	`reg pkt_tx_eop;`
68			`reg [2:0] pkt_tx_mod;`
69	2	antanguay
70	17	antanguay	`integer tx_count;`
71			`integer rx_count;`
72
73	2	antanguay	`/AUTOWIRE/`
74			`// Beginning of automatic wires (for undeclared instantiated-module outputs)`
75			`wire pkt_rx_avail; // From dut of xge_mac.v`
76			`wire [63:0] pkt_rx_data; // From dut of xge_mac.v`
77	6	antanguay	`wire pkt_rx_eop; // From dut of xge_mac.v`
78	2	antanguay	`wire pkt_rx_err; // From dut of xge_mac.v`
79	6	antanguay	`wire [2:0] pkt_rx_mod; // From dut of xge_mac.v`
80	2	antanguay	`wire pkt_rx_sop; // From dut of xge_mac.v`
81			`wire pkt_rx_val; // From dut of xge_mac.v`
82			`wire pkt_tx_full; // From dut of xge_mac.v`
83			`wire wb_ack_o; // From dut of xge_mac.v`
84			`wire [31:0] wb_dat_o; // From dut of xge_mac.v`
85			`wire wb_int_o; // From dut of xge_mac.v`
86			`wire [7:0] xgmii_txc; // From dut of xge_mac.v`
87			`wire [63:0] xgmii_txd; // From dut of xge_mac.v`
88			`// End of automatics`
89
90			`wire [7:0] wb_adr_i;`
91			`wire [31:0] wb_dat_i;`
92
93			`wire [7:0] xgmii_rxc;`
94			`wire [63:0] xgmii_rxd;`
95
96	12	antanguay	`wire [3:0] tx_dataout;`
97	2	antanguay
98	12	antanguay	`wire xaui_tx_l0_n;`
99			`wire xaui_tx_l0_p;`
100			`wire xaui_tx_l1_n;`
101			`wire xaui_tx_l1_p;`
102			`wire xaui_tx_l2_n;`
103			`wire xaui_tx_l2_p;`
104			`wire xaui_tx_l3_n;`
105			`wire xaui_tx_l3_p;`
106
107	2	antanguay	`xge_mac dut(/AUTOINST/`
108			`// Outputs`
109			`.pkt_rx_avail (pkt_rx_avail),`
110			`.pkt_rx_data (pkt_rx_data[63:0]),`
111	6	antanguay	`.pkt_rx_eop (pkt_rx_eop),`
112	2	antanguay	`.pkt_rx_err (pkt_rx_err),`
113	6	antanguay	`.pkt_rx_mod (pkt_rx_mod[2:0]),`
114	2	antanguay	`.pkt_rx_sop (pkt_rx_sop),`
115			`.pkt_rx_val (pkt_rx_val),`
116			`.pkt_tx_full (pkt_tx_full),`
117			`.wb_ack_o (wb_ack_o),`
118			`.wb_dat_o (wb_dat_o[31:0]),`
119			`.wb_int_o (wb_int_o),`
120			`.xgmii_txc (xgmii_txc[7:0]),`
121			`.xgmii_txd (xgmii_txd[63:0]),`
122			`// Inputs`
123			`.clk_156m25 (clk_156m25),`
124			`.clk_xgmii_rx (clk_xgmii_rx),`
125			`.clk_xgmii_tx (clk_xgmii_tx),`
126			`.pkt_rx_ren (pkt_rx_ren),`
127			`.pkt_tx_data (pkt_tx_data[63:0]),`
128	6	antanguay	`.pkt_tx_eop (pkt_tx_eop),`
129			`.pkt_tx_mod (pkt_tx_mod[2:0]),`
130	2	antanguay	`.pkt_tx_sop (pkt_tx_sop),`
131			`.pkt_tx_val (pkt_tx_val),`
132			`.reset_156m25_n (reset_156m25_n),`
133			`.reset_xgmii_rx_n (reset_xgmii_rx_n),`
134			`.reset_xgmii_tx_n (reset_xgmii_tx_n),`
135			`.wb_adr_i (wb_adr_i[7:0]),`
136			`.wb_clk_i (wb_clk_i),`
137			`.wb_cyc_i (wb_cyc_i),`
138			`.wb_dat_i (wb_dat_i[31:0]),`
139			`.wb_rst_i (wb_rst_i),`
140			`.wb_stb_i (wb_stb_i),`
141			`.wb_we_i (wb_we_i),`
142			`.xgmii_rxc (xgmii_rxc[7:0]),`
143			`.xgmii_rxd (xgmii_rxd[63:0]));`
144
145	12	antanguay	`ifdef GXB
146			`// Example of transceiver instance`
147			`gxb gxb(// Outputs`
148			`.rx_ctrldetect ({xgmii_rxc[7],`
149			`xgmii_rxc[5],`
150			`xgmii_rxc[3],`
151			`xgmii_rxc[1],`
152			`xgmii_rxc[6],`
153			`xgmii_rxc[4],`
154			`xgmii_rxc[2],`
155			`xgmii_rxc[0]}),`
156			`.rx_dataout ({xgmii_rxd[63:56],`
157			`xgmii_rxd[47:40],`
158			`xgmii_rxd[31:24],`
159			`xgmii_rxd[15:8],`
160			`xgmii_rxd[55:48],`
161			`xgmii_rxd[39:32],`
162			`xgmii_rxd[23:16],`
163			`xgmii_rxd[7:0]}),`
164			`.tx_dataout (tx_dataout[3:0]),`
165			`// Inputs`
166			`.pll_inclk (clk_156m25),`
167			`.rx_analogreset (~reset_156m25_n),`
168			`.rx_cruclk ({clk_156m25, clk_156m25, clk_156m25, clk_156m25}),`
169			`.rx_datain (tx_dataout[3:0]),`
170			`.rx_digitalreset (~reset_156m25_n),`
171			`.tx_ctrlenable ({xgmii_txc[7],`
172			`xgmii_txc[5],`
173			`xgmii_txc[3],`
174			`xgmii_txc[1],`
175			`xgmii_txc[6],`
176			`xgmii_txc[4],`
177			`xgmii_txc[2],`
178			`xgmii_txc[0]}),`
179			`.tx_datain ({xgmii_txd[63:56],`
180			`xgmii_txd[47:40],`
181			`xgmii_txd[31:24],`
182			`xgmii_txd[15:8],`
183			`xgmii_txd[55:48],`
184			`xgmii_txd[39:32],`
185			`xgmii_txd[23:16],`
186			`xgmii_txd[7:0]}),`
187			`.tx_digitalreset (~reset_156m25_n));`
188			`endif
189	2	antanguay
190	12	antanguay	`ifdef XIL
191			`// Example of transceiver instance`
192			`xaui_block xaui(// Outputs`
193			`.txoutclk (),`
194			`.xgmii_rxd (xgmii_rxd[63:0]),`
195			`.xgmii_rxc (xgmii_rxc[7:0]),`
196			`.xaui_tx_l0_p (xaui_tx_l0_p),`
197			`.xaui_tx_l0_n (xaui_tx_l0_n),`
198			`.xaui_tx_l1_p (xaui_tx_l1_p),`
199			`.xaui_tx_l1_n (xaui_tx_l1_n),`
200			`.xaui_tx_l2_p (xaui_tx_l2_p),`
201			`.xaui_tx_l2_n (xaui_tx_l2_n),`
202			`.xaui_tx_l3_p (xaui_tx_l3_p),`
203			`.xaui_tx_l3_n (xaui_tx_l3_n),`
204			`.txlock (),`
205			`.align_status (),`
206			`.sync_status (),`
207			`.mgt_tx_ready (),`
208			`.drp_o (),`
209			`.drp_rdy (),`
210			`.status_vector (),`
211			`// Inputs`
212			`.dclk (clk_156m25),`
213			`.clk156 (clk_156m25),`
214			`.clk312 (clk_312m50),`
215			`.refclk (clk_156m25),`
216			`.reset (~reset_156m25_n),`
217			`.reset156 (~reset_156m25_n),`
218			`.xgmii_txd (xgmii_txd[63:0]),`
219			`.xgmii_txc (xgmii_txc[7:0]),`
220			`.xaui_rx_l0_p (xaui_tx_l0_p),`
221			`.xaui_rx_l0_n (xaui_tx_l0_n),`
222			`.xaui_rx_l1_p (xaui_tx_l1_p),`
223			`.xaui_rx_l1_n (xaui_tx_l1_n),`
224			`.xaui_rx_l2_p (xaui_tx_l2_p),`
225			`.xaui_rx_l2_n (xaui_tx_l2_n),`
226			`.xaui_rx_l3_p (xaui_tx_l3_p),`
227			`.xaui_rx_l3_n (xaui_tx_l3_n),`
228			`.signal_detect (4'b1111),`
229			`.drp_addr (7'b0),`
230			`.drp_en (2'b0),`
231			`.drp_i (16'b0),`
232			`.drp_we (2'b0),`
233			`.configuration_vector (7'b0));`
234
235			`glbl glbl();`
236			`endif
237
238	2	antanguay	`//---`
239			`// Unused for this testbench`
240
241			`assign wb_adr_i = 8'b0;`
242			`assign wb_clk_i = 1'b0;`
243			`assign wb_cyc_i = 1'b0;`
244			`assign wb_dat_i = 32'b0;`
245			`assign wb_rst_i = 1'b1;`
246			`assign wb_stb_i = 1'b0;`
247			`assign wb_we_i = 1'b0;`
248
249
250	17	antanguay	`initial begin`
251			`tx_count = 0;`
252			`rx_count = 0;`
253			`end`
254
255	2	antanguay	`//---`
256			`// XGMII Loopback`
257	12	antanguay	`// This test is done with loopback on XGMII or using one of the tranceiver examples`
258	2	antanguay
259	12	antanguay	`ifndef GXB
260			`ifndef XIL
261			`assign xgmii_rxc = xgmii_txc;`
262			`assign xgmii_rxd = xgmii_txd;`
263			`endif
264			`endif
265	2	antanguay
266			`//---`
267			`// Clock generation`
268
269			`initial begin`
270			`clk_156m25 = 1'b0;`
271			`clk_xgmii_rx = 1'b0;`
272			`clk_xgmii_tx = 1'b0;`
273			`forever begin`
274			`WaitPS(3200);`
275			`clk_156m25 = ~clk_156m25;`
276			`clk_xgmii_rx = ~clk_xgmii_rx;`
277			`clk_xgmii_tx = ~clk_xgmii_tx;`
278			`end`
279	12	antanguay	`end`
280	2	antanguay
281	12	antanguay	`initial begin`
282			`clk_312m50 = 1'b0;`
283			`forever begin`
284			`WaitPS(1600);`
285			`clk_312m50 = ~clk_312m50;`
286			`end`
287			`end`
288	2	antanguay
289			`//---`
290			`// Reset Generation`
291
292			`initial begin`
293			`reset_156m25_n = 1'b0;`
294			`reset_xgmii_rx_n = 1'b0;`
295			`reset_xgmii_tx_n = 1'b0;`
296			`WaitNS(20);`
297			`reset_156m25_n = 1'b1;`
298			`reset_xgmii_rx_n = 1'b1;`
299			`reset_xgmii_tx_n = 1'b1;`
300			`end`
301
302
303			`//---`
304			`// Init signals`
305
306			`initial begin`
307
308			`for (tx_length = 0; tx_length <= 1000; tx_length = tx_length + 1) begin`
309			`tx_buffer[tx_length] = 0;`
310			`end`
311
312			`pkt_rx_ren = 1'b0;`
313
314			`pkt_tx_data = 64'b0;`
315			`pkt_tx_val = 1'b0;`
316			`pkt_tx_sop = 1'b0;`
317	6	antanguay	`pkt_tx_eop = 1'b0;`
318			`pkt_tx_mod = 3'b0;`
319	2	antanguay
320			`end`
321
322			`task WaitNS;`
323			`input [31:0] delay;`
324			`begin`
325			`#(1000*delay);`
326			`end`
327			`endtask`
328
329			`task WaitPS;`
330			`input [31:0] delay;`
331			`begin`
332			`#(delay);`
333			`end`
334			`endtask`
335
336
337			`//---`
338			`// Task to send a single packet`
339
340			`task TxPacket;`
341			`integer i;`
342			`begin`
343
344			`$display("Transmit packet with length: %d", tx_length);`
345
346			`@(posedge clk_156m25);`
347			`WaitNS(1);`
348			`pkt_tx_val = 1'b1;`
349
350			`for (i = 0; i < tx_length; i = i + 8) begin`
351
352			`pkt_tx_sop = 1'b0;`
353	6	antanguay	`pkt_tx_eop = 1'b0;`
354			`pkt_tx_mod = 2'b0;`
355	2	antanguay
356			`if (i == 0) pkt_tx_sop = 1'b1;`
357
358	6	antanguay	`if (i + 8 >= tx_length) begin`
359			`pkt_tx_eop = 1'b1;`
360			`pkt_tx_mod = tx_length % 8;`
361			`end`
362
363	12	antanguay	pkt_tx_data[`LANE7] = tx_buffer[i];
364			pkt_tx_data[`LANE6] = tx_buffer[i+1];
365			pkt_tx_data[`LANE5] = tx_buffer[i+2];
366			pkt_tx_data[`LANE4] = tx_buffer[i+3];
367			pkt_tx_data[`LANE3] = tx_buffer[i+4];
368			pkt_tx_data[`LANE2] = tx_buffer[i+5];
369			pkt_tx_data[`LANE1] = tx_buffer[i+6];
370			pkt_tx_data[`LANE0] = tx_buffer[i+7];
371	2	antanguay
372			`@(posedge clk_156m25);`
373			`WaitNS(1);`
374
375			`end`
376
377			`pkt_tx_val = 1'b0;`
378	6	antanguay	`pkt_tx_eop = 1'b0;`
379			`pkt_tx_mod = 3'b0;`
380	2	antanguay
381	17	antanguay	`tx_count = tx_count + 1;`
382
383	2	antanguay	`end`
384
385			`endtask`
386
387
388			`//---`
389			`// Task to read a single packet from command file and transmit`
390
391			`task CmdTxPacket;`
392			`input [31:0] file;`
393			`integer count;`
394			`integer data;`
395			`integer i;`
396			`begin`
397
398			`count = $fscanf(file, "%2d", tx_length);`
399
400			`if (count == 1) begin`
401
402			`for (i = 0; i < tx_length; i = i + 1) begin`
403	12	antanguay
404	2	antanguay	`count = $fscanf(file, "%2X", data);`
405			`if (count) begin`
406			`tx_buffer[i] = data;`
407			`end`
408
409			`end`
410
411			`TxPacket();`
412
413			`end`
414			`end`
415
416			`endtask`
417
418
419			`//---`
420			`// Task to read commands from file and stop when complete`
421
422			`task ProcessCmdFile;`
423			`integer file_cmd;`
424			`integer count;`
425			`reg [8*8-1:0] str;`
426			`begin`
427
428			`file_cmd = $fopen("../../tbench/verilog/packets_tx.txt", "r");`
429			`if (!file_cmd) $stop;`
430
431			`while (!$feof(file_cmd)) begin`
432
433			`count = $fscanf(file_cmd, "%s", str);`
434	16	antanguay	`if (count != 1) continue;`
435	2	antanguay
436			`$display("CMD %s", str);`
437
438			`case (str)`
439
440	12	antanguay	`"SEND_PKT":`
441	2	antanguay	`begin`
442			`CmdTxPacket(file_cmd);`
443			`end`
444
445			`endcase`
446
447			`end`
448
449			`$fclose(file_cmd);`
450
451	12	antanguay	`WaitNS(50000);`
452	2	antanguay	`$stop;`
453
454			`end`
455			`endtask`
456
457			`initial begin`
458	12	antanguay	`WaitNS(5000);`
459			`ifdef XIL
460			`WaitNS(200000);`
461			`endif
462	2	antanguay	`ProcessCmdFile();`
463			`end`
464
465
466			`//---`
467			`// Task to read a single packet from receive interface and display`
468
469			`task RxPacket;`
470			`reg done;`
471			`begin`
472
473			`done = 0;`
474
475			`pkt_rx_ren <= 1'b1;`
476			`@(posedge clk_156m25);`
477
478			`while (!done) begin`
479
480			`if (pkt_rx_val) begin`
481
482			`if (pkt_rx_sop) begin`
483			`$display("\n\n------------------------");`
484	17	antanguay	`$display("Received Packet");`
485			`$display("------------------------");`
486	2	antanguay	`end`
487
488			`$display("%x", pkt_rx_data);`
489
490			`if (pkt_rx_eop) begin`
491			`done <= 1;`
492			`pkt_rx_ren <= 1'b0;`
493			`end`
494
495			`if (pkt_rx_eop) begin`
496			`$display("------------------------\n\n");`
497			`end`
498
499			`end`
500

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