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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  File name "tb_xge_mac.v"                                    ////
////                                                              ////
////  This file is part of the "10GE MAC" project                 ////
////  http://www.opencores.org/cores/xge_mac/                     ////
////                                                              ////
////  Author(s):                                                  ////
////      - A. Tanguay (antanguay@opencores.org)                  ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2008 AUTHORS. All rights reserved.             ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
 
 
`include "timescale.v"
`include "defines.v"
 
//`define GXB
//`define XIL
//`define XIL_V10
 
module tb;
 
 
/*AUTOREG*/
 
reg [7:0]     tx_buffer[0:10000];
integer       tx_length;
 
reg           clk_156m25;
reg           clk_312m50;
reg           clk_xgmii_rx;
reg           clk_xgmii_tx;
 
reg           reset_156m25_n;
reg           reset_xgmii_rx_n;
reg           reset_xgmii_tx_n;
 
reg           pkt_rx_ren;
 
reg  [63:0]   pkt_tx_data;
reg           pkt_tx_val;
reg           pkt_tx_sop;
reg           pkt_tx_eop;
reg  [2:0]    pkt_tx_mod;
 
reg           wb_clk_i;
reg  [31:0]   wb_adr_i;
reg           wb_cyc_i;
reg  [31:0]   wb_dat_i;
reg           wb_rst_i;
reg           wb_stb_i;
reg           wb_we_i;
 
integer       tx_count;
integer       rx_count;
 
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire                    pkt_rx_avail;           // From dut of xge_mac.v
wire [63:0]             pkt_rx_data;            // From dut of xge_mac.v
wire                    pkt_rx_eop;             // From dut of xge_mac.v
wire                    pkt_rx_err;             // From dut of xge_mac.v
wire [2:0]              pkt_rx_mod;             // From dut of xge_mac.v
wire                    pkt_rx_sop;             // From dut of xge_mac.v
wire                    pkt_rx_val;             // From dut of xge_mac.v
wire                    pkt_tx_full;            // From dut of xge_mac.v
wire                    wb_ack_o;               // From dut of xge_mac.v
wire [31:0]             wb_dat_o;               // From dut of xge_mac.v
wire                    wb_int_o;               // From dut of xge_mac.v
wire [7:0]              xgmii_txc;              // From dut of xge_mac.v
wire [63:0]             xgmii_txd;              // From dut of xge_mac.v
// End of automatics
 
wire [7:0]              xgmii_rxc;
wire [63:0]             xgmii_rxd;
 
wire [3:0]              tx_dataout;
 
wire                    xaui_tx_l0_n;
wire                    xaui_tx_l0_p;
wire                    xaui_tx_l1_n;
wire                    xaui_tx_l1_p;
wire                    xaui_tx_l2_n;
wire                    xaui_tx_l2_p;
wire                    xaui_tx_l3_n;
wire                    xaui_tx_l3_p;
 
xge_mac dut(/*AUTOINST*/
            // Outputs
            .pkt_rx_avail               (pkt_rx_avail),
            .pkt_rx_data                (pkt_rx_data[63:0]),
            .pkt_rx_eop                 (pkt_rx_eop),
            .pkt_rx_err                 (pkt_rx_err),
            .pkt_rx_mod                 (pkt_rx_mod[2:0]),
            .pkt_rx_sop                 (pkt_rx_sop),
            .pkt_rx_val                 (pkt_rx_val),
            .pkt_tx_full                (pkt_tx_full),
            .wb_ack_o                   (wb_ack_o),
            .wb_dat_o                   (wb_dat_o[31:0]),
            .wb_int_o                   (wb_int_o),
            .xgmii_txc                  (xgmii_txc[7:0]),
            .xgmii_txd                  (xgmii_txd[63:0]),
            // Inputs
            .clk_156m25                 (clk_156m25),
            .clk_xgmii_rx               (clk_xgmii_rx),
            .clk_xgmii_tx               (clk_xgmii_tx),
            .pkt_rx_ren                 (pkt_rx_ren),
            .pkt_tx_data                (pkt_tx_data[63:0]),
            .pkt_tx_eop                 (pkt_tx_eop),
            .pkt_tx_mod                 (pkt_tx_mod[2:0]),
            .pkt_tx_sop                 (pkt_tx_sop),
            .pkt_tx_val                 (pkt_tx_val),
            .reset_156m25_n             (reset_156m25_n),
            .reset_xgmii_rx_n           (reset_xgmii_rx_n),
            .reset_xgmii_tx_n           (reset_xgmii_tx_n),
            .wb_adr_i                   (wb_adr_i[7:0]),
            .wb_clk_i                   (wb_clk_i),
            .wb_cyc_i                   (wb_cyc_i),
            .wb_dat_i                   (wb_dat_i[31:0]),
            .wb_rst_i                   (wb_rst_i),
            .wb_stb_i                   (wb_stb_i),
            .wb_we_i                    (wb_we_i),
            .xgmii_rxc                  (xgmii_rxc[7:0]),
            .xgmii_rxd                  (xgmii_rxd[63:0]));
 
`ifdef GXB
// Example of transceiver instance
gxb gxb(// Outputs
        .rx_ctrldetect                  ({xgmii_rxc[7],
                                          xgmii_rxc[5],
                                          xgmii_rxc[3],
                                          xgmii_rxc[1],
                                          xgmii_rxc[6],
                                          xgmii_rxc[4],
                                          xgmii_rxc[2],
                                          xgmii_rxc[0]}),
        .rx_dataout                     ({xgmii_rxd[63:56],
                                          xgmii_rxd[47:40],
                                          xgmii_rxd[31:24],
                                          xgmii_rxd[15:8],
                                          xgmii_rxd[55:48],
                                          xgmii_rxd[39:32],
                                          xgmii_rxd[23:16],
                                          xgmii_rxd[7:0]}),
        .tx_dataout                     (tx_dataout[3:0]),
        // Inputs
        .pll_inclk                      (clk_156m25),
        .rx_analogreset                 (~reset_156m25_n),
        .rx_cruclk                      ({clk_156m25, clk_156m25, clk_156m25, clk_156m25}),
        .rx_datain                      (tx_dataout[3:0]),
        .rx_digitalreset                (~reset_156m25_n),
        .tx_ctrlenable                  ({xgmii_txc[7],
                                          xgmii_txc[5],
                                          xgmii_txc[3],
                                          xgmii_txc[1],
                                          xgmii_txc[6],
                                          xgmii_txc[4],
                                          xgmii_txc[2],
                                          xgmii_txc[0]}),
        .tx_datain                      ({xgmii_txd[63:56],
                                          xgmii_txd[47:40],
                                          xgmii_txd[31:24],
                                          xgmii_txd[15:8],
                                          xgmii_txd[55:48],
                                          xgmii_txd[39:32],
                                          xgmii_txd[23:16],
                                          xgmii_txd[7:0]}),
        .tx_digitalreset                (~reset_156m25_n));
`endif
 
`ifdef XIL
// Example of transceiver instance
xaui_block xaui(// Outputs
                .txoutclk               (),
                .xgmii_rxd              (xgmii_rxd[63:0]),
                .xgmii_rxc              (xgmii_rxc[7:0]),
                .xaui_tx_l0_p           (xaui_tx_l0_p),
                .xaui_tx_l0_n           (xaui_tx_l0_n),
                .xaui_tx_l1_p           (xaui_tx_l1_p),
                .xaui_tx_l1_n           (xaui_tx_l1_n),
                .xaui_tx_l2_p           (xaui_tx_l2_p),
                .xaui_tx_l2_n           (xaui_tx_l2_n),
                .xaui_tx_l3_p           (xaui_tx_l3_p),
                .xaui_tx_l3_n           (xaui_tx_l3_n),
                .txlock                 (),
                .align_status           (),
                .sync_status            (),
                .mgt_tx_ready           (),
                .drp_o                  (),
                .drp_rdy                (),
                .status_vector          (),
                // Inputs
                .dclk                   (clk_156m25),
                .clk156                 (clk_156m25),
                .clk312                 (clk_312m50),
                .refclk                 (clk_156m25),
                .reset                  (~reset_156m25_n),
                .reset156               (~reset_156m25_n),
                .xgmii_txd              (xgmii_txd[63:0]),
                .xgmii_txc              (xgmii_txc[7:0]),
                .xaui_rx_l0_p           (xaui_tx_l0_p),
                .xaui_rx_l0_n           (xaui_tx_l0_n),
                .xaui_rx_l1_p           (xaui_tx_l1_p),
                .xaui_rx_l1_n           (xaui_tx_l1_n),
                .xaui_rx_l2_p           (xaui_tx_l2_p),
                .xaui_rx_l2_n           (xaui_tx_l2_n),
                .xaui_rx_l3_p           (xaui_tx_l3_p),
                .xaui_rx_l3_n           (xaui_tx_l3_n),
                .signal_detect          (4'b1111),
                .drp_addr               (7'b0),
                .drp_en                 (2'b0),
                .drp_i                  (16'b0),
                .drp_we                 (2'b0),
                .configuration_vector   (7'b0));
 
glbl glbl();
`endif
 
`ifdef XIL_V10
// Example of transceiver instance
xaui_v10_2_block xaui(// Outputs
                .txoutclk               (),
                .xgmii_rxd              (xgmii_rxd[63:0]),
                .xgmii_rxc              (xgmii_rxc[7:0]),
                .xaui_tx_l0_p           (xaui_tx_l0_p),
                .xaui_tx_l0_n           (xaui_tx_l0_n),
                .xaui_tx_l1_p           (xaui_tx_l1_p),
                .xaui_tx_l1_n           (xaui_tx_l1_n),
                .xaui_tx_l2_p           (xaui_tx_l2_p),
                .xaui_tx_l2_n           (xaui_tx_l2_n),
                .xaui_tx_l3_p           (xaui_tx_l3_p),
                .xaui_tx_l3_n           (xaui_tx_l3_n),
                .txlock                 (),
                .align_status           (),
                .sync_status            (),
                .mgt_tx_ready           (),
                .drp_o                  (),
                .drp_rdy                (),
                .status_vector          (),
                // Inputs
                .dclk                   (clk_156m25),
                .clk156                 (clk_156m25),
                .refclk                 (clk_156m25),
                .reset                  (~reset_156m25_n),
                .reset156               (~reset_156m25_n),
                .xgmii_txd              (xgmii_txd[63:0]),
                .xgmii_txc              (xgmii_txc[7:0]),
                .xaui_rx_l0_p           (xaui_tx_l0_p),
                .xaui_rx_l0_n           (xaui_tx_l0_n),
                .xaui_rx_l1_p           (xaui_tx_l1_p),
                .xaui_rx_l1_n           (xaui_tx_l1_n),
                .xaui_rx_l2_p           (xaui_tx_l2_p),
                .xaui_rx_l2_n           (xaui_tx_l2_n),
                .xaui_rx_l3_p           (xaui_tx_l3_p),
                .xaui_rx_l3_n           (xaui_tx_l3_n),
                .signal_detect          (4'b1111),
                .drp_addr               (9'b0),
                .drp_en                 (4'b0),
                .drp_i                  (16'b0),
                .drp_we                 (4'b0),
                .configuration_vector   (7'b0));
 
glbl glbl();
`endif
 
//---
// Wishbone
 
initial begin
    wb_adr_i <= 8'b0;
    wb_cyc_i <= 1'b0;
    wb_dat_i <= 32'b0;
    wb_rst_i <= 1'b1;
    wb_stb_i <= 1'b0;
    wb_we_i <= 1'b0;
    @(posedge wb_clk_i);
    wb_rst_i <= 1'b0;
end
 
initial begin
    tx_count = 0;
    rx_count = 0;
end
 
//---
// XGMII Loopback
// This test is done with loopback on XGMII or using one of the tranceiver examples
 
`ifndef GXB
  `ifndef XIL
    `ifndef XIL_V10
      assign xgmii_rxc = xgmii_txc;
      assign xgmii_rxd = xgmii_txd;
    `endif
  `endif
`endif
 
//---
// Clock generation
 
initial begin
    clk_156m25 <= 1'b0;
    clk_xgmii_rx <= 1'b0;
    clk_xgmii_tx <= 1'b0;
    forever begin
        WaitPS(3200);
        clk_156m25 <= ~clk_156m25;
        clk_xgmii_rx <= ~clk_xgmii_rx;
        clk_xgmii_tx <= ~clk_xgmii_tx;
    end
end
 
initial begin
    wb_clk_i <= 1'b0;
    forever begin
        WaitPS(20000);
        wb_clk_i <= ~wb_clk_i;
    end
end
 
initial begin
    clk_312m50 = 1'b0;
    forever begin
        WaitPS(1600);
        clk_312m50 = ~clk_312m50;
    end
end
 
//---
// Reset Generation
 
initial begin
    reset_156m25_n = 1'b0;
    reset_xgmii_rx_n = 1'b0;
    reset_xgmii_tx_n = 1'b0;
    WaitNS(20);
    reset_156m25_n = 1'b1;
    reset_xgmii_rx_n = 1'b1;
    reset_xgmii_tx_n = 1'b1;
end
 
 
//---
// Init signals
 
initial begin
 
    for (tx_length = 0; tx_length <= 1000; tx_length = tx_length + 1) begin
        tx_buffer[tx_length] = 0;
    end
 
    pkt_rx_ren = 1'b0;
 
    pkt_tx_data = 64'b0;
    pkt_tx_val = 1'b0;
    pkt_tx_sop = 1'b0;
    pkt_tx_eop = 1'b0;
    pkt_tx_mod = 3'b0;
 
end
 
task WaitNS;
  input [31:0] delay;
    begin
        #(1000*delay);
    end
endtask
 
task WaitPS;
  input [31:0] delay;
    begin
        #(delay);
    end
endtask
 
//---
// Task to read register
 
task CpuRead;
  input [31:0] addr;
  output [31:0] data;
    begin
        @(posedge wb_clk_i);
        wb_adr_i <= addr;
        wb_cyc_i <= 1'b1;
        wb_stb_i <= 1'b1;
        @(posedge wb_clk_i);
        wb_stb_i <= 1'b0;
        @(posedge wb_clk_i);
        wb_cyc_i <= 1'b0;
        data <= wb_dat_o;
        @(posedge wb_clk_i);
    end
endtask
 
//---
// Task to send a single packet
 
task TxPacket;
  integer        i;
    begin
 
        $display("Transmit packet with length: %d", tx_length);
 
        @(posedge clk_156m25);
        WaitNS(1);
        pkt_tx_val = 1'b1;
 
        for (i = 0; i < tx_length; i = i + 8) begin
 
            pkt_tx_sop = 1'b0;
            pkt_tx_eop = 1'b0;
            pkt_tx_mod = 2'b0;
 
            if (i == 0) pkt_tx_sop = 1'b1;
 
            if (i + 8 >= tx_length) begin
                pkt_tx_eop = 1'b1;
                pkt_tx_mod = tx_length % 8;
            end
 
            pkt_tx_data[`LANE7] = tx_buffer[i];
            pkt_tx_data[`LANE6] = tx_buffer[i+1];
            pkt_tx_data[`LANE5] = tx_buffer[i+2];
            pkt_tx_data[`LANE4] = tx_buffer[i+3];
            pkt_tx_data[`LANE3] = tx_buffer[i+4];
            pkt_tx_data[`LANE2] = tx_buffer[i+5];
            pkt_tx_data[`LANE1] = tx_buffer[i+6];
            pkt_tx_data[`LANE0] = tx_buffer[i+7];
 
            @(posedge clk_156m25);
            WaitNS(1);
 
        end
 
        pkt_tx_val = 1'b0;
        pkt_tx_eop = 1'b0;
        pkt_tx_mod = 3'b0;
 
        tx_count = tx_count + 1;
 
    end
 
endtask
 
 
//---
// Task to read a single packet from command file and transmit
 
task CmdTxPacket;
  input [31:0] file;
  integer count;
  integer data;
  integer i;
    begin
 
        count = $fscanf(file, "%2d", tx_length);
 
        if (count == 1) begin
 
            for (i = 0; i < tx_length; i = i + 1) begin
 
                count = $fscanf(file, "%2X", data);
                if (count) begin
                    tx_buffer[i] = data;
                end
 
            end
 
            TxPacket();
 
        end
    end
 
endtask
 
 
//---
// Task to read commands from file and stop when complete
 
task ProcessCmdFile;
  integer    file_cmd;
  integer  count;
  reg [8*8-1:0] str;
  reg [31:0] data;
    begin
 
        file_cmd = $fopen("../../tbench/verilog/packets_tx.txt", "r");
        if (!file_cmd) $stop;
 
        while (!$feof(file_cmd)) begin
 
            count = $fscanf(file_cmd, "%s", str);
            if (count != 1) continue;
 
            $display("CMD %s", str);
 
            case (str)
 
              "SEND_PKT":
                begin
                    CmdTxPacket(file_cmd);
                end
 
            endcase
 
        end
 
        $fclose(file_cmd);
 
        WaitNS(50000);
 
        CpuRead(`CPUREG_STATSTXPKTS, data);
        CpuRead(`CPUREG_STATSRXPKTS, data);
 
        CpuRead(`CPUREG_STATSTXOCTETS, data);
        CpuRead(`CPUREG_STATSRXOCTETS, data);
 
        $stop;
 
    end
endtask
 
initial begin
    WaitNS(5000);
`ifdef XIL
    WaitNS(200000);
`endif
    ProcessCmdFile();
end
 
 
//---
// Task to read a single packet from receive interface and display
 
task RxPacket;
  reg done;
    begin
 
        done = 0;
 
        pkt_rx_ren <= 1'b1;
        @(posedge clk_156m25);
 
        while (!done) begin
 
            if (pkt_rx_val) begin
 
                if (pkt_rx_sop) begin
                    $display("\n\n------------------------");
                    $display("Received Packet");
                    $display("------------------------");
                end
 
                $display("%x", pkt_rx_data);
 
                if (pkt_rx_eop) begin
                    done <= 1;
                    pkt_rx_ren <= 1'b0;
                end
 
                if (pkt_rx_eop) begin
                    $display("------------------------\n\n");
                end
 
            end
 
            @(posedge clk_156m25);
 
        end
 
        rx_count = rx_count + 1;
 
    end
endtask
 
initial begin
 
    forever begin
 
        if (pkt_rx_avail) begin
 
            RxPacket();
 
            if (rx_count == tx_count) begin
                $display("All packets received. Sumulation done!!!\n");
            end
 
        end
 
        @(posedge clk_156m25);
 
    end
 
end
 
endmodule

Line No.	Rev	Author	Line
1	2	antanguay	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// File name "tb_xge_mac.v" ////`
4			`//// ////`
5			`//// This file is part of the "10GE MAC" project ////`
6			`//// http://www.opencores.org/cores/xge_mac/ ////`
7			`//// ////`
8			`//// Author(s): ////`
9			`//// - A. Tanguay (antanguay@opencores.org) ////`
10			`//// ////`
11			`//////////////////////////////////////////////////////////////////////`
12			`//// ////`
13			`//// Copyright (C) 2008 AUTHORS. All rights reserved. ////`
14			`//// ////`
15			`//// This source file may be used and distributed without ////`
16			`//// restriction provided that this copyright statement is not ////`
17			`//// removed from the file and that any derivative work contains ////`
18			`//// the original copyright notice and the associated disclaimer. ////`
19			`//// ////`
20			`//// This source file is free software; you can redistribute it ////`
21			`//// and/or modify it under the terms of the GNU Lesser General ////`
22			`//// Public License as published by the Free Software Foundation; ////`
23			`//// either version 2.1 of the License, or (at your option) any ////`
24			`//// later version. ////`
25			`//// ////`
26			`//// This source is distributed in the hope that it will be ////`
27			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
28			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
29			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
30			`//// details. ////`
31			`//// ////`
32			`//// You should have received a copy of the GNU Lesser General ////`
33			`//// Public License along with this source; if not, download it ////`
34			`//// from http://www.opencores.org/lgpl.shtml ////`
35			`//// ////`
36			`//////////////////////////////////////////////////////////////////////`
37
38
39			`include "timescale.v"
40			`include "defines.v"
41
42	14	antanguay	//`define GXB
43			//`define XIL
44	21	antanguay	//`define XIL_V10
45	14	antanguay
46	2	antanguay	`module tb;`
47
48
49			`/AUTOREG/`
50
51			`reg [7:0] tx_buffer[0:10000];`
52			`integer tx_length;`
53
54			`reg clk_156m25;`
55	12	antanguay	`reg clk_312m50;`
56	2	antanguay	`reg clk_xgmii_rx;`
57			`reg clk_xgmii_tx;`
58
59			`reg reset_156m25_n;`
60			`reg reset_xgmii_rx_n;`
61			`reg reset_xgmii_tx_n;`
62
63			`reg pkt_rx_ren;`
64
65			`reg [63:0] pkt_tx_data;`
66			`reg pkt_tx_val;`
67			`reg pkt_tx_sop;`
68	6	antanguay	`reg pkt_tx_eop;`
69			`reg [2:0] pkt_tx_mod;`
70	2	antanguay
71	23	antanguay	`reg wb_clk_i;`
72			`reg [31:0] wb_adr_i;`
73			`reg wb_cyc_i;`
74			`reg [31:0] wb_dat_i;`
75			`reg wb_rst_i;`
76			`reg wb_stb_i;`
77			`reg wb_we_i;`
78
79	17	antanguay	`integer tx_count;`
80			`integer rx_count;`
81
82	2	antanguay	`/AUTOWIRE/`
83			`// Beginning of automatic wires (for undeclared instantiated-module outputs)`
84			`wire pkt_rx_avail; // From dut of xge_mac.v`
85			`wire [63:0] pkt_rx_data; // From dut of xge_mac.v`
86	6	antanguay	`wire pkt_rx_eop; // From dut of xge_mac.v`
87	2	antanguay	`wire pkt_rx_err; // From dut of xge_mac.v`
88	6	antanguay	`wire [2:0] pkt_rx_mod; // From dut of xge_mac.v`
89	2	antanguay	`wire pkt_rx_sop; // From dut of xge_mac.v`
90			`wire pkt_rx_val; // From dut of xge_mac.v`
91			`wire pkt_tx_full; // From dut of xge_mac.v`
92			`wire wb_ack_o; // From dut of xge_mac.v`
93			`wire [31:0] wb_dat_o; // From dut of xge_mac.v`
94			`wire wb_int_o; // From dut of xge_mac.v`
95			`wire [7:0] xgmii_txc; // From dut of xge_mac.v`
96			`wire [63:0] xgmii_txd; // From dut of xge_mac.v`
97			`// End of automatics`
98
99			`wire [7:0] xgmii_rxc;`
100			`wire [63:0] xgmii_rxd;`
101
102	12	antanguay	`wire [3:0] tx_dataout;`
103	2	antanguay
104	12	antanguay	`wire xaui_tx_l0_n;`
105			`wire xaui_tx_l0_p;`
106			`wire xaui_tx_l1_n;`
107			`wire xaui_tx_l1_p;`
108			`wire xaui_tx_l2_n;`
109			`wire xaui_tx_l2_p;`
110			`wire xaui_tx_l3_n;`
111			`wire xaui_tx_l3_p;`
112
113	2	antanguay	`xge_mac dut(/AUTOINST/`
114			`// Outputs`
115			`.pkt_rx_avail (pkt_rx_avail),`
116			`.pkt_rx_data (pkt_rx_data[63:0]),`
117	6	antanguay	`.pkt_rx_eop (pkt_rx_eop),`
118	2	antanguay	`.pkt_rx_err (pkt_rx_err),`
119	6	antanguay	`.pkt_rx_mod (pkt_rx_mod[2:0]),`
120	2	antanguay	`.pkt_rx_sop (pkt_rx_sop),`
121			`.pkt_rx_val (pkt_rx_val),`
122			`.pkt_tx_full (pkt_tx_full),`
123			`.wb_ack_o (wb_ack_o),`
124			`.wb_dat_o (wb_dat_o[31:0]),`
125			`.wb_int_o (wb_int_o),`
126			`.xgmii_txc (xgmii_txc[7:0]),`
127			`.xgmii_txd (xgmii_txd[63:0]),`
128			`// Inputs`
129			`.clk_156m25 (clk_156m25),`
130			`.clk_xgmii_rx (clk_xgmii_rx),`
131			`.clk_xgmii_tx (clk_xgmii_tx),`
132			`.pkt_rx_ren (pkt_rx_ren),`
133			`.pkt_tx_data (pkt_tx_data[63:0]),`
134	6	antanguay	`.pkt_tx_eop (pkt_tx_eop),`
135			`.pkt_tx_mod (pkt_tx_mod[2:0]),`
136	2	antanguay	`.pkt_tx_sop (pkt_tx_sop),`
137			`.pkt_tx_val (pkt_tx_val),`
138			`.reset_156m25_n (reset_156m25_n),`
139			`.reset_xgmii_rx_n (reset_xgmii_rx_n),`
140			`.reset_xgmii_tx_n (reset_xgmii_tx_n),`
141			`.wb_adr_i (wb_adr_i[7:0]),`
142			`.wb_clk_i (wb_clk_i),`
143			`.wb_cyc_i (wb_cyc_i),`
144			`.wb_dat_i (wb_dat_i[31:0]),`
145			`.wb_rst_i (wb_rst_i),`
146			`.wb_stb_i (wb_stb_i),`
147			`.wb_we_i (wb_we_i),`
148			`.xgmii_rxc (xgmii_rxc[7:0]),`
149			`.xgmii_rxd (xgmii_rxd[63:0]));`
150
151	12	antanguay	`ifdef GXB
152			`// Example of transceiver instance`
153			`gxb gxb(// Outputs`
154			`.rx_ctrldetect ({xgmii_rxc[7],`
155			`xgmii_rxc[5],`
156			`xgmii_rxc[3],`
157			`xgmii_rxc[1],`
158			`xgmii_rxc[6],`
159			`xgmii_rxc[4],`
160			`xgmii_rxc[2],`
161			`xgmii_rxc[0]}),`
162			`.rx_dataout ({xgmii_rxd[63:56],`
163			`xgmii_rxd[47:40],`
164			`xgmii_rxd[31:24],`
165			`xgmii_rxd[15:8],`
166			`xgmii_rxd[55:48],`
167			`xgmii_rxd[39:32],`
168			`xgmii_rxd[23:16],`
169			`xgmii_rxd[7:0]}),`
170			`.tx_dataout (tx_dataout[3:0]),`
171			`// Inputs`
172			`.pll_inclk (clk_156m25),`
173			`.rx_analogreset (~reset_156m25_n),`
174			`.rx_cruclk ({clk_156m25, clk_156m25, clk_156m25, clk_156m25}),`
175			`.rx_datain (tx_dataout[3:0]),`
176			`.rx_digitalreset (~reset_156m25_n),`
177			`.tx_ctrlenable ({xgmii_txc[7],`
178			`xgmii_txc[5],`
179			`xgmii_txc[3],`
180			`xgmii_txc[1],`
181			`xgmii_txc[6],`
182			`xgmii_txc[4],`
183			`xgmii_txc[2],`
184			`xgmii_txc[0]}),`
185			`.tx_datain ({xgmii_txd[63:56],`
186			`xgmii_txd[47:40],`
187			`xgmii_txd[31:24],`
188			`xgmii_txd[15:8],`
189			`xgmii_txd[55:48],`
190			`xgmii_txd[39:32],`
191			`xgmii_txd[23:16],`
192			`xgmii_txd[7:0]}),`
193			`.tx_digitalreset (~reset_156m25_n));`
194			`endif
195	2	antanguay
196	12	antanguay	`ifdef XIL
197			`// Example of transceiver instance`
198			`xaui_block xaui(// Outputs`
199			`.txoutclk (),`
200			`.xgmii_rxd (xgmii_rxd[63:0]),`
201			`.xgmii_rxc (xgmii_rxc[7:0]),`
202			`.xaui_tx_l0_p (xaui_tx_l0_p),`
203			`.xaui_tx_l0_n (xaui_tx_l0_n),`
204			`.xaui_tx_l1_p (xaui_tx_l1_p),`
205			`.xaui_tx_l1_n (xaui_tx_l1_n),`
206			`.xaui_tx_l2_p (xaui_tx_l2_p),`
207			`.xaui_tx_l2_n (xaui_tx_l2_n),`
208			`.xaui_tx_l3_p (xaui_tx_l3_p),`
209			`.xaui_tx_l3_n (xaui_tx_l3_n),`
210			`.txlock (),`
211			`.align_status (),`
212			`.sync_status (),`
213			`.mgt_tx_ready (),`
214			`.drp_o (),`
215			`.drp_rdy (),`
216			`.status_vector (),`
217			`// Inputs`
218			`.dclk (clk_156m25),`
219			`.clk156 (clk_156m25),`
220			`.clk312 (clk_312m50),`
221			`.refclk (clk_156m25),`
222			`.reset (~reset_156m25_n),`
223			`.reset156 (~reset_156m25_n),`
224			`.xgmii_txd (xgmii_txd[63:0]),`
225			`.xgmii_txc (xgmii_txc[7:0]),`
226			`.xaui_rx_l0_p (xaui_tx_l0_p),`
227			`.xaui_rx_l0_n (xaui_tx_l0_n),`
228			`.xaui_rx_l1_p (xaui_tx_l1_p),`
229			`.xaui_rx_l1_n (xaui_tx_l1_n),`
230			`.xaui_rx_l2_p (xaui_tx_l2_p),`
231			`.xaui_rx_l2_n (xaui_tx_l2_n),`
232			`.xaui_rx_l3_p (xaui_tx_l3_p),`
233			`.xaui_rx_l3_n (xaui_tx_l3_n),`
234			`.signal_detect (4'b1111),`
235			`.drp_addr (7'b0),`
236			`.drp_en (2'b0),`
237			`.drp_i (16'b0),`
238			`.drp_we (2'b0),`
239			`.configuration_vector (7'b0));`
240
241			`glbl glbl();`
242			`endif
243
244	21	antanguay	`ifdef XIL_V10
245			`// Example of transceiver instance`
246			`xaui_v10_2_block xaui(// Outputs`
247			`.txoutclk (),`
248			`.xgmii_rxd (xgmii_rxd[63:0]),`
249			`.xgmii_rxc (xgmii_rxc[7:0]),`
250			`.xaui_tx_l0_p (xaui_tx_l0_p),`
251			`.xaui_tx_l0_n (xaui_tx_l0_n),`
252			`.xaui_tx_l1_p (xaui_tx_l1_p),`
253			`.xaui_tx_l1_n (xaui_tx_l1_n),`
254			`.xaui_tx_l2_p (xaui_tx_l2_p),`
255			`.xaui_tx_l2_n (xaui_tx_l2_n),`
256			`.xaui_tx_l3_p (xaui_tx_l3_p),`
257			`.xaui_tx_l3_n (xaui_tx_l3_n),`
258			`.txlock (),`
259			`.align_status (),`
260			`.sync_status (),`
261			`.mgt_tx_ready (),`
262			`.drp_o (),`
263			`.drp_rdy (),`
264			`.status_vector (),`
265			`// Inputs`
266			`.dclk (clk_156m25),`
267			`.clk156 (clk_156m25),`
268			`.refclk (clk_156m25),`
269			`.reset (~reset_156m25_n),`
270			`.reset156 (~reset_156m25_n),`
271			`.xgmii_txd (xgmii_txd[63:0]),`
272			`.xgmii_txc (xgmii_txc[7:0]),`
273			`.xaui_rx_l0_p (xaui_tx_l0_p),`
274			`.xaui_rx_l0_n (xaui_tx_l0_n),`
275			`.xaui_rx_l1_p (xaui_tx_l1_p),`
276			`.xaui_rx_l1_n (xaui_tx_l1_n),`
277			`.xaui_rx_l2_p (xaui_tx_l2_p),`
278			`.xaui_rx_l2_n (xaui_tx_l2_n),`
279			`.xaui_rx_l3_p (xaui_tx_l3_p),`
280			`.xaui_rx_l3_n (xaui_tx_l3_n),`
281			`.signal_detect (4'b1111),`
282			`.drp_addr (9'b0),`
283			`.drp_en (4'b0),`
284			`.drp_i (16'b0),`
285			`.drp_we (4'b0),`
286			`.configuration_vector (7'b0));`
287
288			`glbl glbl();`
289			`endif
290
291	2	antanguay	`//---`
292	23	antanguay	`// Wishbone`
293	2	antanguay
294	23	antanguay	`initial begin`
295			`wb_adr_i <= 8'b0;`
296			`wb_cyc_i <= 1'b0;`
297			`wb_dat_i <= 32'b0;`
298			`wb_rst_i <= 1'b1;`
299			`wb_stb_i <= 1'b0;`
300			`wb_we_i <= 1'b0;`
301			`@(posedge wb_clk_i);`
302			`wb_rst_i <= 1'b0;`
303			`end`
304	2	antanguay
305	17	antanguay	`initial begin`
306			`tx_count = 0;`
307			`rx_count = 0;`
308			`end`
309
310	2	antanguay	`//---`
311			`// XGMII Loopback`
312	12	antanguay	`// This test is done with loopback on XGMII or using one of the tranceiver examples`
313	2	antanguay
314	12	antanguay	`ifndef GXB
315			`ifndef XIL
316	21	antanguay	`ifndef XIL_V10
317			`assign xgmii_rxc = xgmii_txc;`
318			`assign xgmii_rxd = xgmii_txd;`
319			`endif
320	12	antanguay	`endif
321			`endif
322	2	antanguay
323			`//---`
324			`// Clock generation`
325
326			`initial begin`
327	23	antanguay	`clk_156m25 <= 1'b0;`
328			`clk_xgmii_rx <= 1'b0;`
329			`clk_xgmii_tx <= 1'b0;`
330	2	antanguay	`forever begin`
331			`WaitPS(3200);`
332	23	antanguay	`clk_156m25 <= ~clk_156m25;`
333			`clk_xgmii_rx <= ~clk_xgmii_rx;`
334			`clk_xgmii_tx <= ~clk_xgmii_tx;`
335	2	antanguay	`end`
336	12	antanguay	`end`
337	2	antanguay
338	12	antanguay	`initial begin`
339	23	antanguay	`wb_clk_i <= 1'b0;`
340			`forever begin`
341			`WaitPS(20000);`
342			`wb_clk_i <= ~wb_clk_i;`
343			`end`
344			`end`
345
346			`initial begin`
347	12	antanguay	`clk_312m50 = 1'b0;`
348			`forever begin`
349			`WaitPS(1600);`
350			`clk_312m50 = ~clk_312m50;`
351			`end`
352			`end`
353	2	antanguay
354			`//---`
355			`// Reset Generation`
356
357			`initial begin`
358			`reset_156m25_n = 1'b0;`
359			`reset_xgmii_rx_n = 1'b0;`
360			`reset_xgmii_tx_n = 1'b0;`
361			`WaitNS(20);`
362			`reset_156m25_n = 1'b1;`
363			`reset_xgmii_rx_n = 1'b1;`
364			`reset_xgmii_tx_n = 1'b1;`
365			`end`
366
367
368			`//---`
369			`// Init signals`
370
371			`initial begin`
372
373			`for (tx_length = 0; tx_length <= 1000; tx_length = tx_length + 1) begin`
374			`tx_buffer[tx_length] = 0;`
375			`end`
376
377			`pkt_rx_ren = 1'b0;`
378
379			`pkt_tx_data = 64'b0;`
380			`pkt_tx_val = 1'b0;`
381			`pkt_tx_sop = 1'b0;`
382	6	antanguay	`pkt_tx_eop = 1'b0;`
383			`pkt_tx_mod = 3'b0;`
384	2	antanguay
385			`end`
386
387			`task WaitNS;`
388			`input [31:0] delay;`
389			`begin`
390			`#(1000*delay);`
391			`end`
392			`endtask`
393
394			`task WaitPS;`
395			`input [31:0] delay;`
396			`begin`
397			`#(delay);`
398			`end`
399			`endtask`
400
401	23	antanguay	`//---`
402			`// Task to read register`
403	2	antanguay
404	23	antanguay	`task CpuRead;`
405			`input [31:0] addr;`
406			`output [31:0] data;`
407			`begin`
408			`@(posedge wb_clk_i);`
409			`wb_adr_i <= addr;`
410			`wb_cyc_i <= 1'b1;`
411			`wb_stb_i <= 1'b1;`
412			`@(posedge wb_clk_i);`
413			`wb_stb_i <= 1'b0;`
414			`@(posedge wb_clk_i);`
415			`wb_cyc_i <= 1'b0;`
416			`data <= wb_dat_o;`
417			`@(posedge wb_clk_i);`
418			`end`
419			`endtask`
420
421	2	antanguay	`//---`
422			`// Task to send a single packet`
423
424			`task TxPacket;`
425			`integer i;`
426			`begin`
427
428			`$display("Transmit packet with length: %d", tx_length);`
429
430			`@(posedge clk_156m25);`
431			`WaitNS(1);`
432			`pkt_tx_val = 1'b1;`
433
434			`for (i = 0; i < tx_length; i = i + 8) begin`
435
436			`pkt_tx_sop = 1'b0;`
437	6	antanguay	`pkt_tx_eop = 1'b0;`
438			`pkt_tx_mod = 2'b0;`
439	2	antanguay
440			`if (i == 0) pkt_tx_sop = 1'b1;`
441
442	6	antanguay	`if (i + 8 >= tx_length) begin`
443			`pkt_tx_eop = 1'b1;`
444			`pkt_tx_mod = tx_length % 8;`
445			`end`
446
447	12	antanguay	pkt_tx_data[`LANE7] = tx_buffer[i];
448			pkt_tx_data[`LANE6] = tx_buffer[i+1];
449			pkt_tx_data[`LANE5] = tx_buffer[i+2];
450			pkt_tx_data[`LANE4] = tx_buffer[i+3];
451			pkt_tx_data[`LANE3] = tx_buffer[i+4];
452			pkt_tx_data[`LANE2] = tx_buffer[i+5];
453			pkt_tx_data[`LANE1] = tx_buffer[i+6];
454			pkt_tx_data[`LANE0] = tx_buffer[i+7];
455	2	antanguay
456			`@(posedge clk_156m25);`
457			`WaitNS(1);`
458
459			`end`
460
461			`pkt_tx_val = 1'b0;`
462	6	antanguay	`pkt_tx_eop = 1'b0;`
463			`pkt_tx_mod = 3'b0;`
464	2	antanguay
465	17	antanguay	`tx_count = tx_count + 1;`
466
467	2	antanguay	`end`
468
469			`endtask`
470
471
472			`//---`
473			`// Task to read a single packet from command file and transmit`
474
475			`task CmdTxPacket;`
476			`input [31:0] file;`
477			`integer count;`
478			`integer data;`
479			`integer i;`
480			`begin`
481
482			`count = $fscanf(file, "%2d", tx_length);`
483
484			`if (count == 1) begin`
485
486			`for (i = 0; i < tx_length; i = i + 1) begin`
487	12	antanguay
488	2	antanguay	`count = $fscanf(file, "%2X", data);`
489			`if (count) begin`
490			`tx_buffer[i] = data;`
491			`end`
492
493			`end`
494
495			`TxPacket();`
496
497			`end`
498			`end`
499
500			`endtask`

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