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[/] [xilinx_virtex_fp_library/] [trunk/] [DualPathFPAdderMappedConversions/] [leading_zeros.v] - Blame information for rev 19

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`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:     UPT
// Engineer:    Constantina-Elena Gavriliu
// 
// Create Date:    18:50:09 10/17/2013 
// Design Name: 
// Module Name:    leading_zeros 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies:        d_ff.v
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//////////////////////////////////////////////////////////////////////////////////
module leading_zeros #( parameter SIZE_INT = 24,        //mantissa bits
                                                                parameter SIZE_COUNTER  = 5,    //log2(size_mantissa) + 1 = 5)
                                                                parameter PIPELINE = 2)
                                                        (a, ovf, lz);
 
        input [SIZE_INT-1:0]    a;
        input                   ovf;
        output [SIZE_COUNTER-1:0] lz;
 
 
        parameter       nr_levels = SIZE_COUNTER - 1;
        parameter       max_pow_2 = 2 ** SIZE_COUNTER;
        parameter       size_lz = SIZE_COUNTER;
 
        wire [max_pow_2-1:0] a_complete;
        wire [max_pow_2-1:0] v_d[nr_levels-1:0];
        wire [max_pow_2-1:0] v_q[nr_levels-1:0];
        wire [max_pow_2-1:0] p_d[nr_levels-1:0];
        wire [max_pow_2-1:0] p_q[nr_levels-1:0];
        wire [size_lz-1:0]   lzc;
 
        assign a_complete[max_pow_2 - 1 : max_pow_2 - 1 - SIZE_INT + 1] = a;
        generate
                if (max_pow_2 != SIZE_INT)
                begin : gen_if
                        assign a_complete[max_pow_2 - 1 - SIZE_INT : 0] = 0;
                end
        endgenerate
 
        generate
                begin : level_0
                        genvar i;
                        for (i = max_pow_2/4 - 1; i >= 0; i = i - 1)
                        begin : level_0
                                assign v_d[0][i] = (a_complete[4 * i + 3 : 4 * i] == 4'b0000) ? 1'b0 : 1'b1;
                                assign p_d[0][2*i+1:2*i] = (a_complete[4 * i + 3] == 1'b1) ? 2'b00 :
                                                                (a_complete[4 * i + 2] == 1'b1) ? 2'b01 :
                                                                (a_complete[4 * i + 1] == 1'b1) ? 2'b10 : 2'b11;
                        end
                end
        endgenerate
 
        generate
                begin : level_generation_begin
                        genvar i;
                        for (i = 1; i <= nr_levels - 1; i = i + 1)
                        begin : level_generation
                                        genvar j;
                                        for (j = 0; j <= max_pow_2/(2 ** (i + 2)) - 1; j = j + 1)
                                        begin : v_levels
                                                assign v_d[i][j] = v_q[i - 1][2*j+1] | v_q[i - 1][2*j];
                                        end
 
                                        for (j = 0; j <= max_pow_2/(2 ** (i + 2)) - 1; j = j + 1)
                                        begin : p_levels
                                                assign p_d[i][(i+2)*j+i+1] = (~(v_q[i - 1][2*j+1]));
                                                assign p_d[i][(i+2)*j+i : (i+2)*j] = (v_q[i - 1][2*j+1] == 1'b1) ? p_q[i - 1][j*(2*i+2)+2*i+1 : j*(2*i+2) + i + 1] : p_q[i - 1][j*(2*i+2)+i : j*(2*i+2)];
                                        end
                        end
                end
        endgenerate
 
        generate
                if (PIPELINE != 0)
                begin : pipeline_stages
                                genvar i;
                                for (i = 0; i <= nr_levels - 2; i = i + 1)
                                begin : INSERTION
                                        if ((i + 1) % nr_levels/(PIPELINE + 1) == 0)
                                        begin : INS
                                                d_ff #(max_pow_2) P_Di(.clk(clk), .rst(rst), .d(p_d[i]), .q(p_q[i]));
                                                d_ff #(max_pow_2) V_Di(.clk(clk), .rst(rst), .d(v_d[i]), .q(v_q[i]));
                                        end
 
                                        if ((i + 1) % nr_levels/(PIPELINE + 1) != 0)
                                        begin : NO_INS
                                                assign p_q[i] = p_d[i];
                                                assign v_q[i] = v_d[i];
                                        end
                                end
                        assign p_q[nr_levels - 1] = p_d[nr_levels - 1];
                        assign v_q[nr_levels - 1] = v_d[nr_levels - 1];
                end
        endgenerate
 
        generate
                if (PIPELINE == 0)
                begin : no_pipeline
                                genvar i;
                                for (i = 0; i <= nr_levels - 1; i = i + 1)
                                begin : NO_INSERTION
                                        assign p_q[i] = p_d[i];
                                        assign v_q[i] = v_d[i];
                                end
                end
        endgenerate
 
        assign lzc[size_lz - 1:0] = p_q[nr_levels - 1][size_lz - 1:0];
 
        generate
                begin : lz_ovf_begin
                        genvar i;
                        for (i = 0; i <= size_lz - 1; i = i + 1)
                        begin : lz_ovf
                                assign lz[i] = lzc[i] & ((~ovf));
                        end
                end
        endgenerate
 
endmodule

Line No.	Rev	Author	Line
1	11	constantin	`timescale 1ns / 1ps
2			`//////////////////////////////////////////////////////////////////////////////////`
3	19	constantin	`// Company: UPT`
4			`// Engineer: Constantina-Elena Gavriliu`
5	11	constantin	`//`
6			`// Create Date: 18:50:09 10/17/2013`
7			`// Design Name:`
8			`// Module Name: leading_zeros`
9			`// Project Name:`
10			`// Target Devices:`
11			`// Tool versions:`
12			`// Description:`
13			`//`
14	19	constantin	`// Dependencies: d_ff.v`
15	11	constantin	`//`
16			`// Revision:`
17			`// Revision 0.01 - File Created`
18			`// Additional Comments:`
19			`//`
20			`//////////////////////////////////////////////////////////////////////////////////`
21			`module leading_zeros #( parameter SIZE_INT = 24, //mantissa bits`
22			`parameter SIZE_COUNTER = 5, //log2(size_mantissa) + 1 = 5)`
23			`parameter PIPELINE = 2)`
24			`(a, ovf, lz);`
25
26			`input [SIZE_INT-1:0] a;`
27			`input ovf;`
28			`output [SIZE_COUNTER-1:0] lz;`
29
30
31			`parameter nr_levels = SIZE_COUNTER - 1;`
32			`parameter max_pow_2 = 2 ** SIZE_COUNTER;`
33			`parameter size_lz = SIZE_COUNTER;`
34
35			`wire [max_pow_2-1:0] a_complete;`
36			`wire [max_pow_2-1:0] v_d[nr_levels-1:0];`
37			`wire [max_pow_2-1:0] v_q[nr_levels-1:0];`
38			`wire [max_pow_2-1:0] p_d[nr_levels-1:0];`
39			`wire [max_pow_2-1:0] p_q[nr_levels-1:0];`
40			`wire [size_lz-1:0] lzc;`
41
42			`assign a_complete[max_pow_2 - 1 : max_pow_2 - 1 - SIZE_INT + 1] = a;`
43			`generate`
44			`if (max_pow_2 != SIZE_INT)`
45			`begin : gen_if`
46			`assign a_complete[max_pow_2 - 1 - SIZE_INT : 0] = 0;`
47			`end`
48			`endgenerate`
49
50			`generate`
51			`begin : level_0`
52			`genvar i;`
53			`for (i = max_pow_2/4 - 1; i >= 0; i = i - 1)`
54			`begin : level_0`
55			`assign v_d[0][i] = (a_complete[4 * i + 3 : 4 * i] == 4'b0000) ? 1'b0 : 1'b1;`
56			`assign p_d[0][2i+1:2i] = (a_complete[4 * i + 3] == 1'b1) ? 2'b00 :`
57			`(a_complete[4 * i + 2] == 1'b1) ? 2'b01 :`
58			`(a_complete[4 * i + 1] == 1'b1) ? 2'b10 : 2'b11;`
59			`end`
60			`end`
61			`endgenerate`
62
63			`generate`
64			`begin : level_generation_begin`
65			`genvar i;`
66			`for (i = 1; i <= nr_levels - 1; i = i + 1)`
67			`begin : level_generation`
68			`genvar j;`
69			`for (j = 0; j <= max_pow_2/(2 ** (i + 2)) - 1; j = j + 1)`
70			`begin : v_levels`
71			`assign v_d[i][j] = v_q[i - 1][2j+1] \| v_q[i - 1][2j];`
72			`end`
73
74			`for (j = 0; j <= max_pow_2/(2 ** (i + 2)) - 1; j = j + 1)`
75			`begin : p_levels`
76			`assign p_d[i][(i+2)j+i+1] = (~(v_q[i - 1][2j+1]));`
77			`assign p_d[i][(i+2)j+i : (i+2)j] = (v_q[i - 1][2j+1] == 1'b1) ? p_q[i - 1][j(2i+2)+2i+1 : j(2i+2) + i + 1] : p_q[i - 1][j(2i+2)+i : j(2i+2)];`
78			`end`
79			`end`
80			`end`
81			`endgenerate`
82
83			`generate`
84			`if (PIPELINE != 0)`
85			`begin : pipeline_stages`
86			`genvar i;`
87			`for (i = 0; i <= nr_levels - 2; i = i + 1)`
88			`begin : INSERTION`
89			`if ((i + 1) % nr_levels/(PIPELINE + 1) == 0)`
90			`begin : INS`
91			`d_ff #(max_pow_2) P_Di(.clk(clk), .rst(rst), .d(p_d[i]), .q(p_q[i]));`
92			`d_ff #(max_pow_2) V_Di(.clk(clk), .rst(rst), .d(v_d[i]), .q(v_q[i]));`
93			`end`
94
95			`if ((i + 1) % nr_levels/(PIPELINE + 1) != 0)`
96			`begin : NO_INS`
97			`assign p_q[i] = p_d[i];`
98			`assign v_q[i] = v_d[i];`
99			`end`
100			`end`
101			`assign p_q[nr_levels - 1] = p_d[nr_levels - 1];`
102			`assign v_q[nr_levels - 1] = v_d[nr_levels - 1];`
103			`end`
104			`endgenerate`
105
106			`generate`
107			`if (PIPELINE == 0)`
108			`begin : no_pipeline`
109			`genvar i;`
110			`for (i = 0; i <= nr_levels - 1; i = i + 1)`
111			`begin : NO_INSERTION`
112			`assign p_q[i] = p_d[i];`
113			`assign v_q[i] = v_d[i];`
114			`end`
115			`end`
116			`endgenerate`
117
118			`assign lzc[size_lz - 1:0] = p_q[nr_levels - 1][size_lz - 1:0];`
119
120			`generate`
121			`begin : lz_ovf_begin`
122			`genvar i;`
123			`for (i = 0; i <= size_lz - 1; i = i + 1)`
124			`begin : lz_ovf`
125			`assign lz[i] = lzc[i] & ((~ovf));`
126			`end`
127			`end`
128			`endgenerate`
129
130			`endmodule`

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[/] [xilinx_virtex_fp_library/] [trunk/] [DualPathFPAdderMappedConversions/] [leading_zeros.v] - Blame information for rev 19