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Subversion Repositories xmatchpro

[/] [xmatchpro/] [trunk/] [xmw4-comdec/] [xmatch_sim7/] [Behavioral.wcfg] - Blame information for rev 9

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      bus2ip_clk
      bus2ip_clk
   
   
      bus2ip_resetn
      bus2ip_resetn
   
   
      bus2ip_mstrd_src_rdy_n
      bus2ip_mstrd_src_rdy_n
   
   
      bus2ip_mstrd_eof_n
      bus2ip_mstrd_eof_n
   
   
      bus2ip_data[31:0]
      bus2ip_data[31:0]
   
   
      ip2bus_mstrd_dst_dsc_n
      ip2bus_mstrd_dst_dsc_n
   
   
      u_dataout_std[31:0]
      u_dataout_std[31:0]
      HEXRADIX
   
   
      c_dataout_std[31:0]
      c_dataout_std[31:0]
   
   
      u_data_valid_std_bit
      u_data_valid_std_bit
   
   
      c_data_valid_std_bit
      c_data_valid_std_bit
   
   
      rst_codmu
      rst_codmu
   
   
      clk_codmu
      clk_codmu
   
   
      rst_host
      rst_host
   
   
      clk_host
      clk_host
   
   
      din_host[31:0]
      din_host[31:0]
   
   
      wr_en_host
      wr_en_host
   
   
      rd_en_host
      rd_en_host
   
   
      dout_host[31:0]
      dout_host[31:0]
   
   
      full_host
      full_host
   
   
      overflow_host
      overflow_host
   
   
      empty_host
      empty_host
   
   
      underflow_host
      underflow_host
   
   
      addr[3:0]
      addr[3:0]
   
   
      ctrl[3:0]
      ctrl[3:0]
   
   
      trshold[7:0]
      trshold[7:0]
   
   
      bloksiz[15:0]
      bloksiz[15:0]
   
   
      filesiz[31:0]
      filesiz[31:0]
   
   
      statc[7:0]
      statc[7:0]
   
   
      statd[7:0]
      statd[7:0]
   
   
      statr[7:0]
      statr[7:0]
   
   
      statw[7:0]
      statw[7:0]
   
   
      cs
      cs
   
   
      rw
      rw
   
   
      address[3:0]
      address[3:0]
   
   
      control[31:0]
      control[31:0]
   
   
      clk
      clk
   
   
      clear
      clear
   
   
      bus_acknowledge_cc
      bus_acknowledge_cc
   
   
      bus_acknowledge_cu
      bus_acknowledge_cu
   
   
      bus_acknowledge_dc
      bus_acknowledge_dc
   
   
      bus_acknowledge_du
      bus_acknowledge_du
   
   
      wait_cu
      wait_cu
   
   
      wait_cc
      wait_cc
   
   
      wait_dc
      wait_dc
   
   
      wait_du
      wait_du
   
   
      u_datain[31:0]
      u_datain[31:0]
   
   
      c_datain[31:0]
      c_datain[31:0]
   
   
      u_dataout[31:0]
      u_dataout[31:0]
   
   
      c_dataout[31:0]
      c_dataout[31:0]
   
   
      finished_c
      finished_c
   
   
      finished_d
      finished_d
   
   
      compressing
      compressing
   
   
      flushing_c
      flushing_c
   
   
      flushing_d
      flushing_d
   
   
      decompressing
      decompressing
   
   
      u_data_valid
      u_data_valid
   
   
      c_data_valid
      c_data_valid
   
   
      decoding_overflow
      decoding_overflow
   
   
      coding_overflow
      coding_overflow
   
   
      crc_error
      crc_error
   
   
      interrupt_request
      interrupt_request
   
   
      interrupt_acknowledge
      interrupt_acknowledge
   
   
      bus_request_cc
      bus_request_cc
   
   
      bus_request_cu
      bus_request_cu
   
   
      bus_request_dc
      bus_request_dc
   
   
      bus_request_du
      bus_request_du
   
   
      cs_bit
      cs_bit
   
   
      rw_bit
      rw_bit
   
   
      address_bit[3:0]
      address_bit[3:0]
   
   
      control_std[31:0]
      control_std[31:0]
   
   
      clk_std
      clk_std
   
   
      clear_bit
      clear_bit
   
   
      resetn_std
      resetn_std
   
   
      bus_acknowledge_cc_bit
      bus_acknowledge_cc_bit
   
   
      bus_acknowledge_cu_bit
      bus_acknowledge_cu_bit
   
   
      bus_acknowledge_dc_bit
      bus_acknowledge_dc_bit
   
   
      bus_acknowledge_du_bit
      bus_acknowledge_du_bit
   
   
      wait_cu_bit
      wait_cu_bit
   
   
      wait_cc_bit
      wait_cc_bit
   
   
      wait_du_bit
      wait_du_bit
   
   
      c_datain_bit[31:0]
      c_datain_bit[31:0]
   
   
      finished_c_bit
      finished_c_bit
   
   
      finished_d_bit
      finished_d_bit
   
   
      u_data_valid_bit
      u_data_valid_bit
   
   
      c_data_valid_bit
      c_data_valid_bit
   
   
      interupt_acknwldge_bit
      interupt_acknwldge_bit
   
   
      bus_request_cc_bit
      bus_request_cc_bit
   
   
      bus_request_cu_bit
      bus_request_cu_bit
   
   
      bus_request_du_bit
      bus_request_du_bit
   
   
      reg_address[3:0]
      reg_address[3:0]
   
   
      reg_control[3:0]
      reg_control[3:0]
   
   
      reg_threshold[7:0]
      reg_threshold[7:0]
   
   
      reg_bytesize[15:0]
      reg_bytesize[15:0]
   
   
      cur_state1
      cur_state1
   
   
      next_state1
      next_state1
   
   
      slv_reg0[31:0]
      slv_reg0[31:0]
   
   
      reg_cr_test_bit
      reg_cr_test_bit
   
   
      reg_cr_31_to_28[3:0]
      reg_cr_31_to_28[3:0]
   
   
      reg_cr_18_to_12[6:0]
      reg_cr_18_to_12[6:0]
   
   
      reg_cr_11_to_0[11:0]
      reg_cr_11_to_0[11:0]
   
   
      u_datain_reg[31:0]
      u_datain_reg[31:0]
   
   
      c_datain_reg[31:0]
      c_datain_reg[31:0]
   
   
      int_ret_cu_size
      int_ret_cu_size
   
   
      int_ret_dc_size
      int_ret_dc_size
   
   
      clk_bit
      clk_bit
   
   
      wait_dc_bit
      wait_dc_bit
   
   
      bus_request_dc_bit
      bus_request_dc_bit
   
   
      fifo_read_signal
      fifo_read_signal
   
   
      fifo_data_out[31:0]
      fifo_data_out[31:0]
      HEXRADIX
   
   
      c_datain_regx[31:0]
      c_datain_regx[31:0]
      HEXRADIX
   
   
      bus2ip_mstrd_d[31:0]
      bus2ip_mstrd_d[31:0]
      HEXRADIX
   
   
      u_datain_bit[31:0]
      u_datain_bit[31:0]
      HEXRADIX
   
   
      fifo_data_in[31:0]
      fifo_data_in[31:0]
      HEXRADIX
   
   
      cur_state
      cur_state
   
   
      next_state
      next_state
   
   
      cur_state_status
      cur_state_status
   
   
      next_state_status
      next_state_status
   
   
      din_codmu[31:0]
      din_codmu[31:0]
   
   
      wr_en_codmu
      wr_en_codmu
   
   
      rd_en_codmu
      rd_en_codmu
   
   
      dout_codmu[31:0]
      dout_codmu[31:0]
   
   
      full_codmu
      full_codmu
   
   
      overflow_codmu
      overflow_codmu
   
   
      empty_codmu
      empty_codmu
   
   
      rst_buffer
      rst_buffer
   
   
      underflow_codmu
      underflow_codmu
   
   
      wr_en_host_sm
      wr_en_host_sm
   
   
      wr_en_host_conc
      wr_en_host_conc
   
   
      u_datain_regx[31:0]
      u_datain_regx[31:0]
   


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Subversion Repositories xmatchpro

[/] [xmatchpro/] [trunk/] [xmw4-comdec/] [xmatch_sim7/] [Behavioral.wcfg] - Blame information for rev 9

Line No.	Rev	Author	Line
1	9	eejlny
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25			`bus2ip_clk`
26			`bus2ip_clk`
27
28
29			`bus2ip_resetn`
30			`bus2ip_resetn`
31
32
33			`bus2ip_mstrd_src_rdy_n`
34			`bus2ip_mstrd_src_rdy_n`
35
36
37			`bus2ip_mstrd_eof_n`
38			`bus2ip_mstrd_eof_n`
39
40
41			`bus2ip_data[31:0]`
42			`bus2ip_data[31:0]`
43
44
45			`ip2bus_mstrd_dst_dsc_n`
46			`ip2bus_mstrd_dst_dsc_n`
47
48
49			`u_dataout_std[31:0]`
50			`u_dataout_std[31:0]`
51			`HEXRADIX`
52
53
54			`c_dataout_std[31:0]`
55			`c_dataout_std[31:0]`
56
57
58			`u_data_valid_std_bit`
59			`u_data_valid_std_bit`
60
61
62			`c_data_valid_std_bit`
63			`c_data_valid_std_bit`
64
65
66			`rst_codmu`
67			`rst_codmu`
68
69
70			`clk_codmu`
71			`clk_codmu`
72
73
74			`rst_host`
75			`rst_host`
76
77
78			`clk_host`
79			`clk_host`
80
81
82			`din_host[31:0]`
83			`din_host[31:0]`
84
85
86			`wr_en_host`
87			`wr_en_host`
88
89
90			`rd_en_host`
91			`rd_en_host`
92
93
94			`dout_host[31:0]`
95			`dout_host[31:0]`
96
97
98			`full_host`
99			`full_host`
100
101
102			`overflow_host`
103			`overflow_host`
104
105
106			`empty_host`
107			`empty_host`
108
109
110			`underflow_host`
111			`underflow_host`
112
113
114			`addr[3:0]`
115			`addr[3:0]`
116
117
118			`ctrl[3:0]`
119			`ctrl[3:0]`
120
121
122			`trshold[7:0]`
123			`trshold[7:0]`
124
125
126			`bloksiz[15:0]`
127			`bloksiz[15:0]`
128
129
130			`filesiz[31:0]`
131			`filesiz[31:0]`
132
133
134			`statc[7:0]`
135			`statc[7:0]`
136
137
138			`statd[7:0]`
139			`statd[7:0]`
140
141
142			`statr[7:0]`
143			`statr[7:0]`
144
145
146			`statw[7:0]`
147			`statw[7:0]`
148
149
150			`cs`
151			`cs`
152
153
154			`rw`
155			`rw`
156
157
158			`address[3:0]`
159			`address[3:0]`
160
161
162			`control[31:0]`
163			`control[31:0]`
164
165
166			`clk`
167			`clk`
168
169
170			`clear`
171			`clear`
172
173
174			`bus_acknowledge_cc`
175			`bus_acknowledge_cc`
176
177
178			`bus_acknowledge_cu`
179			`bus_acknowledge_cu`
180
181
182			`bus_acknowledge_dc`
183			`bus_acknowledge_dc`
184
185
186			`bus_acknowledge_du`
187			`bus_acknowledge_du`
188
189
190			`wait_cu`
191			`wait_cu`
192
193
194			`wait_cc`
195			`wait_cc`
196
197
198			`wait_dc`
199			`wait_dc`
200
201
202			`wait_du`
203			`wait_du`
204
205
206			`u_datain[31:0]`
207			`u_datain[31:0]`
208
209
210			`c_datain[31:0]`
211			`c_datain[31:0]`
212
213
214			`u_dataout[31:0]`
215			`u_dataout[31:0]`
216
217
218			`c_dataout[31:0]`
219			`c_dataout[31:0]`
220
221
222			`finished_c`
223			`finished_c`
224
225
226			`finished_d`
227			`finished_d`
228
229
230			`compressing`
231			`compressing`
232
233
234			`flushing_c`
235			`flushing_c`
236
237
238			`flushing_d`
239			`flushing_d`
240
241
242			`decompressing`
243			`decompressing`
244
245
246			`u_data_valid`
247			`u_data_valid`
248
249
250			`c_data_valid`
251			`c_data_valid`
252
253
254			`decoding_overflow`
255			`decoding_overflow`
256
257
258			`coding_overflow`
259			`coding_overflow`
260
261
262			`crc_error`
263			`crc_error`
264
265
266			`interrupt_request`
267			`interrupt_request`
268
269
270			`interrupt_acknowledge`
271			`interrupt_acknowledge`
272
273
274			`bus_request_cc`
275			`bus_request_cc`
276
277
278			`bus_request_cu`
279			`bus_request_cu`
280
281
282			`bus_request_dc`
283			`bus_request_dc`
284
285
286			`bus_request_du`
287			`bus_request_du`
288
289
290			`cs_bit`
291			`cs_bit`
292
293
294			`rw_bit`
295			`rw_bit`
296
297
298			`address_bit[3:0]`
299			`address_bit[3:0]`
300
301
302			`control_std[31:0]`
303			`control_std[31:0]`
304
305
306			`clk_std`
307			`clk_std`
308
309
310			`clear_bit`
311			`clear_bit`
312
313
314			`resetn_std`
315			`resetn_std`
316
317
318			`bus_acknowledge_cc_bit`
319			`bus_acknowledge_cc_bit`
320
321
322			`bus_acknowledge_cu_bit`
323			`bus_acknowledge_cu_bit`
324
325
326			`bus_acknowledge_dc_bit`
327			`bus_acknowledge_dc_bit`
328
329
330			`bus_acknowledge_du_bit`
331			`bus_acknowledge_du_bit`
332
333
334			`wait_cu_bit`
335			`wait_cu_bit`
336
337
338			`wait_cc_bit`
339			`wait_cc_bit`
340
341
342			`wait_du_bit`
343			`wait_du_bit`
344
345
346			`c_datain_bit[31:0]`
347			`c_datain_bit[31:0]`
348
349
350			`finished_c_bit`
351			`finished_c_bit`
352
353
354			`finished_d_bit`
355			`finished_d_bit`
356
357
358			`u_data_valid_bit`
359			`u_data_valid_bit`
360
361
362			`c_data_valid_bit`
363			`c_data_valid_bit`
364
365
366			`interupt_acknwldge_bit`
367			`interupt_acknwldge_bit`
368
369
370			`bus_request_cc_bit`
371			`bus_request_cc_bit`
372
373
374			`bus_request_cu_bit`
375			`bus_request_cu_bit`
376
377
378			`bus_request_du_bit`
379			`bus_request_du_bit`
380
381
382			`reg_address[3:0]`
383			`reg_address[3:0]`
384
385
386			`reg_control[3:0]`
387			`reg_control[3:0]`
388
389
390			`reg_threshold[7:0]`
391			`reg_threshold[7:0]`
392
393
394			`reg_bytesize[15:0]`
395			`reg_bytesize[15:0]`
396
397
398			`cur_state1`
399			`cur_state1`
400
401
402			`next_state1`
403			`next_state1`
404
405
406			`slv_reg0[31:0]`
407			`slv_reg0[31:0]`
408
409
410			`reg_cr_test_bit`
411			`reg_cr_test_bit`
412
413
414			`reg_cr_31_to_28[3:0]`
415			`reg_cr_31_to_28[3:0]`
416
417
418			`reg_cr_18_to_12[6:0]`
419			`reg_cr_18_to_12[6:0]`
420
421
422			`reg_cr_11_to_0[11:0]`
423			`reg_cr_11_to_0[11:0]`
424
425
426			`u_datain_reg[31:0]`
427			`u_datain_reg[31:0]`
428
429
430			`c_datain_reg[31:0]`
431			`c_datain_reg[31:0]`
432
433
434			`int_ret_cu_size`
435			`int_ret_cu_size`
436
437
438			`int_ret_dc_size`
439			`int_ret_dc_size`
440
441
442			`clk_bit`
443			`clk_bit`
444
445
446			`wait_dc_bit`
447			`wait_dc_bit`
448
449
450			`bus_request_dc_bit`
451			`bus_request_dc_bit`
452
453
454			`fifo_read_signal`
455			`fifo_read_signal`
456
457
458			`fifo_data_out[31:0]`
459			`fifo_data_out[31:0]`
460			`HEXRADIX`
461
462
463			`c_datain_regx[31:0]`
464			`c_datain_regx[31:0]`
465			`HEXRADIX`
466
467
468			`bus2ip_mstrd_d[31:0]`
469			`bus2ip_mstrd_d[31:0]`
470			`HEXRADIX`
471
472
473			`u_datain_bit[31:0]`
474			`u_datain_bit[31:0]`
475			`HEXRADIX`
476
477
478			`fifo_data_in[31:0]`
479			`fifo_data_in[31:0]`
480			`HEXRADIX`
481
482
483			`cur_state`
484			`cur_state`
485
486
487			`next_state`
488			`next_state`
489
490
491			`cur_state_status`
492			`cur_state_status`
493
494
495			`next_state_status`
496			`next_state_status`
497
498
499			`din_codmu[31:0]`
500			`din_codmu[31:0]`
501
502
503			`wr_en_codmu`
504			`wr_en_codmu`
505
506
507			`rd_en_codmu`
508			`rd_en_codmu`
509
510
511			`dout_codmu[31:0]`
512			`dout_codmu[31:0]`
513
514
515			`full_codmu`
516			`full_codmu`
517
518
519			`overflow_codmu`
520			`overflow_codmu`
521
522
523			`empty_codmu`
524			`empty_codmu`
525
526
527			`rst_buffer`
528			`rst_buffer`
529
530
531			`underflow_codmu`
532			`underflow_codmu`
533
534
535			`wr_en_host_sm`
536			`wr_en_host_sm`
537
538
539			`wr_en_host_conc`
540			`wr_en_host_conc`
541
542
543			`u_datain_regx[31:0]`
544			`u_datain_regx[31:0]`
545
546