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#--------------------------------------------------------------------------------

#--

#--  BMG core Demo Testbench 

#--

#--------------------------------------------------------------------------------

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# Filename: vcs_session.tcl

#

# Description:

#   This is the VCS wave form file.

#

#--------------------------------------------------------------------------------

if { ![gui_is_db_opened -db {bmg_vcs.vpd}] } {

        gui_open_db -design V1 -file bmg_vcs.vpd -nosource

}

gui_set_precision 1ps

gui_set_time_units 1ps

gui_open_window Wave

gui_sg_create DP_RAM_XILINX_512_Group

gui_list_add_group -id Wave.1 {DP_RAM_XILINX_512_Group}

      gui_sg_addsignal -group DP_RAM_XILINX_512_Group  /DP_RAM_XILINX_512_tb/status

      gui_sg_addsignal -group DP_RAM_XILINX_512_Group  /DP_RAM_XILINX_512_tb/DP_RAM_XILINX_512_synth_inst/bmg_port/CLKA

      gui_sg_addsignal -group DP_RAM_XILINX_512_Group  /DP_RAM_XILINX_512_tb/DP_RAM_XILINX_512_synth_inst/bmg_port/ADDRA

      gui_sg_addsignal -group DP_RAM_XILINX_512_Group  /DP_RAM_XILINX_512_tb/DP_RAM_XILINX_512_synth_inst/bmg_port/DINA

      gui_sg_addsignal -group DP_RAM_XILINX_512_Group  /DP_RAM_XILINX_512_tb/DP_RAM_XILINX_512_synth_inst/bmg_port/WEA

      gui_sg_addsignal -group DP_RAM_XILINX_512_Group  /DP_RAM_XILINX_512_tb/DP_RAM_XILINX_512_synth_inst/bmg_port/CLKB

      gui_sg_addsignal -group DP_RAM_XILINX_512_Group  /DP_RAM_XILINX_512_tb/DP_RAM_XILINX_512_synth_inst/bmg_port/ADDRB

      gui_sg_addsignal -group DP_RAM_XILINX_512_Group  /DP_RAM_XILINX_512_tb/DP_RAM_XILINX_512_synth_inst/bmg_port/ENB

      gui_sg_addsignal -group DP_RAM_XILINX_512_Group  /DP_RAM_XILINX_512_tb/DP_RAM_XILINX_512_synth_inst/bmg_port/DOUTB

gui_zoom -window Wave.1 -full