OpenCores
URL https://opencores.org/ocsvn/xmatchpro/xmatchpro/trunk

Subversion Repositories xmatchpro

[/] [xmatchpro/] [trunk/] [xmw4-comdec/] [xmatch_sim7/] [coregen/] [DP_RAM_XILINX_512/] [simulation/] [timing/] [wave_mti.do] - Blame information for rev 9

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 9 eejlny
 
2
 
3
 
4
 
5
 
6
 
7
 
8
 
9
 
10
onerror {resume}
11
quietly WaveActivateNextPane {} 0
12
 
13
 
14
      add wave -noupdate /DP_RAM_XILINX_512_tb/status
15
      add wave -noupdate /DP_RAM_XILINX_512_tb/DP_RAM_XILINX_512_synth_inst/bmg_port/CLKA
16
      add wave -noupdate /DP_RAM_XILINX_512_tb/DP_RAM_XILINX_512_synth_inst/bmg_port/ADDRA
17
      add wave -noupdate /DP_RAM_XILINX_512_tb/DP_RAM_XILINX_512_synth_inst/bmg_port/DINA
18
      add wave -noupdate /DP_RAM_XILINX_512_tb/DP_RAM_XILINX_512_synth_inst/bmg_port/WEA
19
      add wave -noupdate /DP_RAM_XILINX_512_tb/DP_RAM_XILINX_512_synth_inst/bmg_port/CLKB
20
      add wave -noupdate /DP_RAM_XILINX_512_tb/DP_RAM_XILINX_512_synth_inst/bmg_port/ADDRB
21
      add wave -noupdate /DP_RAM_XILINX_512_tb/DP_RAM_XILINX_512_synth_inst/bmg_port/ENB
22
      add wave -noupdate /DP_RAM_XILINX_512_tb/DP_RAM_XILINX_512_synth_inst/bmg_port/DOUTB
23
TreeUpdate [SetDefaultTree]
24
WaveRestoreCursors {{Cursor 1} {0 ps} 0}
25
configure wave -namecolwidth 150
26
configure wave -valuecolwidth 100
27
configure wave -justifyvalue left
28
configure wave -signalnamewidth 1
29
configure wave -snapdistance 10
30
configure wave -datasetprefix 0
31
configure wave -rowmargin 4
32
configure wave -childrowmargin 2
33
configure wave -gridoffset 0
34
configure wave -gridperiod 1
35
configure wave -griddelta 40
36
configure wave -timeline 0
37
configure wave -timelineunits ps
38
update
39
WaveRestoreZoom {0 ps} {9464063 ps}

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.