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#!/bin/sh

# Clean up the results directory

rm -rf results

mkdir results

#Synthesize the Wrapper Files

echo 'Synthesizing example design with XST';

xst -ifn xst.scr

cp DP_RAM_XILINX_MASK_exdes.ngc ./results/

# Copy the netlist generated by Coregen

echo 'Copying files from the netlist directory to the results directory'

cp ../../DP_RAM_XILINX_MASK.ngc results/

#  Copy the constraints files generated by Coregen

echo 'Copying files from constraints directory to results directory'

cp ../example_design/DP_RAM_XILINX_MASK_exdes.ucf results/

cd results

echo 'Running ngdbuild'

ngdbuild -p xc7vx485t-ffg1761-2 DP_RAM_XILINX_MASK_exdes

echo 'Running map'

map DP_RAM_XILINX_MASK_exdes -o mapped.ncd -pr i

echo 'Running par'

par mapped.ncd routed.ncd

echo 'Running trce'

trce -e 10 routed.ncd mapped.pcf -o routed

echo 'Running design through bitgen'

bitgen -w routed -g UnconstrainedPins:Allow

echo 'Running netgen to create gate level VHDL model'

netgen -ofmt vhdl -sim -tm DP_RAM_XILINX_MASK_exdes -pcf mapped.pcf -w routed.ncd routed.vhd