1 |
9 |
eejlny |
--------------------------------------------------------------------------------
|
2 |
|
|
--
|
3 |
|
|
-- FIFO Generator Core Demo Testbench
|
4 |
|
|
--
|
5 |
|
|
--------------------------------------------------------------------------------
|
6 |
|
|
--
|
7 |
|
|
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
|
8 |
|
|
--
|
9 |
|
|
-- This file contains confidential and proprietary information
|
10 |
|
|
-- of Xilinx, Inc. and is protected under U.S. and
|
11 |
|
|
-- international copyright and other intellectual property
|
12 |
|
|
-- laws.
|
13 |
|
|
--
|
14 |
|
|
-- DISCLAIMER
|
15 |
|
|
-- This disclaimer is not a license and does not grant any
|
16 |
|
|
-- rights to the materials distributed herewith. Except as
|
17 |
|
|
-- otherwise provided in a valid license issued to you by
|
18 |
|
|
-- Xilinx, and to the maximum extent permitted by applicable
|
19 |
|
|
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
20 |
|
|
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
21 |
|
|
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
22 |
|
|
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
23 |
|
|
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
24 |
|
|
-- (2) Xilinx shall not be liable (whether in contract or tort,
|
25 |
|
|
-- including negligence, or under any other theory of
|
26 |
|
|
-- liability) for any loss or damage of any kind or nature
|
27 |
|
|
-- related to, arising under or in connection with these
|
28 |
|
|
-- materials, including for any direct, or any indirect,
|
29 |
|
|
-- special, incidental, or consequential loss or damage
|
30 |
|
|
-- (including loss of data, profits, goodwill, or any type of
|
31 |
|
|
-- loss or damage suffered as a result of any action brought
|
32 |
|
|
-- by a third party) even if such damage or loss was
|
33 |
|
|
-- reasonably foreseeable or Xilinx had been advised of the
|
34 |
|
|
-- possibility of the same.
|
35 |
|
|
--
|
36 |
|
|
-- CRITICAL APPLICATIONS
|
37 |
|
|
-- Xilinx products are not designed or intended to be fail-
|
38 |
|
|
-- safe, or for use in any application requiring fail-safe
|
39 |
|
|
-- performance, such as life-support or safety devices or
|
40 |
|
|
-- systems, Class III medical devices, nuclear facilities,
|
41 |
|
|
-- applications related to the deployment of airbags, or any
|
42 |
|
|
-- other applications that could lead to death, personal
|
43 |
|
|
-- injury, or severe property or environmental damage
|
44 |
|
|
-- (individually and collectively, "Critical
|
45 |
|
|
-- Applications"). Customer assumes the sole risk and
|
46 |
|
|
-- liability of any use of Xilinx products in Critical
|
47 |
|
|
-- Applications, subject only to applicable laws and
|
48 |
|
|
-- regulations governing limitations on product liability.
|
49 |
|
|
--
|
50 |
|
|
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
51 |
|
|
-- PART OF THIS FILE AT ALL TIMES.
|
52 |
|
|
--------------------------------------------------------------------------------
|
53 |
|
|
--
|
54 |
|
|
-- Filename: fifo_2048x8wr_256x64rd_prog_full_fifo_gen_v9_3_tb.vhd
|
55 |
|
|
--
|
56 |
|
|
-- Description:
|
57 |
|
|
-- This is the demo testbench top file for fifo_generator core.
|
58 |
|
|
--
|
59 |
|
|
--------------------------------------------------------------------------------
|
60 |
|
|
-- Library Declarations
|
61 |
|
|
--------------------------------------------------------------------------------
|
62 |
|
|
LIBRARY ieee;
|
63 |
|
|
LIBRARY std;
|
64 |
|
|
USE ieee.std_logic_1164.ALL;
|
65 |
|
|
USE ieee.std_logic_unsigned.ALL;
|
66 |
|
|
USE IEEE.std_logic_arith.ALL;
|
67 |
|
|
USE IEEE.std_logic_misc.ALL;
|
68 |
|
|
USE ieee.numeric_std.ALL;
|
69 |
|
|
USE ieee.std_logic_textio.ALL;
|
70 |
|
|
USE std.textio.ALL;
|
71 |
|
|
|
72 |
|
|
LIBRARY work;
|
73 |
|
|
USE work.fifo_2048x8wr_256x64rd_prog_full_fifo_gen_v9_3_pkg.ALL;
|
74 |
|
|
|
75 |
|
|
ENTITY fifo_2048x8wr_256x64rd_prog_full_fifo_gen_v9_3_tb IS
|
76 |
|
|
END ENTITY;
|
77 |
|
|
|
78 |
|
|
|
79 |
|
|
ARCHITECTURE fifo_2048x8wr_256x64rd_prog_full_fifo_gen_v9_3_arch OF fifo_2048x8wr_256x64rd_prog_full_fifo_gen_v9_3_tb IS
|
80 |
|
|
SIGNAL status : STD_LOGIC_VECTOR(7 DOWNTO 0) := "00000000";
|
81 |
|
|
SIGNAL wr_clk : STD_LOGIC;
|
82 |
|
|
SIGNAL rd_clk : STD_LOGIC;
|
83 |
|
|
SIGNAL reset : STD_LOGIC;
|
84 |
|
|
SIGNAL sim_done : STD_LOGIC := '0';
|
85 |
|
|
SIGNAL end_of_sim : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '0');
|
86 |
|
|
-- Write and Read clock periods
|
87 |
|
|
CONSTANT wr_clk_period_by_2 : TIME := 100 ns;
|
88 |
|
|
CONSTANT rd_clk_period_by_2 : TIME := 200 ns;
|
89 |
|
|
-- Procedures to display strings
|
90 |
|
|
PROCEDURE disp_str(CONSTANT str:IN STRING) IS
|
91 |
|
|
variable dp_l : line := null;
|
92 |
|
|
BEGIN
|
93 |
|
|
write(dp_l,str);
|
94 |
|
|
writeline(output,dp_l);
|
95 |
|
|
END PROCEDURE;
|
96 |
|
|
|
97 |
|
|
PROCEDURE disp_hex(signal hex:IN STD_LOGIC_VECTOR(7 DOWNTO 0)) IS
|
98 |
|
|
variable dp_lx : line := null;
|
99 |
|
|
BEGIN
|
100 |
|
|
hwrite(dp_lx,hex);
|
101 |
|
|
writeline(output,dp_lx);
|
102 |
|
|
END PROCEDURE;
|
103 |
|
|
|
104 |
|
|
BEGIN
|
105 |
|
|
|
106 |
|
|
-- Generation of clock
|
107 |
|
|
|
108 |
|
|
PROCESS BEGIN
|
109 |
|
|
WAIT FOR 200 ns; -- Wait for global reset
|
110 |
|
|
WHILE 1 = 1 LOOP
|
111 |
|
|
wr_clk <= '0';
|
112 |
|
|
WAIT FOR wr_clk_period_by_2;
|
113 |
|
|
wr_clk <= '1';
|
114 |
|
|
WAIT FOR wr_clk_period_by_2;
|
115 |
|
|
END LOOP;
|
116 |
|
|
END PROCESS;
|
117 |
|
|
|
118 |
|
|
PROCESS BEGIN
|
119 |
|
|
WAIT FOR 400 ns;-- Wait for global reset
|
120 |
|
|
WHILE 1 = 1 LOOP
|
121 |
|
|
rd_clk <= '0';
|
122 |
|
|
WAIT FOR rd_clk_period_by_2;
|
123 |
|
|
rd_clk <= '1';
|
124 |
|
|
WAIT FOR rd_clk_period_by_2;
|
125 |
|
|
END LOOP;
|
126 |
|
|
END PROCESS;
|
127 |
|
|
|
128 |
|
|
-- Generation of Reset
|
129 |
|
|
|
130 |
|
|
PROCESS BEGIN
|
131 |
|
|
reset <= '1';
|
132 |
|
|
WAIT FOR 4200 ns;
|
133 |
|
|
reset <= '0';
|
134 |
|
|
WAIT;
|
135 |
|
|
END PROCESS;
|
136 |
|
|
|
137 |
|
|
|
138 |
|
|
-- Error message printing based on STATUS signal from fifo_2048x8wr_256x64rd_prog_full_fifo_gen_v9_3_synth
|
139 |
|
|
|
140 |
|
|
PROCESS(status)
|
141 |
|
|
BEGIN
|
142 |
|
|
IF(status /= "0" AND status /= "1") THEN
|
143 |
|
|
disp_str("STATUS:");
|
144 |
|
|
disp_hex(status);
|
145 |
|
|
END IF;
|
146 |
|
|
|
147 |
|
|
IF(status(7) = '1') THEN
|
148 |
|
|
assert false
|
149 |
|
|
report "Data mismatch found"
|
150 |
|
|
severity error;
|
151 |
|
|
END IF;
|
152 |
|
|
|
153 |
|
|
IF(status(1) = '1') THEN
|
154 |
|
|
END IF;
|
155 |
|
|
|
156 |
|
|
IF(status(5) = '1') THEN
|
157 |
|
|
assert false
|
158 |
|
|
report "Empty flag Mismatch/timeout"
|
159 |
|
|
severity error;
|
160 |
|
|
END IF;
|
161 |
|
|
|
162 |
|
|
IF(status(6) = '1') THEN
|
163 |
|
|
assert false
|
164 |
|
|
report "Full Flag Mismatch/timeout"
|
165 |
|
|
severity error;
|
166 |
|
|
END IF;
|
167 |
|
|
END PROCESS;
|
168 |
|
|
|
169 |
|
|
|
170 |
|
|
PROCESS
|
171 |
|
|
BEGIN
|
172 |
|
|
wait until sim_done = '1';
|
173 |
|
|
IF(status /= "0" AND status /= "1") THEN
|
174 |
|
|
assert false
|
175 |
|
|
report "Simulation failed"
|
176 |
|
|
severity failure;
|
177 |
|
|
ELSE
|
178 |
|
|
assert false
|
179 |
|
|
report "Test Completed Successfully"
|
180 |
|
|
severity failure;
|
181 |
|
|
END IF;
|
182 |
|
|
END PROCESS;
|
183 |
|
|
|
184 |
|
|
PROCESS
|
185 |
|
|
BEGIN
|
186 |
|
|
wait for 400 ms;
|
187 |
|
|
assert false
|
188 |
|
|
report "Test bench timed out"
|
189 |
|
|
severity failure;
|
190 |
|
|
END PROCESS;
|
191 |
|
|
|
192 |
|
|
-- Instance of fifo_2048x8wr_256x64rd_prog_full_fifo_gen_v9_3_synth
|
193 |
|
|
|
194 |
|
|
fifo_2048x8wr_256x64rd_prog_full_fifo_gen_v9_3_synth_inst:fifo_2048x8wr_256x64rd_prog_full_fifo_gen_v9_3_synth
|
195 |
|
|
GENERIC MAP(
|
196 |
|
|
FREEZEON_ERROR => 0,
|
197 |
|
|
TB_STOP_CNT => 2,
|
198 |
|
|
TB_SEED => 66
|
199 |
|
|
)
|
200 |
|
|
PORT MAP(
|
201 |
|
|
WR_CLK => wr_clk,
|
202 |
|
|
RD_CLK => rd_clk,
|
203 |
|
|
RESET => reset,
|
204 |
|
|
SIM_DONE => sim_done,
|
205 |
|
|
STATUS => status
|
206 |
|
|
);
|
207 |
|
|
|
208 |
|
|
END ARCHITECTURE;
|