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[/] [xmatchpro/] [trunk/] [xmw4-comdec/] [xmatch_sim7/] [ipcore_dir/] [fifo_2048x8wr_256x64rd_prog_full_fifo_gen_v9_3/] [simulation/] [functional/] [simulate_isim.bat] - Blame information for rev 9

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1 9 eejlny
:: (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
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::
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:: This file contains confidential and proprietary information
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:: of Xilinx, Inc. and is protected under U.S. and
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:: international copyright and other intellectual property
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:: laws.
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::
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:: DISCLAIMER
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:: This disclaimer is not a license and does not grant any
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:: otherwise provided in a valid license issued to you by
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:: Xilinx, and to the maximum extent permitted by applicable
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:: law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
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:: WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
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:: AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
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:: INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
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:: (2) Xilinx shall not be liable (whether in contract or tort,
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:: CRITICAL APPLICATIONS
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echo "Compiling Core VHDL UNISIM/Behavioral model"
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vhpcomp  -work work ..\\..\\..\\fifo_2048x8wr_256x64rd_prog_full_fifo_gen_v9_3.vhd
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vhpcomp  -work work ..\\..\\example_design\\fifo_2048x8wr_256x64rd_prog_full_fifo_gen_v9_3_exdes.vhd
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echo "Compiling Test Bench Files"
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vhpcomp -work work ..\\fifo_2048x8wr_256x64rd_prog_full_fifo_gen_v9_3_pkg.vhd
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vhpcomp -work work ..\\fifo_2048x8wr_256x64rd_prog_full_fifo_gen_v9_3_rng.vhd
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vhpcomp -work work ..\\fifo_2048x8wr_256x64rd_prog_full_fifo_gen_v9_3_dgen.vhd
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vhpcomp -work work ..\\fifo_2048x8wr_256x64rd_prog_full_fifo_gen_v9_3_dverif.vhd
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vhpcomp -work work ..\\fifo_2048x8wr_256x64rd_prog_full_fifo_gen_v9_3_pctrl.vhd
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vhpcomp -work work ..\\fifo_2048x8wr_256x64rd_prog_full_fifo_gen_v9_3_synth.vhd
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vhpcomp -work work ..\\fifo_2048x8wr_256x64rd_prog_full_fifo_gen_v9_3_tb.vhd
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fuse work.fifo_2048x8wr_256x64rd_prog_full_fifo_gen_v9_3_tb -L xilinxcorelib -L unisim -o fifo_2048x8wr_256x64rd_prog_full_fifo_gen_v9_3_tb.exe
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.\\fifo_2048x8wr_256x64rd_prog_full_fifo_gen_v9_3_tb.exe -gui -tclbatch .\\wave_isim.tcl

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