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--    This file is owned and controlled by Xilinx and must be used solely     --

--    for design, simulation, implementation and creation of design files     --

--    limited to Xilinx devices or technologies. Use with non-Xilinx          --

--    devices or technologies is expressly prohibited and immediately         --

--    terminates your license.                                                --

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--    XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY    --

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--    IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS      --

--    MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY      --

--    CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY       --

--    RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION.  XILINX EXPRESSLY       --

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--    (c) Copyright 1995-2015 Xilinx, Inc.                                    --

--    All rights reserved.                                                    --

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--    Generated from core with identifier: xilinx.com:ip:fifo_generator:9.3   --

--                                                                            --

--    Rev 1. The FIFO Generator is a parameterizable first-in/first-out       --

--    memory queue generator. Use it to generate resource and performance     --

--    optimized FIFOs with common or independent read/write clock domains,    --

--    and optional fixed or programmable full and empty flags and             --

--    handshaking signals.  Choose from a selection of memory resource        --

--    types for implementation.  Optional Hamming code based error            --

--    detection and correction as well as error injection capability for      --

--    system test help to insure data integrity.  FIFO width and depth are    --

--    parameterizable, and for native interface FIFOs, asymmetric read and    --

--    write port widths are also supported.                                   --

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-- Interfaces:

--    AXI4Stream_MASTER_M_AXIS

--    AXI4Stream_SLAVE_S_AXIS

--    AXI4_MASTER_M_AXI

--    AXI4_SLAVE_S_AXI

--    AXI4Lite_MASTER_M_AXI

--    AXI4Lite_SLAVE_S_AXI

--    master_aclk

--    slave_aclk

--    slave_aresetn

-- The following code must appear in the VHDL architecture header:

------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG

COMPONENT fifo_2048x8wr_256x64rd_prog_full_fifo_gen_v9_3

  PORT (

    rst : IN STD_LOGIC;

    wr_clk : IN STD_LOGIC;

    rd_clk : IN STD_LOGIC;

    din : IN STD_LOGIC_VECTOR(7 DOWNTO 0);

    wr_en : IN STD_LOGIC;

    rd_en : IN STD_LOGIC;

    dout : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);

    full : OUT STD_LOGIC;

    overflow : OUT STD_LOGIC;

    empty : OUT STD_LOGIC;

    underflow : OUT STD_LOGIC;

    rd_data_count : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);

    wr_data_count : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);

    prog_full : OUT STD_LOGIC

  );

END COMPONENT;

-- COMP_TAG_END ------ End COMPONENT Declaration ------------

-- The following code must appear in the VHDL architecture

-- body. Substitute your own instance name and net names.

------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG

your_instance_name : fifo_2048x8wr_256x64rd_prog_full_fifo_gen_v9_3

  PORT MAP (

    rst => rst,

    wr_clk => wr_clk,

    rd_clk => rd_clk,

    din => din,

    wr_en => wr_en,

    rd_en => rd_en,

    dout => dout,

    full => full,

    overflow => overflow,

    empty => empty,

    underflow => underflow,

    rd_data_count => rd_data_count,

    wr_data_count => wr_data_count,

    prog_full => prog_full

  );

-- INST_TAG_END ------ End INSTANTIATION Template ------------

-- You must compile the wrapper file fifo_2048x8wr_256x64rd_prog_full_fifo_gen_v9_3.vhd when simulating

-- the core, fifo_2048x8wr_256x64rd_prog_full_fifo_gen_v9_3. When compiling the wrapper file, be sure to

-- reference the XilinxCoreLib VHDL simulation library. For detailed

-- instructions, please refer to the "CORE Generator Help".