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--

-- FIFO Generator Core Demo Testbench 

--

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--

-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.

-- 

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--

-- Filename: fifo_generator_v9_3_tb.vhd

--

-- Description:

--   This is the demo testbench top file for fifo_generator core.

--

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-- Library Declarations

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LIBRARY ieee;

LIBRARY std;

USE ieee.std_logic_1164.ALL;

USE ieee.std_logic_unsigned.ALL;

USE IEEE.std_logic_arith.ALL;

USE IEEE.std_logic_misc.ALL;

USE ieee.numeric_std.ALL;

USE ieee.std_logic_textio.ALL;

USE std.textio.ALL;

LIBRARY work;

USE work.fifo_generator_v9_3_pkg.ALL;

ENTITY fifo_generator_v9_3_tb IS

END ENTITY;

ARCHITECTURE fifo_generator_v9_3_arch OF fifo_generator_v9_3_tb IS

 SIGNAL  status              : STD_LOGIC_VECTOR(7 DOWNTO 0) := "00000000";

 SIGNAL  wr_clk              : STD_LOGIC;

 SIGNAL  reset               : STD_LOGIC;

 SIGNAL  sim_done            : STD_LOGIC := '0';

 SIGNAL  end_of_sim          : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '0');

 -- Write and Read clock periods

 CONSTANT wr_clk_period_by_2 : TIME := 100 ns;

 -- Procedures to display strings

 PROCEDURE disp_str(CONSTANT str:IN STRING) IS

    variable dp_l : line := null;

 BEGIN

  write(dp_l,str);

  writeline(output,dp_l);

 END PROCEDURE;

 PROCEDURE disp_hex(signal hex:IN STD_LOGIC_VECTOR(7 DOWNTO 0)) IS

    variable dp_lx : line := null;

 BEGIN

  hwrite(dp_lx,hex);

  writeline(output,dp_lx);

 END PROCEDURE;

BEGIN

  -- Generation of clock

  PROCESS BEGIN

    WAIT FOR 200 ns; -- Wait for global reset

    WHILE 1 = 1 LOOP

      wr_clk <= '0';

      WAIT FOR wr_clk_period_by_2;

      wr_clk <= '1';

      WAIT FOR wr_clk_period_by_2;

    END LOOP;

  END PROCESS;

  -- Generation of Reset

  PROCESS BEGIN

    reset <= '1';

    WAIT FOR 2100 ns;

    reset <= '0';

    WAIT;

  END PROCESS;

  -- Error message printing based on STATUS signal from fifo_generator_v9_3_synth

  PROCESS(status)

  BEGIN

    IF(status /= "0" AND status /= "1") THEN

      disp_str("STATUS:");

      disp_hex(status);

    END IF;

    IF(status(7) = '1') THEN

      assert false

       report "Data mismatch found"

       severity error;

    END IF;

    IF(status(1) = '1') THEN

    END IF;

    IF(status(5) = '1') THEN

      assert false

       report "Empty flag Mismatch/timeout"

       severity error;

    END IF;

    IF(status(6) = '1') THEN

      assert false

       report "Full Flag Mismatch/timeout"

       severity error;

    END IF;

  END PROCESS;

  PROCESS

  BEGIN

    wait until sim_done = '1';

    IF(status /= "0" AND status /= "1") THEN

      assert false

      report "Simulation failed"

      severity failure;

    ELSE

      assert false

      report "Test Completed Successfully"

      severity failure;

    END IF;

  END PROCESS;

  PROCESS

  BEGIN

    wait for 400 ms;

    assert false

    report "Test bench timed out"

    severity failure;

  END PROCESS;

  -- Instance of fifo_generator_v9_3_synth

  fifo_generator_v9_3_synth_inst:fifo_generator_v9_3_synth

   GENERIC MAP(

              FREEZEON_ERROR => 0,

              TB_STOP_CNT    => 2,

              TB_SEED        => 35

              )

  PORT MAP(

           CLK           => wr_clk,

           RESET         => reset,

           SIM_DONE      => sim_done,

           STATUS        => status

          );

END ARCHITECTURE;