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rm -rf simv* csrc DVEfiles AN.DB

echo "Compiling Core VHDL UNISIM/Behavioral model"

vhdlan  ../../implement/results/routed.vhd

echo "Compiling Test Bench Files"

vhdlan   ../fifo_generator_v9_3_pkg.vhd

vhdlan   ../fifo_generator_v9_3_rng.vhd

vhdlan   ../fifo_generator_v9_3_dgen.vhd

vhdlan   ../fifo_generator_v9_3_dverif.vhd

vhdlan   ../fifo_generator_v9_3_pctrl.vhd

vhdlan   ../fifo_generator_v9_3_synth.vhd

vhdlan   ../fifo_generator_v9_3_tb.vhd

echo "Elaborating Design"

vcs -time_res 1ps +neg_tchk +vcs+lic+wait -debug fifo_generator_v9_3_tb

echo "Simulating Design"

./simv -ucli -i ucli_commands.key

dve -session vcs_session.tcl