OpenCores
URL https://opencores.org/ocsvn/xmatchpro/xmatchpro/trunk

Subversion Repositories xmatchpro

[/] [xmatchpro/] [trunk/] [xmw4-comdec/] [xmatch_sim7/] [isim/] [testbench_isim_beh.exe.sim/] [work/] [a_0224978981_1241093336.c] - Blame information for rev 9

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 9 eejlny
/**********************************************************************/
2
/*   ____  ____                                                       */
3
/*  /   /\/   /                                                       */
4
/* /___/  \  /                                                        */
5
/* \   \   \/                                                       */
6
/*  \   \        Copyright (c) 2003-2009 Xilinx, Inc.                */
7
/*  /   /          All Right Reserved.                                 */
8
/* /---/   /\                                                         */
9
/* \   \  /  \                                                      */
10
/*  \___\/\___\                                                    */
11
/***********************************************************************/
12
 
13
/* This file is designed for use with ISim build 0x7708f090 */
14
 
15
#define XSI_HIDE_SYMBOL_SPEC true
16
#include "xsi.h"
17
#include <memory.h>
18
#ifdef __GNUC__
19
#include <stdlib.h>
20
#else
21
#include <malloc.h>
22
#define alloca _alloca
23
#endif
24
static const char *ng0 = "C:/Users/eejlny/projects/xmatch_sim7/xmatch_sim7/src/sreg.vhd";
25
 
26
 
27
 
28
static void work_a_0224978981_1241093336_p_0(char *t0)
29
{
30
    char *t1;
31
    char *t2;
32
    unsigned char t3;
33
    unsigned char t4;
34
    char *t5;
35
    char *t6;
36
    char *t7;
37
    char *t8;
38
    char *t9;
39
    char *t10;
40
    unsigned char t11;
41
    unsigned char t12;
42
 
43
LAB0:    xsi_set_current_line(64, ng0);
44
    t1 = (t0 + 1352U);
45
    t2 = *((char **)t1);
46
    t3 = *((unsigned char *)t2);
47
    t4 = (t3 == (unsigned char)0);
48
    if (t4 != 0)
49
        goto LAB2;
50
 
51
LAB4:    t1 = (t0 + 1472U);
52
    t4 = xsi_signal_has_event(t1);
53
    if (t4 == 1)
54
        goto LAB7;
55
 
56
LAB8:    t3 = (unsigned char)0;
57
 
58
LAB9:    if (t3 != 0)
59
        goto LAB5;
60
 
61
LAB6:
62
LAB3:    t1 = (t0 + 3312);
63
    *((int *)t1) = 1;
64
 
65
LAB1:    return;
66
LAB2:    xsi_set_current_line(65, ng0);
67
    t1 = (t0 + 5431);
68
    t6 = (t0 + 3392);
69
    t7 = (t6 + 56U);
70
    t8 = *((char **)t7);
71
    t9 = (t8 + 56U);
72
    t10 = *((char **)t9);
73
    memcpy(t10, t1, 32U);
74
    xsi_driver_first_trans_fast_port(t6);
75
    xsi_set_current_line(66, ng0);
76
    t1 = (t0 + 5463);
77
    t5 = (t0 + 3456);
78
    t6 = (t5 + 56U);
79
    t7 = *((char **)t6);
80
    t8 = (t7 + 56U);
81
    t9 = *((char **)t8);
82
    memcpy(t9, t1, 5U);
83
    xsi_driver_first_trans_fast_port(t5);
84
    goto LAB3;
85
 
86
LAB5:    xsi_set_current_line(70, ng0);
87
    t2 = (t0 + 1032U);
88
    t6 = *((char **)t2);
89
    t2 = (t0 + 3392);
90
    t7 = (t2 + 56U);
91
    t8 = *((char **)t7);
92
    t9 = (t8 + 56U);
93
    t10 = *((char **)t9);
94
    memcpy(t10, t6, 32U);
95
    xsi_driver_first_trans_fast_port(t2);
96
    xsi_set_current_line(71, ng0);
97
    t1 = (t0 + 1192U);
98
    t2 = *((char **)t1);
99
    t1 = (t0 + 3456);
100
    t5 = (t1 + 56U);
101
    t6 = *((char **)t5);
102
    t7 = (t6 + 56U);
103
    t8 = *((char **)t7);
104
    memcpy(t8, t2, 5U);
105
    xsi_driver_first_trans_fast_port(t1);
106
    goto LAB3;
107
 
108
LAB7:    t2 = (t0 + 1512U);
109
    t5 = *((char **)t2);
110
    t11 = *((unsigned char *)t5);
111
    t12 = (t11 == (unsigned char)1);
112
    t3 = t12;
113
    goto LAB9;
114
 
115
}
116
 
117
 
118
extern void work_a_0224978981_1241093336_init()
119
{
120
        static char *pe[] = {(void *)work_a_0224978981_1241093336_p_0};
121
        xsi_register_didat("work_a_0224978981_1241093336", "isim/testbench_isim_beh.exe.sim/work/a_0224978981_1241093336.didat");
122
        xsi_register_executes(pe);
123
}

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.