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[/] [xmatchpro/] [trunk/] [xmw4-comdec/] [xmatch_sim7/] [lib/] [dzx/] [bit_utils_pkg_body.vhd] - Blame information for rev 9

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 --D  sccsid @(#)bit_utils-body.vhdl    1.2 daisy(C) 2/13/95 /files1/SCCS.model/bvhdl/vhdl_packages/dzx/src/s.bit_utils-body.vhdl
-------------------------------------------------------------------------------
--    File: Bit_Utils
--
-------------------------------------------------------------------------------
 
package body Bit_Utils is
  -- contains the subprogram definitions for subprograms declared above.
 
    ---------------------------------------------------------------------
    -- rising, falling clock edge and clock level detection functions: --
    ---------------------------------------------------------------------
 
    function Rising_Edge (signal clock_name: Bit) return Boolean is
    begin
      return (clock_name = '1') and (clock_name'event);
    end Rising_Edge;
 
    function Falling_Edge (signal clock_name: Bit) return Boolean is
    begin
      return (clock_name = '0') and (clock_name'event);
    end Falling_Edge;
 
    function High_Level (signal clock_name: Bit) return Boolean is
    begin
      return (clock_name = '1');
    end High_Level;
 
    function Low_Level (signal clock_name: Bit) return Boolean is
    begin
      return (clock_name = '0');
    end Low_Level;
 
    -------------------------
    -- Conversion routines --
    -------------------------
 
    function To_Bit (b: Boolean) return Bit is
    begin
      case b is
        when FALSE => return '0';
        when TRUE  => return '1';
      end case;
    end To_Bit;
 
    function To_Char (l: Bit) return Character is
    begin
      case l is
        when '0' => return '0';
        when '1' => return '1';
      end case;
    end To_Char;
 
    function To_String (v: Bit_Vector) return String is
      variable ret: String (v'range);
    begin
      for j in ret'range loop
        ret(j) := To_Char(v(j));
      end loop;
 
      return ret;
    end To_String;
 
 
  -----------------------------------
  -- Boolean reduction functions:  --
  -----------------------------------
  function And_Bits (v: Bit_Vector) return Bit is
    variable ret: Bit :='1';
  begin
    for j in  v'range loop
      ret := ret and v(j);
    end loop;
 
    return ret;
  end And_Bits;
 
  function Nand_Bits (v: Bit_Vector) return Bit is
  begin
    return (not And_Bits(v));
  end Nand_Bits;
 
  function Or_Bits (v: Bit_Vector) return Bit is
    variable ret: Bit := '0';
  begin
    for j in v'range loop
      ret := ret or v(j);
    end loop;
 
    return ret;
  end Or_Bits;
 
  function Nor_Bits (v: Bit_Vector) return Bit is
  begin
    return (not Or_Bits(v));
  end Nor_Bits;
 
  function Xor_Bits (v: Bit_Vector) return Bit is
    variable ret: Bit := '0';
  begin
    for j in v'range loop
      ret := ret xor v(j);
    end loop;
 
    return ret;
  end Xor_Bits;
 
  function Xnor_Bits (v: Bit_Vector) return Bit is
  begin
    return (not Xor_Bits (v));
  end Xnor_Bits;
 
  -- preset / clear procedure:
  procedure PRESET_CLEAR (signal FF: out BIT_VECTOR; PC_VALUE: BIT_VECTOR) is
  begin
    FF <= PC_VALUE;
  end;
 
  procedure PRESET_CLEAR (signal FF: out BIT; PC_VALUE: BIT) is
  begin
    FF <= PC_VALUE;
  end;
 
end Bit_Utils;
 
 

Line No.	Rev	Author	Line
1	9	eejlny
2			`--D sccsid @(#)bit_utils-body.vhdl 1.2 daisy(C) 2/13/95 /files1/SCCS.model/bvhdl/vhdl_packages/dzx/src/s.bit_utils-body.vhdl`
3			`-------------------------------------------------------------------------------`
4			`-- File: Bit_Utils`
5			`--`
6			`-------------------------------------------------------------------------------`
7
8			`package body Bit_Utils is`
9			`-- contains the subprogram definitions for subprograms declared above.`
10
11			`---------------------------------------------------------------------`
12			`-- rising, falling clock edge and clock level detection functions: --`
13			`---------------------------------------------------------------------`
14
15			`function Rising_Edge (signal clock_name: Bit) return Boolean is`
16			`begin`
17			`return (clock_name = '1') and (clock_name'event);`
18			`end Rising_Edge;`
19
20			`function Falling_Edge (signal clock_name: Bit) return Boolean is`
21			`begin`
22			`return (clock_name = '0') and (clock_name'event);`
23			`end Falling_Edge;`
24
25			`function High_Level (signal clock_name: Bit) return Boolean is`
26			`begin`
27			`return (clock_name = '1');`
28			`end High_Level;`
29
30			`function Low_Level (signal clock_name: Bit) return Boolean is`
31			`begin`
32			`return (clock_name = '0');`
33			`end Low_Level;`
34
35			`-------------------------`
36			`-- Conversion routines --`
37			`-------------------------`
38
39			`function To_Bit (b: Boolean) return Bit is`
40			`begin`
41			`case b is`
42			`when FALSE => return '0';`
43			`when TRUE => return '1';`
44			`end case;`
45			`end To_Bit;`
46
47			`function To_Char (l: Bit) return Character is`
48			`begin`
49			`case l is`
50			`when '0' => return '0';`
51			`when '1' => return '1';`
52			`end case;`
53			`end To_Char;`
54
55			`function To_String (v: Bit_Vector) return String is`
56			`variable ret: String (v'range);`
57			`begin`
58			`for j in ret'range loop`
59			`ret(j) := To_Char(v(j));`
60			`end loop;`
61
62			`return ret;`
63			`end To_String;`
64
65
66			`-----------------------------------`
67			`-- Boolean reduction functions: --`
68			`-----------------------------------`
69			`function And_Bits (v: Bit_Vector) return Bit is`
70			`variable ret: Bit :='1';`
71			`begin`
72			`for j in v'range loop`
73			`ret := ret and v(j);`
74			`end loop;`
75
76			`return ret;`
77			`end And_Bits;`
78
79			`function Nand_Bits (v: Bit_Vector) return Bit is`
80			`begin`
81			`return (not And_Bits(v));`
82			`end Nand_Bits;`
83
84			`function Or_Bits (v: Bit_Vector) return Bit is`
85			`variable ret: Bit := '0';`
86			`begin`
87			`for j in v'range loop`
88			`ret := ret or v(j);`
89			`end loop;`
90
91			`return ret;`
92			`end Or_Bits;`
93
94			`function Nor_Bits (v: Bit_Vector) return Bit is`
95			`begin`
96			`return (not Or_Bits(v));`
97			`end Nor_Bits;`
98
99			`function Xor_Bits (v: Bit_Vector) return Bit is`
100			`variable ret: Bit := '0';`
101			`begin`
102			`for j in v'range loop`
103			`ret := ret xor v(j);`
104			`end loop;`
105
106			`return ret;`
107			`end Xor_Bits;`
108
109			`function Xnor_Bits (v: Bit_Vector) return Bit is`
110			`begin`
111			`return (not Xor_Bits (v));`
112			`end Xnor_Bits;`
113
114			`-- preset / clear procedure:`
115			`procedure PRESET_CLEAR (signal FF: out BIT_VECTOR; PC_VALUE: BIT_VECTOR) is`
116			`begin`
117			`FF <= PC_VALUE;`
118			`end;`
119
120			`procedure PRESET_CLEAR (signal FF: out BIT; PC_VALUE: BIT) is`
121			`begin`
122			`FF <= PC_VALUE;`
123			`end;`
124
125			`end Bit_Utils;`
126
127

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[/] [xmatchpro/] [trunk/] [xmw4-comdec/] [xmatch_sim7/] [lib/] [dzx/] [bit_utils_pkg_body.vhd] - Blame information for rev 9