URL https://opencores.org/ocsvn/xmatchpro/xmatchpro/trunk

Subversion Repositories xmatchpro

[/] [xmatchpro/] [trunk/] [xmw4-comdec/] [xmatch_sim7/] [lib/] [xil_lib/] [xil_comp.vhd] - Blame information for rev 9

Details | Compare with Previous | View Log


library ieee;
use ieee.std_logic_1164.all;
 
package xil_comp is
  component DP_RAM_XILINX_256 IS
        port (
        addra: IN std_logic_VECTOR(7 downto 0);
        addrb: IN std_logic_VECTOR(7 downto 0);
        clka: IN std_logic;
        clkb: IN std_logic;
        dina: IN std_logic_VECTOR(31 downto 0);
        doutb: OUT std_logic_VECTOR(31 downto 0);
        enb: IN std_logic;
        wea: IN std_logic_vector(0 downto 0));
END component;
 
component DP_RAM_XILINX_512 IS
        port (
        addra: IN std_logic_VECTOR(8 downto 0);
        addrb: IN std_logic_VECTOR(8 downto 0);
        clka: IN std_logic;
        clkb: IN std_logic;
        dina: IN std_logic_VECTOR(31 downto 0);
        doutb: OUT std_logic_VECTOR(31 downto 0);
        enb: IN std_logic;
        wea: IN std_logic_vector(0 downto 0));
END component;
 
component DP_RAM_XILINX_MASK IS
        port (
        addra: IN std_logic_VECTOR(7 downto 0);
        addrb: IN std_logic_VECTOR(7 downto 0);
        clka: IN std_logic;
        clkb: IN std_logic;
        dina: IN std_logic_VECTOR(3 downto 0);
        doutb: OUT std_logic_VECTOR(3 downto 0);
        enb: IN std_logic;
        wea: IN std_logic_vector(0 downto 0));
END component;
end package;

Line No.	Rev	Author	Line
1	9	eejlny	`library ieee;`
2			`use ieee.std_logic_1164.all;`
3
4			`package xil_comp is`
5			`component DP_RAM_XILINX_256 IS`
6			`port (`
7			`addra: IN std_logic_VECTOR(7 downto 0);`
8			`addrb: IN std_logic_VECTOR(7 downto 0);`
9			`clka: IN std_logic;`
10			`clkb: IN std_logic;`
11			`dina: IN std_logic_VECTOR(31 downto 0);`
12			`doutb: OUT std_logic_VECTOR(31 downto 0);`
13			`enb: IN std_logic;`
14			`wea: IN std_logic_vector(0 downto 0));`
15			`END component;`
16
17			`component DP_RAM_XILINX_512 IS`
18			`port (`
19			`addra: IN std_logic_VECTOR(8 downto 0);`
20			`addrb: IN std_logic_VECTOR(8 downto 0);`
21			`clka: IN std_logic;`
22			`clkb: IN std_logic;`
23			`dina: IN std_logic_VECTOR(31 downto 0);`
24			`doutb: OUT std_logic_VECTOR(31 downto 0);`
25			`enb: IN std_logic;`
26			`wea: IN std_logic_vector(0 downto 0));`
27			`END component;`
28
29			`component DP_RAM_XILINX_MASK IS`
30			`port (`
31			`addra: IN std_logic_VECTOR(7 downto 0);`
32			`addrb: IN std_logic_VECTOR(7 downto 0);`
33			`clka: IN std_logic;`
34			`clkb: IN std_logic;`
35			`dina: IN std_logic_VECTOR(3 downto 0);`
36			`doutb: OUT std_logic_VECTOR(3 downto 0);`
37			`enb: IN std_logic;`
38			`wea: IN std_logic_vector(0 downto 0));`
39			`END component;`
40			`end package;`

Browse

Tools

Subversion Repositories xmatchpro

[/] [xmatchpro/] [trunk/] [xmw4-comdec/] [xmatch_sim7/] [lib/] [xil_lib/] [xil_comp.vhd] - Blame information for rev 9