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[/] [xmatchpro/] [trunk/] [xmw4-comdec/] [xmatch_sim7/] [src/] [input_counter_9bits.vhd] - Blame information for rev 9

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1 9 eejlny
--This library is free software; you can redistribute it and/or
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--modify it under the terms of the GNU Lesser General Public
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--License as published by the Free Software Foundation; either
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--version 2.1 of the License, or (at your option) any later version.
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--This library is distributed in the hope that it will be useful,
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--but WITHOUT ANY WARRANTY; without even the implied warranty of
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--MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
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--Lesser General Public License for more details.
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--You should have received a copy of the GNU Lesser General Public
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--License along with this library; if not, write to the Free Software
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--Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301  USA
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-- e_mail : j.l.nunez-yanez@byacom.co.uk
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-------------------------------------------------
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--  ENTITY       = INPUT_COUNTER                   --
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--  version      = 1.0                         --
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--  last update  = 30/5/01                     --
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--  author       = Jose Nunez                  --
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-------------------------------------------------
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-- FUNCTION
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-- 8 bit counter for the read and write of the input buffer
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--  PIN LIST
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--  ENABLE = enable count 
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--  CLEAR = asyncronus clear of the counter
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--  CLEAR_COUNTERS : syncronous clear of counters
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--  CLK   = master clock
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--  COUNT = count output
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library ieee,dzx;
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use ieee.std_logic_1164.all;
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use dzx.bit_arith.all;
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use dzx.bit_utils.all;
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entity INPUT_COUNTER_9BITS is
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port (ENABLE : in bit;
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          CLEAR : in bit;
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          CLEAR_COUNTERS : in bit;
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          CLK : in bit;
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          COUNT : out bit_vector(8 downto 0)
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     );
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end INPUT_COUNTER_9BITS;
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architecture STRUCTURAL of INPUT_COUNTER_9BITS is
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signal COUNT_AUX : bit_vector(8 downto 0);
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begin
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COUNTING : process (CLK,CLEAR,ENABLE,CLEAR_COUNTERS)
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begin
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        -- asynchronous RESET signal forces all outputs LOW
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      if (CLEAR = '0') then
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            COUNT_AUX <= "000000000";
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            -- check for +ve clock edge
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          elsif ((CLK'event) and (CLK = '1')) then
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                    if (CLEAR_COUNTERS = '1') then
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                               COUNT_AUX <= "000000000";
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                  elsif( ENABLE = '1') then
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                           COUNT_AUX <= COUNT_AUX+"000000001";
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                          else
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                               COUNT_AUX <= COUNT_AUX;
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                          end if;
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         end if;
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end process COUNTING;
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COUNT <= COUNT_AUX;
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end STRUCTURAL;

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