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--This library is free software; you can redistribute it and/or
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--modify it under the terms of the GNU Lesser General Public
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--License as published by the Free Software Foundation; either
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--version 2.1 of the License, or (at your option) any later version.
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--This library is distributed in the hope that it will be useful,
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--but WITHOUT ANY WARRANTY; without even the implied warranty of
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--MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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--Lesser General Public License for more details.
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--You should have received a copy of the GNU Lesser General Public
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--License along with this library; if not, write to the Free Software
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--Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
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-- e_mail : j.l.nunez-yanez@byacom.co.uk
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-------------------------------------
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-- ENTITY = MLD_LOGIC_3_2_2 --
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-- version = 1.0 --
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-- last update = 2/04/01 --
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-- author = Jose Nunez --
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-------------------------------------
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-- FUNCTION
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-- Match location decision logic.
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-- This reads in the match types from each location in the CAM array
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-- and decides which location provides the best hit in terms of the
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-- minimum number of code bits output.
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-- This is part 2 and solves the best match
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-- PIN LIST
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-- DOWN_PRIORITY_6/5/4/3/2/1 = these are the priorities that have been propagated
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-- SAME_LENGTH = same length in data word and search word
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-- MATCH_TYPE_A,B,C,D = It seems necessary to also pipeline the match_type
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-- COLUMN_OR = the result of the or of each column
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-- MATCH_LOC = location of the best match.
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-- MATCH_TYPE = match type of the location with the best match.
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library ieee,dzx;
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use ieee.std_logic_1164.all;
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use dzx.bit_utils.all;
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entity MLD_LOGIC_3_2_2 is
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port
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(
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MASK : in bit_vector(4 downto 0);
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DOWN_PRIORITY_6 : in bit_vector(15 downto 0) ;
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DOWN_PRIORITY_5 : in bit_vector(15 downto 0) ;
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DOWN_PRIORITY_4 : in bit_vector(15 downto 0) ;
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DOWN_PRIORITY_3 : in bit_vector(15 downto 0) ;
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DOWN_PRIORITY_2 : in bit_vector(15 downto 0) ;
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DOWN_PRIORITY_1 : in bit_vector(15 downto 0) ;
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SAME_LENGTH_2 : in bit_vector(15 downto 0);
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SAME_LENGTH_3 : in bit_vector(15 downto 0);
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SAME_LENGTH_4 : in bit_vector(15 downto 0);
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MATCH_TYPE_A : in bit_vector(15 downto 0);
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MATCH_TYPE_B : in bit_vector(15 downto 0);
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MATCH_TYPE_C : in bit_vector(15 downto 0);
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MATCH_TYPE_D : in bit_vector(15 downto 0);
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COLUMN_OR : in bit_vector(6 downto 1);
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MATCH_LOC : out bit_vector(15 downto 0) ;
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MATCH_TYPE : out bit_vector(3 downto 0)
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);
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end MLD_LOGIC_3_2_2;
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architecture DECIDE_3 of MLD_LOGIC_3_2_2 is
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-- a single drop down unit
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component MLD_DPROP
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port
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(
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DIN : in bit_vector(0 to 15);
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DOUT : out bit_vector(0 to 15);
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FULL_OR : out bit
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);
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end component;
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type MTYPE_ARRAY is array(0 to 15) of bit_vector(3 downto 0);
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type PRI_ARRAY is array(0 to 15) of bit_vector(6 downto 1);
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type PRI_TRANS_ARRAY is array(6 downto 1) of bit_vector(0 to 15);
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signal SECOND_TRANS_PRI : PRI_TRANS_ARRAY;
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signal THIRD_TRANS_PRI : PRI_TRANS_ARRAY;
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signal LOCATION : bit_vector(15 downto 0);
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signal LOCATION_INT : bit_vector(15 downto 0);
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signal LOCATION_INT_AUX : bit_vector(15 downto 0);
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signal SECOND_COLUMN_OR : bit_vector(6 downto 1);
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signal MATCH_TYPE_AUX : bit_vector(3 downto 0);
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signal MATCH_TYPE_INT : bit_vector(3 downto 0);
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signal FULL_MATCH_AUX_2 : bit;
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signal FULL_MATCH_AUX_3 : bit;
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signal FULL_MATCH_AUX_4 : bit;
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signal FULL_MATCH_INT : bit;
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signal FULL_TUPLE : bit_vector(15 downto 0);
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begin
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FULL_TUPLE <= x"FFFF" when MASK(1) = '1' else x"0000";
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-- MASK[1] tuple complete consider partial match
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SECOND_TRANS_PRI(6) <= DOWN_PRIORITY_6 and (FULL_TUPLE or SAME_LENGTH_4); -- the length must be the same to consider the match. Partial words can only generate full matches
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SECOND_TRANS_PRI(5) <= DOWN_PRIORITY_5 and (FULL_TUPLE or SAME_LENGTH_3);
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SECOND_TRANS_PRI(4) <= DOWN_PRIORITY_4;
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SECOND_TRANS_PRI(3) <= DOWN_PRIORITY_3;
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SECOND_TRANS_PRI(2) <= DOWN_PRIORITY_2 and (FULL_TUPLE or SAME_LENGTH_2);
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SECOND_TRANS_PRI(1) <= DOWN_PRIORITY_1;
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-- or generation logic
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SECOND_COLUMN_OR(6) <= COLUMN_OR(6);
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SECOND_COLUMN_OR(5) <= not(COLUMN_OR(6)) and COLUMN_OR(5);
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SECOND_COLUMN_OR(4) <= Nor_Bits(COLUMN_OR(6 downto 5))and COLUMN_OR(4);
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SECOND_COLUMN_OR(3) <= Nor_Bits(COLUMN_OR(6 downto 4)) and COLUMN_OR(3);
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SECOND_COLUMN_OR(2) <= Nor_Bits(COLUMN_OR(6 downto 3)) and COLUMN_OR(2);
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SECOND_COLUMN_OR(1) <= Nor_Bits(COLUMN_OR(6 downto 2)) and COLUMN_OR(1);
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ACROSS_PROP : process (SECOND_COLUMN_OR , SECOND_TRANS_PRI)
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begin
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for I in 5 downto 1 loop
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for J in 0 to 15 loop
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THIRD_TRANS_PRI(I)(J) <= SECOND_TRANS_PRI(I)(J) and SECOND_COLUMN_OR(I);
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end loop;
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end loop;
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THIRD_TRANS_PRI(6) <= SECOND_TRANS_PRI(6);
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end process ACROSS_PROP;
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LOCATION_DECIDE : process (THIRD_TRANS_PRI)
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begin
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for I in 0 to 15 loop
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LOCATION(15-I) <= (THIRD_TRANS_PRI(6)(I) or THIRD_TRANS_PRI(5)(I) or THIRD_TRANS_PRI(4)(I)) or (THIRD_TRANS_PRI(3)(I) or THIRD_TRANS_PRI(2)(I) or THIRD_TRANS_PRI(1)(I));
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end loop;
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end process LOCATION_DECIDE;
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DROP_DOWN : MLD_DPROP port map ( DIN => LOCATION,
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DOUT => LOCATION_INT,
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FULL_OR => open );
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TRANSPOSE : process(LOCATION_INT)
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begin
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for I in 0 to 15 loop
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LOCATION_INT_AUX(15-I) <= LOCATION_INT(I);
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end loop;
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end process;
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MUX : process (LOCATION_INT_AUX , MATCH_TYPE_A, MATCH_TYPE_B, MATCH_TYPE_C, MATCH_TYPE_D)
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variable MATCH_TYPE_A_TEMP : bit_vector(15 downto 0);
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variable MATCH_TYPE_B_TEMP : bit_vector(15 downto 0);
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variable MATCH_TYPE_C_TEMP : bit_vector(15 downto 0);
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variable MATCH_TYPE_D_TEMP : bit_vector(15 downto 0);
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begin
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for I in 0 to 15 loop
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MATCH_TYPE_A_TEMP(I) := MATCH_TYPE_A(I) or LOCATION_INT_AUX(I);
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MATCH_TYPE_B_TEMP(I) := MATCH_TYPE_B(I) or LOCATION_INT_AUX(I);
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MATCH_TYPE_C_TEMP(I) := MATCH_TYPE_C(I) or LOCATION_INT_AUX(I);
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MATCH_TYPE_D_TEMP(I) := MATCH_TYPE_D(I) or LOCATION_INT_AUX(I);
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end loop;
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MATCH_TYPE_AUX(3) <= And_Bits(MATCH_TYPE_A_TEMP);
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MATCH_TYPE_AUX(2) <= And_Bits(MATCH_TYPE_B_TEMP);
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MATCH_TYPE_AUX(1) <= And_Bits(MATCH_TYPE_C_TEMP);
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MATCH_TYPE_AUX(0) <= And_Bits(MATCH_TYPE_D_TEMP);
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end process MUX;
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-- active high same length
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FULL_MATCH_AUX_2 <= or_bits(SAME_LENGTH_2 and DOWN_PRIORITY_2);
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FULL_MATCH_AUX_3 <= or_bits(SAME_LENGTH_3 and DOWN_PRIORITY_5);
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FULL_MATCH_AUX_4 <= or_bits(SAME_LENGTH_4 and DOWN_PRIORITY_6);
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-- promote match type to total (15) when lengths are equal and inverted match type is 15,14 or 12;
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MATCH_TYPE_PROMOTION: process(MATCH_TYPE_AUX, FULL_MATCH_AUX_2,FULL_MATCH_AUX_3,FULL_MATCH_AUX_4)
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begin
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case MATCH_TYPE_AUX is
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when "0000" =>
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if FULL_MATCH_AUX_4 = '1' then
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MATCH_TYPE_INT <= "0000";
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else
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MATCH_TYPE_INT <= MATCH_TYPE_AUX;
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end if;
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when "0001" =>
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if FULL_MATCH_AUX_3 = '1' then
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MATCH_TYPE_INT <= "0000";
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else
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MATCH_TYPE_INT <= MATCH_TYPE_AUX;
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end if;
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when "0011" =>
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if FULL_MATCH_AUX_2 = '1' then
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MATCH_TYPE_INT <= "0000";
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else
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MATCH_TYPE_INT <= MATCH_TYPE_AUX;
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end if;
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when others =>
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MATCH_TYPE_INT <= MATCH_TYPE_AUX;
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end case;
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end process MATCH_TYPE_PROMOTION;
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FULL_MATCH_INT <= '0' when MATCH_TYPE_INT = "0000" else '1';
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MATCH_TYPE <= MATCH_TYPE_INT;
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MATCH_LOC <= LOCATION_INT_AUX;
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end DECIDE_3;
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