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[/] [xmatchpro/] [trunk/] [xmw4-comdec/] [xmatch_sim7/] [src/] [reg_temp.vhd] - Blame information for rev 9

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1 9 eejlny
--This library is free software; you can redistribute it and/or
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--modify it under the terms of the GNU Lesser General Public
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--License as published by the Free Software Foundation; either
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--version 2.1 of the License, or (at your option) any later version.
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--This library is distributed in the hope that it will be useful,
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--but WITHOUT ANY WARRANTY; without even the implied warranty of
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--MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
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--Lesser General Public License for more details.
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--You should have received a copy of the GNU Lesser General Public
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--License along with this library; if not, write to the Free Software
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--Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301  USA
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-- e_mail : j.l.nunez-yanez@byacom.co.uk
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---------------------------------
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--  ENTITY       = REG_TEMP     --
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--  version      = 1.0         --
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--  last update  = 21/08/00    --
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--  author       = Jose Nunez  --
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---------------------------------
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library ieee,dzx;
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use ieee.std_logic_1164.all;
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use dzx.attributes.all;
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use dzx.bit_utils.all;
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entity REG_TEMP is
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port
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(
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      DATA_IN : in bit_vector(31 downto 0) ;
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      MASK_IN : in bit_vector(3 downto 0) ;
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      CLK : in bit ;
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          CLEAR : in bit ;
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          RESET : in bit;
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                ENABLE : in bit;
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          DATA_OUT : out std_logic_vector(31 downto 0);
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          MASK_OUT : out std_logic_vector(3 downto 0)
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);
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    end REG_TEMP;
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architecture LATCH of REG_TEMP is
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signal QOUT : bit_vector(31 downto 0);
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signal MOUT : bit_vector(3 downto 0);
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begin
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FLIP_FLOPS : process (CLK,CLEAR)
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begin
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        -- asynchronous RESET signal forces all outputs LOW
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        if (CLEAR = '0') then
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               QOUT <= x"00000000";
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                   MOUT <= "1111";
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          -- check for +ve clock edge
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          elsif ((CLK'event) and (CLK = '1')) then
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          -- check for synchronous clear signal
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                 if (RESET = '0') then
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               QOUT <= x"00000000";
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                   MOUT <= "1111";
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                 elsif (ENABLE = '0') then
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                         QOUT <= DATA_IN;
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                         MOUT <= MASK_IN;
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                else
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                                 QOUT <= QOUT;
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                                MOUT <= MOUT;
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                 end if;
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           end if;
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end process FLIP_FLOPS;
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DATA_OUT <= To_X01Z(QOUT);
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MASK_OUT <= To_X01Z(MOUT);
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end LATCH;
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