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[/] [xucpu/] [trunk/] [target/] [Xilinx/] [1k/] [functional.wcfg] - Blame information for rev 41

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      clock
      clock
   
   
      reset
      reset
   
   
      sys_clk
      sys_clk
   
   
      sys_rst
      sys_rst
   
   
      int_rst
      int_rst
   
   
      addr_out[14:0]
      addr_out[14:0]
   
   
      address[14:0]
      address[14:0]
   
   
      clka
      clka
   
   
      addra[14:0]
      addra[14:0]
   
   
      douta[15:0]
      douta[15:0]
   
   
      databus_in[15:0]
      databus_in[15:0]
   
   
      data_in[15:0]
      data_in[15:0]
   
   
      d_ir_load
      d_ir_load
   
   
      ir[15:0]
      ir[15:0]
   
   
      state
      state
   
   
      data_in[15:0]
      data_in[15:0]
   
   
      we
      we
   
   
      register_file[0:31]
      register_file[0:31]
   
   
      pc[14:0]
      pc[14:0]
   
   
      addr_out_reg[14:0]
      addr_out_reg[14:0]
   
   
      data_out_reg[15:0]
      data_out_reg[15:0]
   
   
      a[15:0]
      a[15:0]
   
   
      b[15:0]
      b[15:0]
   


Line No.	Rev	Author	Line
1	4	lcdsgmtr
2
3
4
5
6
7
8
9
10
11
12
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14
15
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18
19
20
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22
23
24
25			`clock`
26			`clock`
27
28
29			`reset`
30			`reset`
31
32
33			`sys_clk`
34			`sys_clk`
35
36
37			`sys_rst`
38			`sys_rst`
39
40
41			`int_rst`
42			`int_rst`
43
44
45			`addr_out[14:0]`
46			`addr_out[14:0]`
47
48
49			`address[14:0]`
50			`address[14:0]`
51
52
53			`clka`
54			`clka`
55
56
57			`addra[14:0]`
58			`addra[14:0]`
59
60
61			`douta[15:0]`
62			`douta[15:0]`
63
64
65			`databus_in[15:0]`
66			`databus_in[15:0]`
67
68
69			`data_in[15:0]`
70			`data_in[15:0]`
71
72
73			`d_ir_load`
74			`d_ir_load`
75
76
77			`ir[15:0]`
78			`ir[15:0]`
79
80
81			`state`
82			`state`
83
84
85			`data_in[15:0]`
86			`data_in[15:0]`
87
88
89			`we`
90			`we`
91
92
93			`register_file[0:31]`
94			`register_file[0:31]`
95
96
97			`pc[14:0]`
98			`pc[14:0]`
99
100
101			`addr_out_reg[14:0]`
102			`addr_out_reg[14:0]`
103
104
105			`data_out_reg[15:0]`
106			`data_out_reg[15:0]`
107
108
109			`a[15:0]`
110			`a[15:0]`
111
112
113			`b[15:0]`
114			`b[15:0]`
115
116

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[/] [xucpu/] [trunk/] [target/] [Xilinx/] [1k/] [functional.wcfg] - Blame information for rev 41