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Subversion Repositories xucpu

[/] [xucpu/] [trunk/] [target/] [Xilinx/] [1k/] [iseconfig/] [xucpu.projectmgr] - Blame information for rev 41

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         2
         /RAM32K - Structural |home|jurgen|Projects|xucpu|src|components|BRAM|RAM.vhdl
         /clock_gen - Behavioral |home|jurgen|Projects|xucpu|src|system|clock.vhdl
         /mux32to1 - Behavioral |home|jurgen|Projects|xucpu|src|components|multiplexer|MUX.vhdl
         /summation - Behavioral |home|jurgen|Projects|xucpu|src|components|ALU|summation.vhdl
         /system - Structural |home|jurgen|Projects|xucpu|src|system|system.vhdl
      
      
         system - Structural (/home/jurgen/Projects/xucpu/src/system/system.vhdl)
      
      1
      0
      000000ff00000000000000010000000100000000000000000000000000000000020200000001000000010000006400000294000000020000000000000000000000000200000064ffffffff000000810000000300000002000002940000000100000003000000000000000100000003
      true
      system - Structural (/home/jurgen/Projects/xucpu/src/system/system.vhdl)
   
   
      
         1
         Design Utilities
      
      
         
      
      0
      0
      000000ff0000000000000001000000010000000000000000000000000000000000000000000000011f000000010000000100000000000000000000000064ffffffff0000008100000000000000010000011f0000000100000000
      false
      
   
   
      
         1
      
      
      0
      0
      000000ff00000000000000010000000000000000010000000000000000000000000000000000000392000000040101000100000000000000000000000064ffffffff000000810000000000000004000001cc0000000100000000000000d00000000100000000000000840000000100000000000000720000000100000000
      false
      /home/jurgen/Projects/xucpu/src/components/ALU/alu2.vhdl
   
   
      
         1
         work
      
      
      0
      0
      000000ff00000000000000010000000000000000010000000000000000000000000000000000000121000000010001000100000000000000000000000064ffffffff000000810000000000000001000001210000000100000000
      false
      work
   
   
      
         1
         Configure Target Device
         Design Utilities
         Implement Design/Map
         Implement Design/Place & Route/Back-annotate Pin Locations
         Implement Design/Place & Route/Generate IBIS Model
         Implement Design/Translate
         User Constraints
      
      
         
      
      0
      0
      000000ff0000000000000001000000010000000000000000000000000000000000000000000000010f000000010000000100000000000000000000000064ffffffff0000008100000000000000010000010f0000000100000000
      false
      
   
   
      
         1
         User Constraints
      
      
         
      
      0
      0
      000000ff0000000000000001000000010000000000000000000000000000000000000000000000011f000000010000000100000000000000000000000064ffffffff0000008100000000000000010000011f0000000100000000
      false
      
   
   
      
         2
         /RAM32K - Structural |home|jurgen|Projects|xucpu|src|components|BRAM|RAM.vhdl
         /clock_gen - Behavioral |home|jurgen|Projects|xucpu|src|system|clock.vhdl
         /mux32to1 - Behavioral |home|jurgen|Projects|xucpu|src|components|multiplexer|MUX.vhdl
         /startup_sim - behavior |home|jurgen|Projects|xucpu|tb|startup_sim.vhdl
         /summation - Behavioral |home|jurgen|Projects|xucpu|src|components|ALU|summation.vhdl
      
      
         Unassigned User Library Modules
      
      0
      0
      000000ff00000000000000010000000100000000000000000000000000000000020200000001000000010000006400000294000000020000000000000000000000000200000064ffffffff000000810000000300000002000002940000000100000003000000000000000100000003
      false
      Unassigned User Library Modules
   
   
      
         1
         Design Utilities
      
      
         
      
      0
      0
      000000ff0000000000000001000000010000000000000000000000000000000000000000000000011f000000010000000100000000000000000000000064ffffffff0000008100000000000000010000011f0000000100000000
      false
      
   
   
      
         2
         /startup_sim - behavior |home|jurgen|Projects|xucpu|tb|startup_sim.vhdl/uut - system - Structure
      
      
         startup_sim - behavior (/home/jurgen/Projects/xucpu/tb/startup_sim.vhdl)
      
      0
      0
      000000ff000000000000000100000001000000000000000000000000000000000202000000010000000100000064000002c0000000020000000000000000000000000200000064ffffffff000000810000000300000002000002c00000000100000003000000000000000100000003
      false
      startup_sim - behavior (/home/jurgen/Projects/xucpu/tb/startup_sim.vhdl)
   
   
      
         1
         Design Utilities
      
      
         
      
      0
      0
      000000ff0000000000000001000000010000000000000000000000000000000000000000000000011f000000010000000100000000000000000000000064ffffffff0000008100000000000000010000011f0000000100000000
      false
      
   
   
      
         1
      
      
         ISim Simulator
      
      0
      0
      000000ff0000000000000001000000010000000000000000000000000000000000000000000000011f000000010000000100000000000000000000000064ffffffff0000008100000000000000010000011f0000000100000000
      false
      ISim Simulator
   
   000000ff0000000000000002000001490000012001000000060100000002
   Implementation
   


Line No.	Rev	Author	Line
1	28	lcdsgmtr
2
3
4
5
6
7
8
9			`2`
10			`/RAM32K - Structural \|home\|jurgen\|Projects\|xucpu\|src\|components\|BRAM\|RAM.vhdl`
11			`/clock_gen - Behavioral \|home\|jurgen\|Projects\|xucpu\|src\|system\|clock.vhdl`
12			`/mux32to1 - Behavioral \|home\|jurgen\|Projects\|xucpu\|src\|components\|multiplexer\|MUX.vhdl`
13			`/summation - Behavioral \|home\|jurgen\|Projects\|xucpu\|src\|components\|ALU\|summation.vhdl`
14			`/system - Structural \|home\|jurgen\|Projects\|xucpu\|src\|system\|system.vhdl`
15
16
17			`system - Structural (/home/jurgen/Projects/xucpu/src/system/system.vhdl)`
18
19			`1`
20			`0`
21			`000000ff00000000000000010000000100000000000000000000000000000000020200000001000000010000006400000294000000020000000000000000000000000200000064ffffffff000000810000000300000002000002940000000100000003000000000000000100000003`
22			`true`
23			`system - Structural (/home/jurgen/Projects/xucpu/src/system/system.vhdl)`
24
25
26
27			`1`
28			`Design Utilities`
29
30
31
32
33			`0`
34			`0`
35			`000000ff0000000000000001000000010000000000000000000000000000000000000000000000011f000000010000000100000000000000000000000064ffffffff0000008100000000000000010000011f0000000100000000`
36			`false`
37
38
39
40
41			`1`
42
43
44			`0`
45			`0`
46			`000000ff00000000000000010000000000000000010000000000000000000000000000000000000392000000040101000100000000000000000000000064ffffffff000000810000000000000004000001cc0000000100000000000000d00000000100000000000000840000000100000000000000720000000100000000`
47			`false`
48			`/home/jurgen/Projects/xucpu/src/components/ALU/alu2.vhdl`
49
50
51
52			`1`
53			`work`
54
55
56			`0`
57			`0`
58			`000000ff00000000000000010000000000000000010000000000000000000000000000000000000121000000010001000100000000000000000000000064ffffffff000000810000000000000001000001210000000100000000`
59			`false`
60			`work`
61
62
63
64			`1`
65			`Configure Target Device`
66			`Design Utilities`
67			`Implement Design/Map`
68			`Implement Design/Place & Route/Back-annotate Pin Locations`
69			`Implement Design/Place & Route/Generate IBIS Model`
70			`Implement Design/Translate`
71			`User Constraints`
72
73
74
75
76			`0`
77			`0`
78			`000000ff0000000000000001000000010000000000000000000000000000000000000000000000010f000000010000000100000000000000000000000064ffffffff0000008100000000000000010000010f0000000100000000`
79			`false`
80
81
82
83
84			`1`
85			`User Constraints`
86
87
88
89
90			`0`
91			`0`
92			`000000ff0000000000000001000000010000000000000000000000000000000000000000000000011f000000010000000100000000000000000000000064ffffffff0000008100000000000000010000011f0000000100000000`
93			`false`
94
95
96
97
98			`2`
99			`/RAM32K - Structural \|home\|jurgen\|Projects\|xucpu\|src\|components\|BRAM\|RAM.vhdl`
100			`/clock_gen - Behavioral \|home\|jurgen\|Projects\|xucpu\|src\|system\|clock.vhdl`
101			`/mux32to1 - Behavioral \|home\|jurgen\|Projects\|xucpu\|src\|components\|multiplexer\|MUX.vhdl`
102			`/startup_sim - behavior \|home\|jurgen\|Projects\|xucpu\|tb\|startup_sim.vhdl`
103			`/summation - Behavioral \|home\|jurgen\|Projects\|xucpu\|src\|components\|ALU\|summation.vhdl`
104
105
106			`Unassigned User Library Modules`
107
108			`0`
109			`0`
110			`000000ff00000000000000010000000100000000000000000000000000000000020200000001000000010000006400000294000000020000000000000000000000000200000064ffffffff000000810000000300000002000002940000000100000003000000000000000100000003`
111			`false`
112			`Unassigned User Library Modules`
113
114
115
116			`1`
117			`Design Utilities`
118
119
120
121
122			`0`
123			`0`
124			`000000ff0000000000000001000000010000000000000000000000000000000000000000000000011f000000010000000100000000000000000000000064ffffffff0000008100000000000000010000011f0000000100000000`
125			`false`
126
127
128
129
130			`2`
131			`/startup_sim - behavior \|home\|jurgen\|Projects\|xucpu\|tb\|startup_sim.vhdl/uut - system - Structure`
132
133
134			`startup_sim - behavior (/home/jurgen/Projects/xucpu/tb/startup_sim.vhdl)`
135
136			`0`
137			`0`
138			`000000ff000000000000000100000001000000000000000000000000000000000202000000010000000100000064000002c0000000020000000000000000000000000200000064ffffffff000000810000000300000002000002c00000000100000003000000000000000100000003`
139			`false`
140			`startup_sim - behavior (/home/jurgen/Projects/xucpu/tb/startup_sim.vhdl)`
141
142
143
144			`1`
145			`Design Utilities`
146
147
148
149
150			`0`
151			`0`
152			`000000ff0000000000000001000000010000000000000000000000000000000000000000000000011f000000010000000100000000000000000000000064ffffffff0000008100000000000000010000011f0000000100000000`
153			`false`
154
155
156
157
158			`1`
159
160
161			`ISim Simulator`
162
163			`0`
164			`0`
165			`000000ff0000000000000001000000010000000000000000000000000000000000000000000000011f000000010000000100000000000000000000000064ffffffff0000008100000000000000010000011f0000000100000000`
166			`false`
167			`ISim Simulator`
168
169			`000000ff0000000000000002000001490000012001000000060100000002`
170			`Implementation`
171
172

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Subversion Repositories xucpu

[/] [xucpu/] [trunk/] [target/] [Xilinx/] [1k/] [iseconfig/] [xucpu.projectmgr] - Blame information for rev 41