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[/] [xucpu/] [trunk/] [target/] [Xilinx/] [1k/] [post_route.wcfg] - Blame information for rev 41

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      clock
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      clock
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      reset
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      reset
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      sys_clk
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      sys_clk
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      sys_rst
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      sys_rst
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      int_rst
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      int_rst
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      addr_out[14:0]
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      addr_out[14:0]
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      address[14:0]
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      address[14:0]
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      addra[13:0]
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      addra[13:0]
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      databus_in[15:0]
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      databus_in[15:0]
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      data_in[15:0]
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      data_in[15:0]
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      data_in[15:0]
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      data_in[15:0]
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      reg_a[3:0]
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      reg_a[3:0]
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      reg_b[3:0]
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      reg_b[3:0]
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      op_sel[3:0]
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      op_sel[3:0]
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      we
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      we
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      y[15:0]
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      y[15:0]
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      pc[14:0]
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      pc[14:0]
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      addr_out_reg[14:0]
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      addr_out_reg[14:0]
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      data_out_reg[15:0]
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      data_out_reg[15:0]
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      a[15:0]
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      b[15:0]
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      b[15:0]
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